From patchwork Sun Jun 28 15:39:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 222992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D54FCC433DF for ; Sun, 28 Jun 2020 15:39:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ACE28206F2 for ; Sun, 28 Jun 2020 15:39:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Jyffb/+x" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726002AbgF1Pjo (ORCPT ); Sun, 28 Jun 2020 11:39:44 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:25198 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725970AbgF1Pjo (ORCPT ); Sun, 28 Jun 2020 11:39:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593358782; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/T+n/WMSXGYQh59L/TuX8qKl/A0OCCf7D9e+yxcaST8=; b=Jyffb/+xfGDNkSrezdz2ETCEFNPhhTSNjM52+Ngr/NS5HxVg24SvFaxAE57nCSZSDNWNw6 hURcgrNvQVcm9YPo0f7PAV1IdFcAC+15pnTKNKY4+Q7bXAYci/xFItdVNjhbBBBpAX2I8y kmiWW1jsMRFOfD+mdnwopL52UkCOYd4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-26-4ukXpm18Mj6zIPXoXD6WzA-1; Sun, 28 Jun 2020 11:39:40 -0400 X-MC-Unique: 4ukXpm18Mj6zIPXoXD6WzA-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2EEA080400C; Sun, 28 Jun 2020 15:39:39 +0000 (UTC) Received: from x1.localdomain.com (ovpn-112-41.ams2.redhat.com [10.36.112.41]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7F252289B5; Sun, 28 Jun 2020 15:39:37 +0000 (UTC) From: Hans de Goede To: Cezary Rojewski , Pierre-Louis Bossart , Liam Girdwood , Jie Yang , Mark Brown , Oder Chiou Cc: Hans de Goede , alsa-devel@alsa-project.org, stable@vger.kernel.org Subject: [PATCH 2/6] ASoC: rt5670: Correct RT5670_LDO_SEL_MASK Date: Sun, 28 Jun 2020 17:39:29 +0200 Message-Id: <20200628153933.70538-2-hdegoede@redhat.com> In-Reply-To: <20200628153933.70538-1-hdegoede@redhat.com> References: <20200628153933.70538-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The RT5670_PWR_ANLG1 register has 3 bits to select the LDO voltage, so the correct mask is 0x7 not 0x3. Because of this wrong mask we were programming the ldo bits to a setting of binary 001 (0x05 & 0x03) instead of binary 101 when moving to SND_SOC_BIAS_PREPARE. According to the datasheet 001 is a reserved value, so no idea what it did, since the driver was working fine before I guess we got lucky and it does something which is ok. Fixes: 5e8351de740d ("ASoC: add RT5670 CODEC driver") Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede --- sound/soc/codecs/rt5670.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/rt5670.h b/sound/soc/codecs/rt5670.h index a8c3e44770b8..de0203369b7c 100644 --- a/sound/soc/codecs/rt5670.h +++ b/sound/soc/codecs/rt5670.h @@ -757,7 +757,7 @@ #define RT5670_PWR_VREF2_BIT 4 #define RT5670_PWR_FV2 (0x1 << 3) #define RT5670_PWR_FV2_BIT 3 -#define RT5670_LDO_SEL_MASK (0x3) +#define RT5670_LDO_SEL_MASK (0x7) #define RT5670_LDO_SEL_SFT 0 /* Power Management for Analog 2 (0x64) */