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[209.132.180.67]) by mx.google.com with ESMTP id y38si1460090plh.332.2017.09.20.07.51.30; Wed, 20 Sep 2017 07:51:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=I69SpOdb; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751797AbdITOv2 (ORCPT + 6 others); Wed, 20 Sep 2017 10:51:28 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:50416 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751709AbdITOv0 (ORCPT ); Wed, 20 Sep 2017 10:51:26 -0400 Received: by mail-wm0-f48.google.com with SMTP id v142so7929482wmv.5 for ; Wed, 20 Sep 2017 07:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=I69SpOdbO2RvEsZ9S+sl0cMfbSb+Dd0V2swRkrpyf+7pPxHdAnqUuRvkD63NwfVufC CHbzc5nKj/nPU5MVgukR7WfG0g+dUxgsFaj906Z12+Tzp6k8c8dcQmvgxodSo/6tDfLj 23yi0K+eXujARNgHI/03A2ERWBN5PE5D5lyl8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=baJrxhouPX8QaI7JqMYh4dCnkpn64ajYcNnBkmBIws8D2NvRC+QEZTopQeLgnICA0b cop9xuoIhUpGBRwnPsAlz2y7vCO6zmUSTP2OuHK06/cZ9Knz9rxDWs4VuOiQ0vCi9g3L JbKJcnnsBTx34bYg5YopJsReATsFGy+RXd3GBYBHK5bNYPoF532aHaONTsvwHun0VDCu Cn2OIDGjebQzdVsf/VeyFm0RG4paRwl+8NP8gVXscruUfx1/lTFkRfOz+4yR3ehMmaRv vfftIcHZd30Z4zkAoB/TQ/8pC6FWuO756dbPwaVBo1FZW+1FBdwxNQWrwVtfpa8yvcJt 2QTQ== X-Gm-Message-State: AHPjjUjQP+9kTJ2q0Bkbe0fci9NAd98FP+zgMTS0IWKFtnmDZufqTgZC 1Vv58zuyBBbSGwfbo/ZDX+WMOA== X-Google-Smtp-Source: AOwi7QBj7qeQoNV38bqxJiFUeyYNzyrJt60qXZYVc2wT/b1N70DWQdBAFPEgNdawAIFQnHh4cND8uw== X-Received: by 10.28.212.65 with SMTP id l62mr4117216wmg.77.1505919084951; Wed, 20 Sep 2017 07:51:24 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.203.94]) by smtp.gmail.com with ESMTPSA id z108sm2088197wrc.49.2017.09.20.07.51.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Sep 2017 07:51:24 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v3 2/2] arm: dts: stm32: remove useless clocksource nodes Date: Wed, 20 Sep 2017 16:51:07 +0200 Message-Id: <1505919067-28041-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505919067-28041-1-git-send-email-benjamin.gaignard@linaro.org> References: <1505919067-28041-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index a8113dc..fd211cb 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 4506eb9..c4d0273 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;