From patchwork Tue Sep 19 18:47:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 113053 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5259367qgf; Tue, 19 Sep 2017 11:48:16 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCvzNuB3HE+jdSZ574Bog6i+/4udTxwQwhD1wY1L6YSpdiacVzxFO/dn7o79V/bLTU3y+Nv X-Received: by 10.84.129.193 with SMTP id b59mr2096197plb.76.1505846896568; Tue, 19 Sep 2017 11:48:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505846896; cv=none; d=google.com; s=arc-20160816; b=PNZh+hAIhhG7/FM6zvI/mJ5nFX7PXVs7twbyXbhS/PkV96anVMLvVbpAp1dfBmpnVT O7+x/N5FN6c4cEXb0A/CroClYFTylNOoTNZc26Ns4SpzTNPn3scUkRa659wcyScmqoZa Rc/vwaCMaVxAurWij2MDWRBk0j0s3gTw9yub3Rkcg0h2FgiNalu6LX35nhka9hKhLnE/ 10ObMVULtBycz9+XysNbkaGdutOXKcD5X+7PuT7uFEA9cGkExHedIql34YsSaajXt5iB j3DinEjeMdnOb+ySK5/IVkZ3tYfmP0y4trwLSDy4w+/EwGeyD5ZUR9tmpwcG6UAurVmQ 76bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=fpW+qwGKiqRGI1Icu9+vMDJeWfuexJVmMZi0cpjnNsk=; b=wCHhpNS3tBeP+phyQrw1ZWlaTJ3vYhV7Hgth7BfjKIZ53nT7IyACLRqdUsdreqDHdt luuv0gzEdRndSO5M7I1ylkWGOQ+s9vLMnuB+Ioj4faXzpAJ97pul5jXUIBFlsErkPSb+ p3V/Rqp5pNThhCwL3nYZAQGP3kvPM+01QhivnkcILfgaBwxPKSNquQvegD1pftlnPv80 xbWJ9D65/5TBkkYqEEhzK2F1wobx6xI5y0FnwsinHRQP8ttVXjfIiJw/KZNGStiKAhuA 0MUZ3tAWQZP18Kn98mGlmaMFeMe9GcHEQl0rNuRAGrUT/rKx7a5wOXP46trsL3KeXtgR yaNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u17si1740389pgb.317.2017.09.19.11.48.16; Tue, 19 Sep 2017 11:48:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751647AbdISSsM (ORCPT + 26 others); Tue, 19 Sep 2017 14:48:12 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54036 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbdISSsJ (ORCPT ); Tue, 19 Sep 2017 14:48:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B95B715BE; Tue, 19 Sep 2017 11:48:08 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5F5083F483; Tue, 19 Sep 2017 11:48:07 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@codeaurora.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jeremy Linton Subject: [PATCH v2 1/6] ACPI/PPTT: Add Processor Properties Topology Table parsing Date: Tue, 19 Sep 2017 13:47:46 -0500 Message-Id: <20170919184751.25110-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170919184751.25110-1-jeremy.linton@arm.com> References: <20170919184751.25110-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ACPI 6.2 adds a new table, which describes how processing units are related to each other in tree like fashion. Caches are also sprinkled throughout the tree and describe the properties of the caches in relation to other caches and processing units. Add the code to parse the cache hierarchy and report the total number of levels of cache for a given core using acpi_find_last_cache_level() as well as fill out the individual cores cache information with cache_setup_acpi() once the cpu_cacheinfo structure has been populated by the arch specific code. Further, report peers in the topology using setup_acpi_cpu_topology() to report a unique ID for each processing unit at a given level in the tree. These unique id's can then be used to match related processing units which exist as threads, COD (clusters on die), within a given package, etc. Signed-off-by: Jeremy Linton --- drivers/acpi/pptt.c | 458 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 458 insertions(+) create mode 100644 drivers/acpi/pptt.c -- 2.13.5 diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c new file mode 100644 index 000000000000..f7694fa1e0bd --- /dev/null +++ b/drivers/acpi/pptt.c @@ -0,0 +1,458 @@ +/* + * Copyright (C) 2017, ARM + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * This file implements parsing of Processor Properties Topology Table (PPTT) + * which is optionally used to describe the processor and cache topology. + * Due to the relative pointers used throughout the table, this doesn't + * leverage the existing subtable parsing in the kernel. + */ +#define pr_fmt(fmt) "ACPI PPTT: " fmt + +#include +#include +#include + +/* + * Given the PPTT table, find and verify that the subtable entry + * is located within the table + */ +static struct acpi_subtable_header *fetch_pptt_subtable( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + struct acpi_subtable_header *entry; + + /* there isn't a subtable at reference 0 */ + if (!pptt_ref) + return NULL; + + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length) + return NULL; + + entry = (struct acpi_subtable_header *)((u8 *)table_hdr + pptt_ref); + + if (pptt_ref + entry->length > table_hdr->length) + return NULL; + + return entry; +} + +static struct acpi_pptt_processor *fetch_pptt_node( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr, pptt_ref); +} + +static struct acpi_pptt_cache *fetch_pptt_cache( + struct acpi_table_header *table_hdr, u32 pptt_ref) +{ + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, pptt_ref); +} + +static struct acpi_subtable_header *acpi_get_pptt_resource( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *node, int resource) +{ + u32 ref; + + if (resource >= node->number_of_priv_resources) + return NULL; + + ref = *(u32 *)((u8 *)node + sizeof(struct acpi_pptt_processor) + + sizeof(u32) * resource); + + return fetch_pptt_subtable(table_hdr, ref); +} + +/* + * given a pptt resource, verify that it is a cache node, then walk + * down each level of caches, counting how many levels are found + * as well as checking the cache type (icache, dcache, unified). If a + * level & type match, then we set found, and continue the search. + * Once the entire cache branch has been walked return its max + * depth. + */ +static int acpi_pptt_walk_cache(struct acpi_table_header *table_hdr, + int local_level, + struct acpi_subtable_header *res, + struct acpi_pptt_cache **found, + int level, int type) +{ + struct acpi_pptt_cache *cache; + + if (res->type != ACPI_PPTT_TYPE_CACHE) + return 0; + + cache = (struct acpi_pptt_cache *) res; + while (cache) { + local_level++; + + if ((local_level == level) && + (cache->flags & ACPI_PPTT_CACHE_TYPE_VALID) && + ((cache->attributes & ACPI_PPTT_MASK_CACHE_TYPE) == type)) { + if (*found != NULL) + pr_err("Found duplicate cache level/type unable to determine uniqueness\n"); + + pr_debug("Found cache @ level %d\n", level); + *found = cache; + /* + * continue looking at this node's resource list + * to verify that we don't find a duplicate + * cache node. + */ + } + cache = fetch_pptt_cache(table_hdr, cache->next_level_of_cache); + } + return local_level; +} + +/* + * Given a CPU node look for cache levels that exist at this level, and then + * for each cache node, count how many levels exist below (logically above) it. + * If a level and type are specified, and we find that level/type, abort + * processing and return the acpi_pptt_cache structure. + */ +static struct acpi_pptt_cache *acpi_find_cache_level( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + int *starting_level, int level, int type) +{ + struct acpi_subtable_header *res; + int number_of_levels = *starting_level; + int resource = 0; + struct acpi_pptt_cache *ret = NULL; + int local_level; + + /* walk down from processor node */ + while ((res = acpi_get_pptt_resource(table_hdr, cpu_node, resource))) { + resource++; + + local_level = acpi_pptt_walk_cache(table_hdr, *starting_level, + res, &ret, level, type); + /* + * we are looking for the max depth. Since its potentially + * possible for a given node to have resources with differing + * depths verify that the depth we have found is the largest. + */ + if (number_of_levels < local_level) + number_of_levels = local_level; + } + if (number_of_levels > *starting_level) + *starting_level = number_of_levels; + + return ret; +} + +/* + * given a processor node containing a processing unit, walk into it and count + * how many levels exist solely for it, and then walk up each level until we hit + * the root node (ignore the package level because it may be possible to have + * caches that exist across packages). Count the number of cache levels that + * exist at each level on the way up. + */ +static int acpi_process_node(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node) +{ + int total_levels = 0; + + do { + acpi_find_cache_level(table_hdr, cpu_node, &total_levels, 0, 0); + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while (cpu_node); + + return total_levels; +} + +/* + * Find the subtable entry describing the provided processor + */ +static struct acpi_pptt_processor *acpi_find_processor_node( + struct acpi_table_header *table_hdr, + u32 acpi_cpu_id) +{ + struct acpi_subtable_header *entry; + unsigned long table_end; + struct acpi_pptt_processor *cpu_node; + + table_end = (unsigned long)table_hdr + table_hdr->length; + entry = (struct acpi_subtable_header *)((u8 *)table_hdr + + sizeof(struct acpi_table_pptt)); + + /* find the processor structure associated with this cpuid */ + while (((unsigned long)entry) + sizeof(struct acpi_subtable_header) < table_end) { + cpu_node = (struct acpi_pptt_processor *)entry; + + if ((entry->type == ACPI_PPTT_TYPE_PROCESSOR) && + (cpu_node->flags & ACPI_PPTT_ACPI_PROCESSOR_ID_VALID)) { + pr_debug("checking phy_cpu_id %d against acpi id %d\n", + acpi_cpu_id, cpu_node->acpi_processor_id); + if (acpi_cpu_id == cpu_node->acpi_processor_id) { + /* found the correct entry */ + pr_debug("match found!\n"); + return (struct acpi_pptt_processor *)entry; + } + } + + if (entry->length == 0) { + pr_err("Invalid zero length subtable\n"); + break; + } + entry = (struct acpi_subtable_header *) + ((u8 *)entry + entry->length); + } + + return NULL; +} + +/* + * Given a acpi_pptt_processor node, walk up until we identify the + * package that the node is associated with or we run out of levels + * to request. + */ +static struct acpi_pptt_processor *acpi_find_processor_package_id( + struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu, + int level) +{ + struct acpi_pptt_processor *prev_node; + + while (cpu && level && !(cpu->flags & ACPI_PPTT_PHYSICAL_PACKAGE)) { + pr_debug("level %d\n", level); + prev_node = fetch_pptt_node(table_hdr, cpu->parent); + if (prev_node == NULL) + break; + cpu = prev_node; + level--; + } + return cpu; +} + +static int acpi_parse_pptt(struct acpi_table_header *table_hdr, u32 acpi_cpu_id) +{ + int number_of_levels = 0; + struct acpi_pptt_processor *cpu; + + cpu = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (cpu) + number_of_levels = acpi_process_node(table_hdr, cpu); + + return number_of_levels; +} + +#define ACPI_6_2_CACHE_TYPE_DATA (0x0) +#define ACPI_6_2_CACHE_TYPE_INSTR (1<<2) +#define ACPI_6_2_CACHE_TYPE_UNIFIED (1<<3) +#define ACPI_6_2_CACHE_POLICY_WB (0x0) +#define ACPI_6_2_CACHE_POLICY_WT (1<<4) +#define ACPI_6_2_CACHE_READ_ALLOCATE (0x0) +#define ACPI_6_2_CACHE_WRITE_ALLOCATE (0x01) +#define ACPI_6_2_CACHE_RW_ALLOCATE (0x02) + +static u8 acpi_cache_type(enum cache_type type) +{ + switch (type) { + case CACHE_TYPE_DATA: + pr_debug("Looking for data cache\n"); + return ACPI_6_2_CACHE_TYPE_DATA; + case CACHE_TYPE_INST: + pr_debug("Looking for instruction cache\n"); + return ACPI_6_2_CACHE_TYPE_INSTR; + default: + pr_debug("Unknown cache type, assume unified\n"); + case CACHE_TYPE_UNIFIED: + pr_debug("Looking for unified cache\n"); + return ACPI_6_2_CACHE_TYPE_UNIFIED; + } +} + +/* find the ACPI node describing the cache type/level for the given CPU */ +static struct acpi_pptt_cache *acpi_find_cache_node( + struct acpi_table_header *table_hdr, u32 acpi_cpu_id, + enum cache_type type, unsigned int level, + struct acpi_pptt_processor **node) +{ + int total_levels = 0; + struct acpi_pptt_cache *found = NULL; + struct acpi_pptt_processor *cpu_node; + u8 acpi_type = acpi_cache_type(type); + + pr_debug("Looking for CPU %d's level %d cache type %d\n", + acpi_cpu_id, level, acpi_type); + + cpu_node = acpi_find_processor_node(table_hdr, acpi_cpu_id); + if (!cpu_node) + return NULL; + + do { + found = acpi_find_cache_level(table_hdr, cpu_node, &total_levels, level, acpi_type); + *node = cpu_node; + cpu_node = fetch_pptt_node(table_hdr, cpu_node->parent); + } while ((cpu_node) && (!found)); + + return found; +} + +int acpi_find_last_cache_level(unsigned int cpu) +{ + u32 acpi_cpu_id; + struct acpi_table_header *table; + int number_of_levels = 0; + acpi_status status; + + pr_debug("Cache Setup find last level cpu=%d\n", cpu); + + acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + } else { + number_of_levels = acpi_parse_pptt(table, acpi_cpu_id); + acpi_put_table(table); + } + pr_debug("Cache Setup find last level level=%d\n", number_of_levels); + + return number_of_levels; +} + +/* + * The ACPI spec implies that the fields in the cache structures are used to + * extend and correct the information probed from the hardware. In the case + * of arm64 the CCSIDR probing has been removed because it might be incorrect. + */ +static void update_cache_properties(struct cacheinfo *this_leaf, + struct acpi_pptt_cache *found_cache, + struct acpi_pptt_processor *cpu_node) +{ + if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) + this_leaf->size = found_cache->size; + if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) + this_leaf->coherency_line_size = found_cache->line_size; + if (found_cache->flags & ACPI_PPTT_NUMBER_OF_SETS_VALID) + this_leaf->number_of_sets = found_cache->number_of_sets; + if (found_cache->flags & ACPI_PPTT_ASSOCIATIVITY_VALID) + this_leaf->ways_of_associativity = found_cache->associativity; + if (found_cache->flags & ACPI_PPTT_WRITE_POLICY_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY) { + case ACPI_6_2_CACHE_POLICY_WT: + this_leaf->attributes = CACHE_WRITE_THROUGH; + break; + case ACPI_6_2_CACHE_POLICY_WB: + this_leaf->attributes = CACHE_WRITE_BACK; + break; + default: + pr_err("Unknown ACPI cache policy %d\n", + found_cache->attributes & ACPI_PPTT_MASK_WRITE_POLICY); + } + if (found_cache->flags & ACPI_PPTT_ALLOCATION_TYPE_VALID) + switch (found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE) { + case ACPI_6_2_CACHE_READ_ALLOCATE: + this_leaf->attributes |= CACHE_READ_ALLOCATE; + break; + case ACPI_6_2_CACHE_WRITE_ALLOCATE: + this_leaf->attributes |= CACHE_WRITE_ALLOCATE; + break; + case ACPI_6_2_CACHE_RW_ALLOCATE: + this_leaf->attributes |= + CACHE_READ_ALLOCATE|CACHE_WRITE_ALLOCATE; + break; + default: + pr_err("Unknown ACPI cache allocation policy %d\n", + found_cache->attributes & ACPI_PPTT_MASK_ALLOCATION_TYPE); + } +} + +static void cache_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu) +{ + struct acpi_pptt_cache *found_cache; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + u32 acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + struct cacheinfo *this_leaf; + unsigned int index = 0; + struct acpi_pptt_processor *cpu_node = NULL; + + while (index < get_cpu_cacheinfo(cpu)->num_leaves) { + this_leaf = this_cpu_ci->info_list + index; + found_cache = acpi_find_cache_node(table, acpi_cpu_id, + this_leaf->type, + this_leaf->level, + &cpu_node); + pr_debug("found = %p %p\n", found_cache, cpu_node); + if (found_cache) + update_cache_properties(this_leaf, + found_cache, + cpu_node); + + index++; + } +} + +static int topology_setup_acpi_cpu(struct acpi_table_header *table, + unsigned int cpu, int level) +{ + struct acpi_pptt_processor *cpu_node; + u32 acpi_cpu_id = acpi_cpu_get_madt_gicc(cpu)->uid; + + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); + if (cpu_node) { + cpu_node = acpi_find_processor_package_id(table, cpu_node, level); + return (int)((u8 *)cpu_node - (u8 *)table); + } + pr_err_once("PPTT table found, but unable to locate core for %d\n", + cpu); + return -ENOENT; +} + +/* + * simply assign a ACPI cache entry to each known CPU cache entry + * determining which entries are shared is done later. + */ +int cache_setup_acpi(unsigned int cpu) +{ + struct acpi_table_header *table; + acpi_status status; + + pr_debug("Cache Setup ACPI cpu %d\n", cpu); + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cache topology may be inaccurate\n"); + return -ENOENT; + } + + cache_setup_acpi_cpu(table, cpu); + acpi_put_table(table); + + return status; +} + +/* + * Determine a topology unique ID for each thread/core/cluster/socket/etc. + * This ID can then be used to group peers. + */ +int setup_acpi_cpu_topology(unsigned int cpu, int level) +{ + struct acpi_table_header *table; + acpi_status status; + int retval; + + status = acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + pr_err_once("No PPTT table found, cpu topology may be inaccurate\n"); + return -ENOENT; + } + retval = topology_setup_acpi_cpu(table, cpu, level); + pr_debug("Topology Setup ACPI cpu %d, level %d ret = %d\n", + cpu, level, retval); + acpi_put_table(table); + + return retval; +} From patchwork Tue Sep 19 18:47:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 113058 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5260721qgf; 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[209.132.180.67]) by mx.google.com with ESMTP id c8si1683161pfm.118.2017.09.19.11.49.45; Tue, 19 Sep 2017 11:49:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751875AbdISStn (ORCPT + 26 others); Tue, 19 Sep 2017 14:49:43 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54058 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751587AbdISSsL (ORCPT ); Tue, 19 Sep 2017 14:48:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F35D15BF; Tue, 19 Sep 2017 11:48:10 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5012E3F483; Tue, 19 Sep 2017 11:48:09 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@codeaurora.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jeremy Linton Subject: [PATCH v2 2/6] ACPI: Enable PPTT support on ARM64 Date: Tue, 19 Sep 2017 13:47:47 -0500 Message-Id: <20170919184751.25110-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170919184751.25110-1-jeremy.linton@arm.com> References: <20170919184751.25110-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we have a PPTT parser, in preparation for its use on arm64, lets build it. Signed-off-by: Jeremy Linton --- arch/arm64/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/arm64/Kconfig | 3 +++ 3 files changed, 5 insertions(+) -- 2.13.5 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..68c9d1289735 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -7,6 +7,7 @@ config ARM64 select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ACPI_MCFG if ACPI select ACPI_SPCR_TABLE if ACPI + select ACPI_PPTT if ACPI select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 90265ab4437a..c92a0c937551 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_ACPI_BGRT) += bgrt.o obj-$(CONFIG_ACPI_CPPC_LIB) += cppc_acpi.o obj-$(CONFIG_ACPI_SPCR_TABLE) += spcr.o obj-$(CONFIG_ACPI_DEBUGGER_USER) += acpi_dbg.o +obj-$(CONFIG_ACPI_PPTT) += pptt.o # processor has its own "processor." module_param namespace processor-y := processor_driver.o diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig index 5a6f80fce0d6..74b855a669ea 100644 --- a/drivers/acpi/arm64/Kconfig +++ b/drivers/acpi/arm64/Kconfig @@ -7,3 +7,6 @@ config ACPI_IORT config ACPI_GTDT bool + +config ACPI_PPTT + bool \ No newline at end of file From patchwork Tue Sep 19 18:47:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 113054 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5259404qgf; Tue, 19 Sep 2017 11:48:19 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAdobfKxxdpCJoWOFC6Y+kfZltO+KRWI9baJ/PHNidF0ZbdYdb8C+1c1oGGRfuCxgVuO3w3 X-Received: by 10.84.172.131 with SMTP id n3mr2180544plb.408.1505846899160; Tue, 19 Sep 2017 11:48:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505846899; cv=none; d=google.com; s=arc-20160816; b=K2YoeLnGm5se0vbqYdd/+ACphlK/ivG8opdond3MeIYOvefATm9G62AZ3ul/wqaevO oFQxBg0JCSWAhpdS5IOA/UdTmfpYzLf9TLx8cRtgH+pJojlKbLlsifdHIiv5JpJceyiC qwT48lvl6odVnNpjMJeSByZBR3dQofcs24kom7XQ8Q28RhDIuSy4J5oywMg7GJKUKPwJ TIzFEbyuiMZSkm1iRmft6DeGtTl2hoipH+n6u8791SSszYHbvK7tZPZVU7dxXirAV2Ou oHPPGZI172OF7xRu/MtY2d8SN+L9xnfDOv8tpBKr3Ln9Lk9xl0TJvbH3Q/f7msGadnoi qbpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jyFBMl2cKfancZGPuIbT1TLbJRxt6lp0cppg8cEG/cY=; b=mWfL6ZMK1rhjQEy/zYONnxOtA8U5jbDtOrW+gyiCl2ETlLYGY3hDn8Oe06Ufnson0s /SjYgBgY8tqC0BoyXaD3WLr/LL8M5uxjVjHkbFSL5cqkowhz+Jq0rXKQ2uJW1+oKO92/ I3YvC/qyGJ/mTRNFyScHsWNDlEjcGHUK9nDM5y4j+XghVm4hRfxjNCs7sWzV+48Xczaj 2/L++annHXPrfgyUTMabqjagbr7tsDn0pOi2f7RAzvAFWyh5P5llL7BT4e/OEn6TXgyd nrHQPE/u4pS6E59NbUDHvJ/BdB/ssfCbr5cc5cURT1/cYdQNg8TTeyfh2CYHHzXYHL68 lzgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j8si1826809pgp.526.2017.09.19.11.48.18; Tue, 19 Sep 2017 11:48:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751722AbdISSsP (ORCPT + 26 others); Tue, 19 Sep 2017 14:48:15 -0400 Received: from foss.arm.com ([217.140.101.70]:54068 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751621AbdISSsM (ORCPT ); Tue, 19 Sep 2017 14:48:12 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69573165D; Tue, 19 Sep 2017 11:48:12 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2A6FA3F483; Tue, 19 Sep 2017 11:48:11 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@codeaurora.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jeremy Linton Subject: [PATCH v2 3/6] drivers: base: cacheinfo: arm64: Add support for ACPI based firmware tables Date: Tue, 19 Sep 2017 13:47:48 -0500 Message-Id: <20170919184751.25110-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170919184751.25110-1-jeremy.linton@arm.com> References: <20170919184751.25110-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The /sys cache entries should support ACPI/PPTT generated cache topology information. Lets detect ACPI systems and call an arch specific cache_setup_acpi() routine to update the hardware probed cache topology. For arm64, if ACPI is enabled, determine the max number of cache levels and populate them using a PPTT table if one is available. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cacheinfo.c | 23 ++++++++++++++++++----- drivers/acpi/pptt.c | 1 + drivers/base/cacheinfo.c | 17 +++++++++++------ include/linux/cacheinfo.h | 10 ++++++++-- 4 files changed, 38 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 380f2e2fbed5..2e2cf0d312ba 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -17,6 +17,7 @@ * along with this program. If not, see . */ +#include #include #include @@ -44,9 +45,17 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type = type; } +#ifndef CONFIG_ACPI +int acpi_find_last_cache_level(unsigned int cpu) +{ + /*ACPI kernels should be built with PPTT support*/ + return 0; +} +#endif + static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves, of_level; + unsigned int ctype, level, leaves, fw_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -59,15 +68,19 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } - of_level = of_find_last_cache_level(cpu); - if (level < of_level) { + if (acpi_disabled) + fw_level = of_find_last_cache_level(cpu); + else + fw_level = acpi_find_last_cache_level(cpu); + + if (level < fw_level) { /* * some external caches not specified in CLIDR_EL1 * the information may be available in the device tree * only unified external caches are considered here */ - leaves += (of_level - level); - level = of_level; + leaves += (fw_level - level); + level = fw_level; } this_cpu_ci->num_levels = level; diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index f7694fa1e0bd..0dd918c3782c 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -331,6 +331,7 @@ static void update_cache_properties(struct cacheinfo *this_leaf, struct acpi_pptt_cache *found_cache, struct acpi_pptt_processor *cpu_node) { + this_leaf->firmware_node = found_cache; if (found_cache->flags & ACPI_PPTT_SIZE_PROPERTY_VALID) this_leaf->size = found_cache->size; if (found_cache->flags & ACPI_PPTT_LINE_SIZE_VALID) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af2739537..8eca279e50d1 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -86,7 +86,7 @@ static int cache_setup_of_node(unsigned int cpu) static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) { - return sib_leaf->of_node == this_leaf->of_node; + return sib_leaf->firmware_node == this_leaf->firmware_node; } /* OF properties to query for a given cache type */ @@ -215,6 +215,11 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, } #endif +int __weak cache_setup_acpi(unsigned int cpu) +{ + return -ENOTSUPP; +} + static int cache_shared_cpu_map_setup(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -225,11 +230,11 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) if (this_cpu_ci->cpu_map_populated) return 0; - if (of_have_populated_dt()) + if (!acpi_disabled) + ret = cache_setup_acpi(cpu); + else if (of_have_populated_dt()) ret = cache_setup_of_node(cpu); - else if (!acpi_disabled) - /* No cache property/hierarchy support yet in ACPI */ - ret = -ENOTSUPP; + if (ret) return ret; @@ -286,7 +291,7 @@ static void cache_shared_cpu_map_remove(unsigned int cpu) static void cache_override_properties(unsigned int cpu) { - if (of_have_populated_dt()) + if (acpi_disabled && of_have_populated_dt()) return cache_of_override_properties(cpu); } diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 6a524bf6a06d..0114eb9ab67b 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -36,6 +36,9 @@ enum cache_type { * @of_node: if devicetree is used, this represents either the cpu node in * case there's no explicit cache node or the cache node itself in the * device tree + * @firmware_node: Shared with of_node. When not using DT, this may contain + * pointers to other firmware based values. Particularly ACPI/PPTT + * unique values. * @disable_sysfs: indicates whether this node is visible to the user via * sysfs or not * @priv: pointer to any private data structure specific to particular @@ -64,8 +67,10 @@ struct cacheinfo { #define CACHE_ALLOCATE_POLICY_MASK \ (CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE) #define CACHE_ID BIT(4) - - struct device_node *of_node; + union { + struct device_node *of_node; + void *firmware_node; + }; bool disable_sysfs; void *priv; }; @@ -98,6 +103,7 @@ int func(unsigned int cpu) \ struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); +int acpi_find_last_cache_level(unsigned int cpu); const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf); From patchwork Tue Sep 19 18:47:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 113057 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5259954qgf; Tue, 19 Sep 2017 11:48:56 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBQyMWDj0uGB6PXq4rrdHNyxPh205FkQG++qUcI/B9C/2ccTGR3NDFbLuN56TsrXXopHQA7 X-Received: by 10.98.10.146 with SMTP id 18mr2133878pfk.346.1505846936318; Tue, 19 Sep 2017 11:48:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505846936; cv=none; d=google.com; s=arc-20160816; b=C5CTwMUBMrorUvvc5dLh1mhgb+8+Miaf2dA8HpGfNUheIL07WuMt3rnb3ja9g8owU4 BBXusTHYJbutjwqwwKFJ2GSmntcGw0e0OMMhR+YcGGWFWCVcihS9yXKzXEbsYqlw/w0S qVzBFSwRWv2nsRCbOrtr+JZvBOUWhsIxpi+3OMkAdZMMlKVQpTqETMxsNfeAlFb9IthM LGU5nl3m5KftZo2ZrmXUIoo7S+CdCbENk+STCmnJ2J7sScs3oIDPH04U0Rb81nogg3rE SiEOTif2Bt/Baz9tbWKrqa++lEJr41i5ESVvmKlyXLCcNYxAHMzZ3B1/5CWf10jX8aUJ NqZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=FcTDi/Rx2LPQbtZTFEAbjbMopuLBW6IS4Yp5ZSeXsMo=; b=HA78LwB/nk5nfBDS3GaJKuWIXqL4aD5YgXb0uSBT+FSI031UAHsHceXgSzKVYKUCas vuW03xZj3DeBMpQQ91XA716goXdl+qBWtuGkFp4F5Vt7eBJUv0AnlHPX2elsEHzkmgHk 7E+xcE08fkgeKXgnWkcD06o16Alk5l0tCRKclmj+U8Em835grBksimbNZFqDDh0GUGDA bbbdyQsPGyTHv7j4MyHMG6F0qmwTxI07DuvzugB/PXGRBOwxZoV+TSOIeYaLM7bSJgtH xlEYRJXJqFGdUmqK1WByVLn3By2pszd0Dn/YlDANM7u7IBAcD5Nn2bVe2O9md/4U7RJG 2sQQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b73si6794614pli.337.2017.09.19.11.48.56; Tue, 19 Sep 2017 11:48:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751752AbdISSsy (ORCPT + 26 others); Tue, 19 Sep 2017 14:48:54 -0400 Received: from foss.arm.com ([217.140.101.70]:54090 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbdISSsP (ORCPT ); Tue, 19 Sep 2017 14:48:15 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A367B1682; Tue, 19 Sep 2017 11:48:14 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 258B93F483; Tue, 19 Sep 2017 11:48:13 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@codeaurora.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jeremy Linton Subject: [PATCH v2 4/6] Topology: Add cluster on die macros and arm64 decoding Date: Tue, 19 Sep 2017 13:47:49 -0500 Message-Id: <20170919184751.25110-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170919184751.25110-1-jeremy.linton@arm.com> References: <20170919184751.25110-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Many modern machines have cluster on die (COD) non-uniformity as well as the traditional multi-socket architectures. Reusing the multi-socket or NUMA on die concepts for these (as arm64 does) breaks down when presented with actual multi-socket/COD machines. Similar, problems are also visible on some x86 machines so it seems appropriate to start abstracting and making these topologies visible. To start, a topology_cod_id() macro is added which defaults to returning the same information as topology_physical_package_id(). Moving forward we can start to spit out the differences. For arm64, an additional package_id is added to the cpu_topology array. Initially this will be equal to the cluster_id as well. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/topology.h | 4 +++- arch/arm64/kernel/topology.c | 8 ++++++-- include/linux/topology.h | 3 +++ 3 files changed, 12 insertions(+), 3 deletions(-) -- 2.13.5 diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 8b57339823e9..bd7517960d39 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -7,13 +7,15 @@ struct cpu_topology { int thread_id; int core_id; int cluster_id; + int package_id; cpumask_t thread_sibling; cpumask_t core_sibling; }; extern struct cpu_topology cpu_topology[NR_CPUS]; -#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) +#define topology_physical_package_id(cpu) (cpu_topology[cpu].package_id) +#define topology_cod_id(cpu) (cpu_topology[cpu].cluster_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 8d48b233e6ce..9147e5b6326d 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -67,6 +67,8 @@ static int __init parse_core(struct device_node *core, int cluster_id, leaf = false; cpu = get_cpu_for_node(t); if (cpu >= 0) { + /* maintain DT cluster == package behavior */ + cpu_topology[cpu].package_id = cluster_id; cpu_topology[cpu].cluster_id = cluster_id; cpu_topology[cpu].core_id = core_id; cpu_topology[cpu].thread_id = i; @@ -88,7 +90,7 @@ static int __init parse_core(struct device_node *core, int cluster_id, core); return -EINVAL; } - + cpu_topology[cpu].package_id = cluster_id; cpu_topology[cpu].cluster_id = cluster_id; cpu_topology[cpu].core_id = core_id; } else if (leaf) { @@ -228,7 +230,7 @@ static void update_siblings_masks(unsigned int cpuid) for_each_possible_cpu(cpu) { cpu_topo = &cpu_topology[cpu]; - if (cpuid_topo->cluster_id != cpu_topo->cluster_id) + if (cpuid_topo->package_id != cpu_topo->package_id) continue; cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); @@ -273,6 +275,7 @@ void store_cpu_topology(unsigned int cpuid) MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; } + cpuid_topo->package_id = cpuid_topo->cluster_id; pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, @@ -292,6 +295,7 @@ static void __init reset_cpu_topology(void) cpu_topo->thread_id = -1; cpu_topo->core_id = 0; cpu_topo->cluster_id = -1; + cpu_topo->package_id = -1; cpumask_clear(&cpu_topo->core_sibling); cpumask_set_cpu(cpu, &cpu_topo->core_sibling); diff --git a/include/linux/topology.h b/include/linux/topology.h index cb0775e1ee4b..4660749a7303 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -184,6 +184,9 @@ static inline int cpu_to_mem(int cpu) #ifndef topology_physical_package_id #define topology_physical_package_id(cpu) ((void)(cpu), -1) #endif +#ifndef topology_cod_id /* cluster on die */ +#define topology_cod_id(cpu) topology_physical_package_id(cpu) +#endif #ifndef topology_core_id #define topology_core_id(cpu) ((void)(cpu), 0) #endif From patchwork Tue Sep 19 18:47:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 113056 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5259692qgf; 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[209.132.180.67]) by mx.google.com with ESMTP id k1si1880769pgc.473.2017.09.19.11.48.38; Tue, 19 Sep 2017 11:48:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751848AbdISSsW (ORCPT + 26 others); Tue, 19 Sep 2017 14:48:22 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54132 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751568AbdISSsT (ORCPT ); Tue, 19 Sep 2017 14:48:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 629EB169F; Tue, 19 Sep 2017 11:48:18 -0700 (PDT) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 235993F483; Tue, 19 Sep 2017 11:48:17 -0700 (PDT) From: Jeremy Linton To: linux-acpi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sudeep.holla@arm.com, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@codeaurora.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jeremy Linton Subject: [PATCH v2 6/6] arm64: topology: Enable ACPI/PPTT based CPU topology. Date: Tue, 19 Sep 2017 13:47:51 -0500 Message-Id: <20170919184751.25110-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170919184751.25110-1-jeremy.linton@arm.com> References: <20170919184751.25110-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Propagate the topology information from the PPTT tree to the cpu_topology array. We can get the thread id, core_id and cluster_id by assuming certain levels of the PPTT tree correspond to those concepts. The package_id is flagged in the tree and can be found by passing an arbitrary large level to setup_acpi_cpu_topology() which terminates its search when it finds an ACPI node flagged as the physical package. If the tree doesn't contain enough levels to represent all of thread/core/cod/package then the package id will be used for the missing levels. Since server/ACPI machines are more likely to be multisocket and NUMA, this patch also modifies the default clusters=sockets behavior for ACPI machines to sockets=sockets. DT machines continue to represent sockets as clusters. For ACPI machines, this results in a more normalized view of the topology. Cluster level scheduler decisions are still being made due to the "MC" level in the scheduler which has knowledge of cache sharing domains. This code is loosely based on a combination of code from: Xiongfeng Wang John Garry Jeffrey Hugo Signed-off-by: Jeremy Linton --- arch/arm64/kernel/topology.c | 54 +++++++++++++++++++++++++++++++++++++++++++- include/linux/topology.h | 1 + 2 files changed, 54 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 9147e5b6326d..42f3e7f28b2b 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -304,6 +306,54 @@ static void __init reset_cpu_topology(void) } } +#ifdef CONFIG_ACPI +/* + * Propagate the topology information of the processor_topology_node tree to the + * cpu_topology array. + */ +static int __init parse_acpi_topology(void) +{ + u64 is_threaded; + int cpu; + int topology_id; + /* set a large depth, to hit ACPI_PPTT_PHYSICAL_PACKAGE if one exists */ + const int max_topo = 0xFF; + + is_threaded = read_cpuid_mpidr() & MPIDR_MT_BITMASK; + + for_each_possible_cpu(cpu) { + topology_id = setup_acpi_cpu_topology(cpu, 0); + if (topology_id < 0) + return topology_id; + + if (is_threaded) { + cpu_topology[cpu].thread_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].core_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 2); + cpu_topology[cpu].cluster_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, max_topo); + cpu_topology[cpu].package_id = topology_id; + } else { + cpu_topology[cpu].thread_id = -1; + cpu_topology[cpu].core_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, 1); + cpu_topology[cpu].cluster_id = topology_id; + topology_id = setup_acpi_cpu_topology(cpu, max_topo); + cpu_topology[cpu].package_id = topology_id; + } + } + return 0; +} + +#else +static int __init parse_acpi_topology(void) +{ + /*ACPI kernels should be built with PPTT support*/ + return -EINVAL; +} +#endif + void __init init_cpu_topology(void) { reset_cpu_topology(); @@ -312,6 +362,8 @@ void __init init_cpu_topology(void) * Discard anything that was parsed if we hit an error so we * don't use partial information. */ - if (of_have_populated_dt() && parse_dt_topology()) + if ((!acpi_disabled) && parse_acpi_topology()) + reset_cpu_topology(); + else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } diff --git a/include/linux/topology.h b/include/linux/topology.h index 4660749a7303..cbf2fb13bf92 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -43,6 +43,7 @@ if (nr_cpus_node(node)) int arch_update_cpu_topology(void); +int setup_acpi_cpu_topology(unsigned int cpu, int level); /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10