From patchwork Mon May 4 08:25:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 219992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EACD3C4724C for ; Mon, 4 May 2020 08:28:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D638420746 for ; Mon, 4 May 2020 08:28:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728229AbgEDI2L (ORCPT ); Mon, 4 May 2020 04:28:11 -0400 Received: from mga14.intel.com ([192.55.52.115]:33993 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725941AbgEDI2K (ORCPT ); Mon, 4 May 2020 04:28:10 -0400 IronPort-SDR: kaJdNBMbY7/g6XmfObkCHQLn82n5RkTDSZoV3XXX/r+k4TYiT3qjpEsWKQPTQlgvP7UUYDJujA 2A/s8LWjgxsg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 01:28:09 -0700 IronPort-SDR: BQP69Bwj01df2NtARTZCiNEIYFyU8ChgTGocHArhXsO+n/UROWgoZK+DAxazfPU1nL8b7UNwUO 5VTpNvSu+RlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,351,1583222400"; d="scan'208";a="295436026" Received: from pg-nxl3.altera.com ([10.142.129.93]) by orsmga008.jf.intel.com with ESMTP; 04 May 2020 01:28:07 -0700 From: Joyce Ooi To: Thor Thayer , "David S . Miller" Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen Subject: [PATCHv2 02/10] net: eth: altera: set rx and tx ring size before init_dma call Date: Mon, 4 May 2020 16:25:50 +0800 Message-Id: <20200504082558.112627-3-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200504082558.112627-1-joyce.ooi@intel.com> References: <20200504082558.112627-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen It is more appropriate to set the rx and tx ring size before calling the init function for the dma. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: no change --- drivers/net/ethernet/altera/altera_tse_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 2a9e6157a8a1..539e744e23f7 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -1154,6 +1154,10 @@ static int tse_open(struct net_device *dev) int i; unsigned long int flags; + /* set tx and rx ring size */ + priv->rx_ring_size = dma_rx_num; + priv->tx_ring_size = dma_tx_num; + /* Reset and configure TSE MAC and probe associated PHY */ ret = priv->dmaops->init_dma(priv); if (ret != 0) { @@ -1196,8 +1200,6 @@ static int tse_open(struct net_device *dev) priv->dmaops->reset_dma(priv); /* Create and initialize the TX/RX descriptors chains. */ - priv->rx_ring_size = dma_rx_num; - priv->tx_ring_size = dma_tx_num; ret = alloc_init_skbufs(priv); if (ret) { netdev_err(dev, "DMA descriptors initialization failed\n"); From patchwork Mon May 4 08:25:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 219991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 192C0C3A5A9 for ; Mon, 4 May 2020 08:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 02D4C20746 for ; Mon, 4 May 2020 08:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728263AbgEDI2X (ORCPT ); Mon, 4 May 2020 04:28:23 -0400 Received: from mga11.intel.com ([192.55.52.93]:41838 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725941AbgEDI2W (ORCPT ); Mon, 4 May 2020 04:28:22 -0400 IronPort-SDR: Ohq/psjAR35C+51axythSRzKxAV4+gjt8xC71gOjW2Iq2xmTe837WveRH3o9UHilxTddfyHXsp uU0TVsGzBu+A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 01:28:21 -0700 IronPort-SDR: WgM8V4w0X8z+/n+TqQX+1ywYpC0JK8hZM1n6SyW+64bro91NX6CPmR/ST+6EJNVnskeSip1otI DFZztNtGuX4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,351,1583222400"; d="scan'208";a="295436068" Received: from pg-nxl3.altera.com ([10.142.129.93]) by orsmga008.jf.intel.com with ESMTP; 04 May 2020 01:28:18 -0700 From: Joyce Ooi To: Thor Thayer , "David S . Miller" Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen Subject: [PATCHv2 04/10] net: eth: altera: add optional function to start tx dma Date: Mon, 4 May 2020 16:25:52 +0800 Message-Id: <20200504082558.112627-5-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200504082558.112627-1-joyce.ooi@intel.com> References: <20200504082558.112627-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Allow for optional start up of tx dma if the start_txdma function is defined in altera_dmaops. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: no change --- drivers/net/ethernet/altera/altera_tse.h | 1 + drivers/net/ethernet/altera/altera_tse_main.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index 7d0c98fc103e..26c5541fda27 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -401,6 +401,7 @@ struct altera_dmaops { int (*init_dma)(struct altera_tse_private *priv); void (*uninit_dma)(struct altera_tse_private *priv); void (*start_rxdma)(struct altera_tse_private *priv); + void (*start_txdma)(struct altera_tse_private *priv); }; /* This structure is private to each device. diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 539e744e23f7..3c756afd0d39 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -1244,6 +1244,9 @@ static int tse_open(struct net_device *dev) priv->dmaops->start_rxdma(priv); + if (priv->dmaops->start_txdma) + priv->dmaops->start_txdma(priv); + /* Start MAC Rx/Tx */ spin_lock(&priv->mac_cfg_lock); tse_set_mac(priv, true); @@ -1646,6 +1649,7 @@ static const struct altera_dmaops altera_dtype_sgdma = { .init_dma = sgdma_initialize, .uninit_dma = sgdma_uninitialize, .start_rxdma = sgdma_start_rxdma, + .start_txdma = NULL, }; static const struct altera_dmaops altera_dtype_msgdma = { @@ -1665,6 +1669,7 @@ static const struct altera_dmaops altera_dtype_msgdma = { .init_dma = msgdma_initialize, .uninit_dma = msgdma_uninitialize, .start_rxdma = msgdma_start_rxdma, + .start_txdma = NULL, }; static const struct of_device_id altera_tse_ids[] = { From patchwork Mon May 4 08:25:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 219990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 624AAC47258 for ; Mon, 4 May 2020 08:28:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CF5620746 for ; Mon, 4 May 2020 08:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728299AbgEDI2b (ORCPT ); Mon, 4 May 2020 04:28:31 -0400 Received: from mga11.intel.com ([192.55.52.93]:41838 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725941AbgEDI2a (ORCPT ); Mon, 4 May 2020 04:28:30 -0400 IronPort-SDR: 4jvSrRXoGoL4rRlgMSTp9hIuVIs3Xu4mMJEXnQJEX0HFHY5fJirgNd31s9Viin9u5VvXxgZHh0 veLHqyqPVp3g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 01:28:29 -0700 IronPort-SDR: 5tGc/wjDo24Bg62hMXoECzy14pG3iufIGwhyoRqrbfG+sJPuOtibQ/H9PBMp/WkQbzwX2dT/TY 8UEypeU4NA2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,351,1583222400"; d="scan'208";a="295436100" Received: from pg-nxl3.altera.com ([10.142.129.93]) by orsmga008.jf.intel.com with ESMTP; 04 May 2020 01:28:26 -0700 From: Joyce Ooi To: Thor Thayer , "David S . Miller" Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Dalon Westergreen Subject: [PATCHv2 06/10] net: eth: altera: Add missing identifier names to function declarations Date: Mon, 4 May 2020 16:25:54 +0800 Message-Id: <20200504082558.112627-7-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200504082558.112627-1-joyce.ooi@intel.com> References: <20200504082558.112627-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen The sgdma and msgdma header files included function declarations without identifier names for pointers. Add appropriate identifier names. Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: this patch is added in patch version 2 --- drivers/net/ethernet/altera/altera_msgdma.h | 30 ++++++++++++++------------- drivers/net/ethernet/altera/altera_sgdma.h | 32 +++++++++++++++-------------- 2 files changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_msgdma.h b/drivers/net/ethernet/altera/altera_msgdma.h index 9813fbfff4d3..23f5b2a13898 100644 --- a/drivers/net/ethernet/altera/altera_msgdma.h +++ b/drivers/net/ethernet/altera/altera_msgdma.h @@ -6,19 +6,21 @@ #ifndef __ALTERA_MSGDMA_H__ #define __ALTERA_MSGDMA_H__ -void msgdma_reset(struct altera_tse_private *); -void msgdma_enable_txirq(struct altera_tse_private *); -void msgdma_enable_rxirq(struct altera_tse_private *); -void msgdma_disable_rxirq(struct altera_tse_private *); -void msgdma_disable_txirq(struct altera_tse_private *); -void msgdma_clear_rxirq(struct altera_tse_private *); -void msgdma_clear_txirq(struct altera_tse_private *); -u32 msgdma_tx_completions(struct altera_tse_private *); -void msgdma_add_rx_desc(struct altera_tse_private *, struct tse_buffer *); -int msgdma_tx_buffer(struct altera_tse_private *, struct tse_buffer *); -u32 msgdma_rx_status(struct altera_tse_private *); -int msgdma_initialize(struct altera_tse_private *); -void msgdma_uninitialize(struct altera_tse_private *); -void msgdma_start_rxdma(struct altera_tse_private *); +void msgdma_reset(struct altera_tse_private *priv); +void msgdma_enable_txirq(struct altera_tse_private *priv); +void msgdma_enable_rxirq(struct altera_tse_private *priv); +void msgdma_disable_rxirq(struct altera_tse_private *priv); +void msgdma_disable_txirq(struct altera_tse_private *priv); +void msgdma_clear_rxirq(struct altera_tse_private *priv); +void msgdma_clear_txirq(struct altera_tse_private *priv); +u32 msgdma_tx_completions(struct altera_tse_private *priv); +void msgdma_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *buffer); +int msgdma_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer); +u32 msgdma_rx_status(struct altera_tse_private *priv); +int msgdma_initialize(struct altera_tse_private *priv); +void msgdma_uninitialize(struct altera_tse_private *priv); +void msgdma_start_rxdma(struct altera_tse_private *priv); #endif /* __ALTERA_MSGDMA_H__ */ diff --git a/drivers/net/ethernet/altera/altera_sgdma.h b/drivers/net/ethernet/altera/altera_sgdma.h index 08afe1c9994f..3fb201417820 100644 --- a/drivers/net/ethernet/altera/altera_sgdma.h +++ b/drivers/net/ethernet/altera/altera_sgdma.h @@ -6,20 +6,22 @@ #ifndef __ALTERA_SGDMA_H__ #define __ALTERA_SGDMA_H__ -void sgdma_reset(struct altera_tse_private *); -void sgdma_enable_txirq(struct altera_tse_private *); -void sgdma_enable_rxirq(struct altera_tse_private *); -void sgdma_disable_rxirq(struct altera_tse_private *); -void sgdma_disable_txirq(struct altera_tse_private *); -void sgdma_clear_rxirq(struct altera_tse_private *); -void sgdma_clear_txirq(struct altera_tse_private *); -int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *); -u32 sgdma_tx_completions(struct altera_tse_private *); -void sgdma_add_rx_desc(struct altera_tse_private *priv, struct tse_buffer *); -void sgdma_status(struct altera_tse_private *); -u32 sgdma_rx_status(struct altera_tse_private *); -int sgdma_initialize(struct altera_tse_private *); -void sgdma_uninitialize(struct altera_tse_private *); -void sgdma_start_rxdma(struct altera_tse_private *); +void sgdma_reset(struct altera_tse_private *priv); +void sgdma_enable_txirq(struct altera_tse_private *priv); +void sgdma_enable_rxirq(struct altera_tse_private *priv); +void sgdma_disable_rxirq(struct altera_tse_private *priv); +void sgdma_disable_txirq(struct altera_tse_private *priv); +void sgdma_clear_rxirq(struct altera_tse_private *priv); +void sgdma_clear_txirq(struct altera_tse_private *priv); +int sgdma_tx_buffer(struct altera_tse_private *priv, + struct tse_buffer *buffer); +u32 sgdma_tx_completions(struct altera_tse_private *priv); +void sgdma_add_rx_desc(struct altera_tse_private *priv, + struct tse_buffer *buffer); +void sgdma_status(struct altera_tse_private *priv); +u32 sgdma_rx_status(struct altera_tse_private *priv); +int sgdma_initialize(struct altera_tse_private *priv); +void sgdma_uninitialize(struct altera_tse_private *priv); +void sgdma_start_rxdma(struct altera_tse_private *priv); #endif /* __ALTERA_SGDMA_H__ */ From patchwork Mon May 4 08:25:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 219989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 291C5C4724C for ; Mon, 4 May 2020 08:28:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 010112078E for ; Mon, 4 May 2020 08:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728334AbgEDI2s (ORCPT ); Mon, 4 May 2020 04:28:48 -0400 Received: from mga02.intel.com ([134.134.136.20]:49039 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725941AbgEDI2r (ORCPT ); Mon, 4 May 2020 04:28:47 -0400 IronPort-SDR: bu6SBuH5gpW5BIRW8S37SeDhuLpZ3KtB6qeUWvqqk8MrhjvcEaCRd4MKNwPZtw0hg6KdiMxgp7 vSgaoyelqRRA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 01:28:43 -0700 IronPort-SDR: aLTcQANPzQtIiNEOoZ3Y9pHy1O8QIVVa6rPEWqK1/Cne+W4Jxcg6GmnjLDDDXtdzJdGx+OEqJQ jNWOSCjEULcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,351,1583222400"; d="scan'208";a="295436130" Received: from pg-nxl3.altera.com ([10.142.129.93]) by orsmga008.jf.intel.com with ESMTP; 04 May 2020 01:28:40 -0700 From: Joyce Ooi To: Thor Thayer , "David S . Miller" Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Richard Cochran Subject: [PATCHv2 08/10] net: eth: altera: add support for ptp and timestamping Date: Mon, 4 May 2020 16:25:56 +0800 Message-Id: <20200504082558.112627-9-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200504082558.112627-1-joyce.ooi@intel.com> References: <20200504082558.112627-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Add support for the ptp clock used with the tse, and update the driver to support timestamping when enabled. We also enable debugfs entries for the ptp clock to allow some user control and interaction with the ptp clock. Cc: Richard Cochran Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: rename altera_ptp to intel_fpga_tod --- drivers/net/ethernet/altera/Kconfig | 1 + drivers/net/ethernet/altera/Makefile | 3 +- drivers/net/ethernet/altera/altera_tse.h | 8 + drivers/net/ethernet/altera/altera_tse_ethtool.c | 28 ++ drivers/net/ethernet/altera/altera_tse_main.c | 118 +++++++- drivers/net/ethernet/altera/intel_fpga_tod.c | 358 +++++++++++++++++++++++ drivers/net/ethernet/altera/intel_fpga_tod.h | 56 ++++ 7 files changed, 570 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/altera/intel_fpga_tod.c create mode 100644 drivers/net/ethernet/altera/intel_fpga_tod.h diff --git a/drivers/net/ethernet/altera/Kconfig b/drivers/net/ethernet/altera/Kconfig index 2690c398d2b2..6dec7094cb4b 100644 --- a/drivers/net/ethernet/altera/Kconfig +++ b/drivers/net/ethernet/altera/Kconfig @@ -3,6 +3,7 @@ config ALTERA_TSE tristate "Altera Triple-Speed Ethernet MAC support" depends on HAS_DMA select PHYLIB + imply PTP_1588_CLOCK ---help--- This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. diff --git a/drivers/net/ethernet/altera/Makefile b/drivers/net/ethernet/altera/Makefile index a52db80aee9f..fc2e460926b3 100644 --- a/drivers/net/ethernet/altera/Makefile +++ b/drivers/net/ethernet/altera/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \ -altera_msgdma.o altera_sgdma.o altera_utils.o + altera_msgdma.o altera_sgdma.o altera_utils.o \ + intel_fpga_tod.o diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index 79d02748c89d..b7c176a808ac 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -28,6 +28,8 @@ #include #include +#include "intel_fpga_tod.h" + #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in * bytes @@ -417,6 +419,12 @@ struct altera_tse_private { /* TSE Revision */ u32 revision; + /* Shared PTP structure */ + struct intel_fpga_tod_private ptp_priv; + int hwts_tx_en; + int hwts_rx_en; + u32 ptp_enable; + /* mSGDMA Rx Dispatcher address space */ void __iomem *rx_dma_csr; void __iomem *rx_dma_desc; diff --git a/drivers/net/ethernet/altera/altera_tse_ethtool.c b/drivers/net/ethernet/altera/altera_tse_ethtool.c index 420d77f00eab..cec41a2c7b00 100644 --- a/drivers/net/ethernet/altera/altera_tse_ethtool.c +++ b/drivers/net/ethernet/altera/altera_tse_ethtool.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "altera_tse.h" @@ -222,6 +223,32 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs, buf[i] = csrrd32(priv->mac_dev, i * 4); } +static int tse_get_ts_info(struct net_device *dev, + struct ethtool_ts_info *info) +{ + struct altera_tse_private *priv = netdev_priv(dev); + + if (priv->ptp_enable) { + if (priv->ptp_priv.ptp_clock) + info->phc_index = + ptp_clock_index(priv->ptp_priv.ptp_clock); + + info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + + info->tx_types = (1 << HWTSTAMP_TX_OFF) | + (1 << HWTSTAMP_TX_ON); + + info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_ALL); + + return 0; + } else { + return ethtool_op_get_ts_info(dev, info); + } +} + static const struct ethtool_ops tse_ethtool_ops = { .get_drvinfo = tse_get_drvinfo, .get_regs_len = tse_reglen, @@ -234,6 +261,7 @@ static const struct ethtool_ops tse_ethtool_ops = { .set_msglevel = tse_set_msglevel, .get_link_ksettings = phy_ethtool_get_link_ksettings, .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_ts_info = tse_get_ts_info, }; void altera_tse_set_ethtool_ops(struct net_device *netdev) diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 24a1d30c6780..c874b8c1dd48 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -18,14 +18,17 @@ */ #include +#include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -40,6 +43,7 @@ #include "altera_tse.h" #include "altera_sgdma.h" #include "altera_msgdma.h" +#include "intel_fpga_tod.h" static atomic_t instance_count = ATOMIC_INIT(~0); /* Module parameters */ @@ -598,7 +602,11 @@ static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev) if (ret) goto out; - skb_tx_timestamp(skb); + if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && + priv->hwts_tx_en)) + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + else + skb_tx_timestamp(skb); priv->tx_prod++; dev->stats.tx_bytes += skb->len; @@ -1238,6 +1246,13 @@ static int tse_open(struct net_device *dev) if (dev->phydev) phy_start(dev->phydev); + ret = intel_fpga_tod_init(&priv->ptp_priv); + if (ret) + netdev_warn(dev, "Failed PTP initialization\n"); + + priv->hwts_tx_en = 0; + priv->hwts_rx_en = 0; + napi_enable(&priv->napi); netif_start_queue(dev); @@ -1309,6 +1324,83 @@ static int tse_shutdown(struct net_device *dev) return 0; } +/* ioctl to configure timestamping */ +static int tse_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct altera_tse_private *priv = netdev_priv(dev); + struct hwtstamp_config config; + + if (!netif_running(dev)) + return -EINVAL; + + if (!priv->ptp_enable) { + netdev_alert(priv->dev, "Timestamping not supported"); + return -EOPNOTSUPP; + } + + if (cmd == SIOCSHWTSTAMP) { + if (copy_from_user(&config, ifr->ifr_data, + sizeof(struct hwtstamp_config))) + return -EFAULT; + + if (config.flags) + return -EINVAL; + + switch (config.tx_type) { + case HWTSTAMP_TX_OFF: + priv->hwts_tx_en = 0; + break; + case HWTSTAMP_TX_ON: + priv->hwts_tx_en = 1; + break; + default: + return -ERANGE; + } + + switch (config.rx_filter) { + case HWTSTAMP_FILTER_NONE: + priv->hwts_rx_en = 0; + config.rx_filter = HWTSTAMP_FILTER_NONE; + break; + default: + priv->hwts_rx_en = 1; + config.rx_filter = HWTSTAMP_FILTER_ALL; + break; + } + + if (copy_to_user(ifr->ifr_data, &config, + sizeof(struct hwtstamp_config))) + return -EFAULT; + else + return 0; + } + + if (cmd == SIOCGHWTSTAMP) { + config.flags = 0; + + if (priv->hwts_tx_en) + config.tx_type = HWTSTAMP_TX_ON; + else + config.tx_type = HWTSTAMP_TX_OFF; + + if (priv->hwts_rx_en) + config.rx_filter = HWTSTAMP_FILTER_ALL; + else + config.rx_filter = HWTSTAMP_FILTER_NONE; + + if (copy_to_user(ifr->ifr_data, &config, + sizeof(struct hwtstamp_config))) + return -EFAULT; + else + return 0; + } + + if (!dev->phydev) + return -EINVAL; + + return phy_mii_ioctl(dev->phydev, ifr, cmd); +} + static struct net_device_ops altera_tse_netdev_ops = { .ndo_open = tse_open, .ndo_stop = tse_shutdown, @@ -1317,6 +1409,7 @@ static struct net_device_ops altera_tse_netdev_ops = { .ndo_set_rx_mode = tse_set_rx_mode, .ndo_change_mtu = tse_change_mtu, .ndo_validate_addr = eth_validate_addr, + .ndo_do_ioctl = tse_do_ioctl, }; /* Probe Altera TSE MAC device @@ -1568,6 +1661,27 @@ static int altera_tse_probe(struct platform_device *pdev) netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret); goto err_init_phy; } + + priv->ptp_enable = of_property_read_bool(pdev->dev.of_node, + "altr,has-ptp"); + dev_info(&pdev->dev, "PTP Enable: %d\n", priv->ptp_enable); + + if (priv->ptp_enable) { + /* MAP PTP */ + ret = intel_fpga_tod_probe(pdev, &priv->ptp_priv); + if (ret) { + dev_err(&pdev->dev, "cannot map PTP\n"); + goto err_init_phy; + } + ret = intel_fpga_tod_register(&priv->ptp_priv, + priv->device); + if (ret) { + dev_err(&pdev->dev, "Failed to register PTP clock\n"); + ret = -ENXIO; + goto err_init_phy; + } + } + return 0; err_init_phy: @@ -1595,6 +1709,8 @@ static int altera_tse_remove(struct platform_device *pdev) } platform_set_drvdata(pdev, NULL); + if (priv->ptp_enable) + intel_fpga_tod_unregister(&priv->ptp_priv); altera_tse_mdio_destroy(ndev); unregister_netdev(ndev); free_netdev(ndev); diff --git a/drivers/net/ethernet/altera/intel_fpga_tod.c b/drivers/net/ethernet/altera/intel_fpga_tod.c new file mode 100644 index 000000000000..3771597642da --- /dev/null +++ b/drivers/net/ethernet/altera/intel_fpga_tod.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Intel FPGA ToD PTP Hardware Clock (PHC) Linux driver + * Copyright (C) 2015-2016 Altera Corporation. All rights reserved. + * Copyright (C) 2017-2020 Intel Corporation. All rights reserved. + * + * Author(s): + * Dalon Westergreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "altera_utils.h" +#include "intel_fpga_tod.h" + +#define NOMINAL_PPB 1000000000ULL +#define TOD_PERIOD_MAX 0xfffff +#define TOD_PERIOD_MIN 0 +#define TOD_DRIFT_ADJUST_FNS_MAX 0xffff +#define TOD_DRIFT_ADJUST_RATE_MAX 0xffff +#define TOD_ADJUST_COUNT_MAX 0xfffff +#define TOD_ADJUST_MS_MAX (((((TOD_PERIOD_MAX) >> 16) + 1) * \ + ((TOD_ADJUST_COUNT_MAX) + 1)) / \ + 1000000UL) + +/* A fine ToD HW clock offset adjustment. + * To perform the fine offset adjustment the AdjustPeriod register is used + * to replace the Period register for AdjustCount clock cycles in hardware. + */ +static int fine_adjust_tod_clock(struct intel_fpga_tod_private *priv, + u32 adjust_period, u32 adjust_count) +{ + int limit; + + csrwr32(adjust_period, priv->tod_ctrl, tod_csroffs(adjust_period)); + csrwr32(adjust_count, priv->tod_ctrl, tod_csroffs(adjust_count)); + + /* Wait for present offset adjustment update to complete */ + limit = TOD_ADJUST_MS_MAX; + while (limit--) { + if (!csrrd32(priv->tod_ctrl, tod_csroffs(adjust_count))) + break; + mdelay(1); + } + if (limit < 0) + return -EBUSY; + + return 0; +} + +/* A coarse ToD HW clock offset adjustment. + * The coarse time adjustment performs by adding or subtracting the delta value + * from the current ToD HW clock time. + */ +static int coarse_adjust_tod_clock(struct intel_fpga_tod_private *priv, + s64 delta) +{ + u32 seconds_msb, seconds_lsb, nanosec; + u64 seconds, now; + + if (delta == 0) + goto out; + + /* Get current time */ + nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec)); + seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb)); + seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb)); + + /* Calculate new time */ + seconds = (((u64)(seconds_msb & 0x0000ffff)) << 32) | seconds_lsb; + now = seconds * NSEC_PER_SEC + nanosec + delta; + + seconds = div_u64_rem(now, NSEC_PER_SEC, &nanosec); + seconds_msb = upper_32_bits(seconds) & 0x0000ffff; + seconds_lsb = lower_32_bits(seconds); + + /* Set corrected time */ + csrwr32(seconds_msb, priv->tod_ctrl, tod_csroffs(seconds_msb)); + csrwr32(seconds_lsb, priv->tod_ctrl, tod_csroffs(seconds_lsb)); + csrwr32(nanosec, priv->tod_ctrl, tod_csroffs(nanosec)); + +out: + return 0; +} + +static int intel_fpga_tod_adjust_fine(struct ptp_clock_info *ptp, + long scaled_ppm) +{ + struct intel_fpga_tod_private *priv = + container_of(ptp, struct intel_fpga_tod_private, ptp_clock_ops); + u32 tod_period, tod_rem, tod_drift_adjust_fns, tod_drift_adjust_rate; + unsigned long flags; + unsigned long rate; + int ret = 0; + u64 ppb; + + rate = clk_get_rate(priv->tod_clk); + + /* From scaled_ppm_to_ppb */ + ppb = 1 + scaled_ppm; + ppb *= 125; + ppb >>= 13; + + ppb += NOMINAL_PPB; + + tod_period = div_u64_rem(ppb << 16, rate, &tod_rem); + if (tod_period > TOD_PERIOD_MAX) { + ret = -ERANGE; + goto out; + } + + /* The drift of ToD adjusted periodically by adding a drift_adjust_fns + * correction value every drift_adjust_rate count of clock cycles. + */ + tod_drift_adjust_fns = tod_rem / gcd(tod_rem, rate); + tod_drift_adjust_rate = rate / gcd(tod_rem, rate); + + while ((tod_drift_adjust_fns > TOD_DRIFT_ADJUST_FNS_MAX) | + (tod_drift_adjust_rate > TOD_DRIFT_ADJUST_RATE_MAX)) { + tod_drift_adjust_fns = tod_drift_adjust_fns >> 1; + tod_drift_adjust_rate = tod_drift_adjust_rate >> 1; + } + + if (tod_drift_adjust_fns == 0) + tod_drift_adjust_rate = 0; + + spin_lock_irqsave(&priv->tod_lock, flags); + csrwr32(tod_period, priv->tod_ctrl, tod_csroffs(period)); + csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_period)); + csrwr32(0, priv->tod_ctrl, tod_csroffs(adjust_count)); + csrwr32(tod_drift_adjust_fns, priv->tod_ctrl, + tod_csroffs(drift_adjust)); + csrwr32(tod_drift_adjust_rate, priv->tod_ctrl, + tod_csroffs(drift_adjust_rate)); + spin_unlock_irqrestore(&priv->tod_lock, flags); + +out: + return ret; +} + +static int intel_fpga_tod_adjust_time(struct ptp_clock_info *ptp, s64 delta) +{ + struct intel_fpga_tod_private *priv = + container_of(ptp, struct intel_fpga_tod_private, ptp_clock_ops); + unsigned long flags; + u32 period, diff, rem, rem_period, adj_period; + u64 count; + int neg_adj = 0, ret = 0; + + if (delta < 0) { + neg_adj = 1; + delta = -delta; + } + + spin_lock_irqsave(&priv->tod_lock, flags); + + /* Get the maximum possible value of the Period register offset + * adjustment in nanoseconds scale. This depends on the current + * Period register setting and the maximum and minimum possible + * values of the Period register. + */ + period = csrrd32(priv->tod_ctrl, tod_csroffs(period)); + + if (neg_adj) + diff = (period - TOD_PERIOD_MIN) >> 16; + else + diff = (TOD_PERIOD_MAX - period) >> 16; + + /* Find the number of cycles required for the + * time adjustment + */ + count = div_u64_rem(delta, diff, &rem); + + if (neg_adj) { + adj_period = period - (diff << 16); + rem_period = period - (rem << 16); + } else { + adj_period = period + (diff << 16); + rem_period = period + (rem << 16); + } + + /* If count is larger than the maximum count, + * just set the time. + */ + if (count > TOD_ADJUST_COUNT_MAX) { + /* Perform the coarse time offset adjustment */ + ret = coarse_adjust_tod_clock(priv, delta); + } else { + /* Adjust the period for count cycles to adjust + * the time. + */ + if (count) + ret = fine_adjust_tod_clock(priv, adj_period, count); + + /* If there is a remainder, adjust the period for an + * additional cycle + */ + if (rem) + ret = fine_adjust_tod_clock(priv, rem_period, 1); + } + + spin_unlock_irqrestore(&priv->tod_lock, flags); + + return ret; +} + +static int intel_fpga_tod_get_time(struct ptp_clock_info *ptp, + struct timespec64 *ts) +{ + struct intel_fpga_tod_private *priv = + container_of(ptp, struct intel_fpga_tod_private, ptp_clock_ops); + u32 seconds_msb, seconds_lsb, nanosec; + unsigned long flags; + u64 seconds; + + spin_lock_irqsave(&priv->tod_lock, flags); + nanosec = csrrd32(priv->tod_ctrl, tod_csroffs(nanosec)); + seconds_lsb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_lsb)); + seconds_msb = csrrd32(priv->tod_ctrl, tod_csroffs(seconds_msb)); + spin_unlock_irqrestore(&priv->tod_lock, flags); + + seconds = (((u64)(seconds_msb & 0x0000ffff)) << 32) | seconds_lsb; + + ts->tv_nsec = nanosec; + ts->tv_sec = (__kernel_old_time_t)seconds; + + return 0; +} + +static int intel_fpga_tod_set_time(struct ptp_clock_info *ptp, + const struct timespec64 *ts) +{ + struct intel_fpga_tod_private *priv = + container_of(ptp, struct intel_fpga_tod_private, ptp_clock_ops); + u32 seconds_msb = upper_32_bits(ts->tv_sec) & 0x0000ffff; + u32 seconds_lsb = lower_32_bits(ts->tv_sec); + u32 nanosec = lower_32_bits(ts->tv_nsec); + unsigned long flags; + + spin_lock_irqsave(&priv->tod_lock, flags); + csrwr32(seconds_msb, priv->tod_ctrl, tod_csroffs(seconds_msb)); + csrwr32(seconds_lsb, priv->tod_ctrl, tod_csroffs(seconds_lsb)); + csrwr32(nanosec, priv->tod_ctrl, tod_csroffs(nanosec)); + spin_unlock_irqrestore(&priv->tod_lock, flags); + + return 0; +} + +static int intel_fpga_tod_enable_feature(struct ptp_clock_info *ptp, + struct ptp_clock_request *request, + int on) +{ + return -EOPNOTSUPP; +} + +static struct ptp_clock_info intel_fpga_tod_clock_ops = { + .owner = THIS_MODULE, + .name = "intel_fpga_tod", + .max_adj = 500000000, + .n_alarm = 0, + .n_ext_ts = 0, + .n_per_out = 0, + .pps = 0, + .adjfine = intel_fpga_tod_adjust_fine, + .adjtime = intel_fpga_tod_adjust_time, + .gettime64 = intel_fpga_tod_get_time, + .settime64 = intel_fpga_tod_set_time, + .enable = intel_fpga_tod_enable_feature, +}; + +/* Initialize PTP control block registers */ +int intel_fpga_tod_init(struct intel_fpga_tod_private *priv) +{ + struct timespec64 now; + int ret = 0; + + ret = intel_fpga_tod_adjust_fine(&priv->ptp_clock_ops, 0l); + if (ret != 0) + goto out; + + /* Initialize the hardware clock to the system time */ + ktime_get_real_ts64(&now); + intel_fpga_tod_set_time(&priv->ptp_clock_ops, &now); + + spin_lock_init(&priv->tod_lock); + +out: + return ret; +} + +/* Register the PTP clock driver to kernel */ +int intel_fpga_tod_register(struct intel_fpga_tod_private *priv, + struct device *device) +{ + int ret = 0; + + priv->ptp_clock_ops = intel_fpga_tod_clock_ops; + + priv->ptp_clock = ptp_clock_register(&priv->ptp_clock_ops, device); + if (IS_ERR(priv->ptp_clock)) { + priv->ptp_clock = NULL; + ret = -ENODEV; + } + + if (priv->tod_clk) + ret = clk_prepare_enable(priv->tod_clk); + + return ret; +} + +/* Remove/unregister the ptp clock driver from the kernel */ +void intel_fpga_tod_unregister(struct intel_fpga_tod_private *priv) +{ + if (priv->ptp_clock) { + ptp_clock_unregister(priv->ptp_clock); + priv->ptp_clock = NULL; + } + + if (priv->tod_clk) + clk_disable_unprepare(priv->tod_clk); +} + +/* Common PTP probe function */ +int intel_fpga_tod_probe(struct platform_device *pdev, + struct intel_fpga_tod_private *priv) +{ + struct resource *ptp_res; + int ret = -ENODEV; + + priv->dev = (struct net_device *)platform_get_drvdata(pdev); + + /* Time-of-Day (ToD) Clock address space */ + ret = request_and_map(pdev, "tod_ctrl", &ptp_res, + (void __iomem **)&priv->tod_ctrl); + if (ret) + goto err; + + dev_info(&pdev->dev, "\tTOD Ctrl at 0x%08lx\n", + (unsigned long)ptp_res->start); + + /* Time-of-Day (ToD) Clock period clock */ + priv->tod_clk = devm_clk_get(&pdev->dev, "tod_clk"); + if (IS_ERR(priv->tod_clk)) { + dev_err(&pdev->dev, "cannot obtain ToD period clock\n"); + ret = -ENXIO; + goto err; + } +err: + return ret; +} + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/altera/intel_fpga_tod.h b/drivers/net/ethernet/altera/intel_fpga_tod.h new file mode 100644 index 000000000000..064b97c2bf38 --- /dev/null +++ b/drivers/net/ethernet/altera/intel_fpga_tod.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Altera PTP Hardware Clock (PHC) Linux driver + * Copyright (C) 2015-2016 Altera Corporation. All rights reserved. + * Copyright (C) 2017-2020 Intel Corporation. All rights reserved. + * + * Author(s): + * Dalon Westergreen + */ + +#ifndef __INTEL_FPGA_TOD_H__ +#define __INTEL_FPGA_TOD_H__ + +#include +#include +#include +#include +#include + +/* Altera Time-of-Day (ToD) clock register space. */ +struct intel_fpga_tod { + u32 seconds_msb; + u32 seconds_lsb; + u32 nanosec; + u32 reserved1[0x1]; + u32 period; + u32 adjust_period; + u32 adjust_count; + u32 drift_adjust; + u32 drift_adjust_rate; +}; + +#define tod_csroffs(a) (offsetof(struct intel_fpga_tod, a)) + +struct intel_fpga_tod_private { + struct net_device *dev; + + struct ptp_clock_info ptp_clock_ops; + struct ptp_clock *ptp_clock; + + /* Time-of-Day (ToD) Clock address space */ + struct intel_fpga_tod __iomem *tod_ctrl; + struct clk *tod_clk; + + /* ToD clock registers protection */ + spinlock_t tod_lock; +}; + +int intel_fpga_tod_init(struct intel_fpga_tod_private *priv); +void intel_fpga_tod_uinit(struct intel_fpga_tod_private *priv); +int intel_fpga_tod_register(struct intel_fpga_tod_private *priv, + struct device *device); +void intel_fpga_tod_unregister(struct intel_fpga_tod_private *priv); +int intel_fpga_tod_probe(struct platform_device *pdev, + struct intel_fpga_tod_private *priv); + +#endif /* __INTEL_FPGA_TOD_H__ */ From patchwork Mon May 4 08:25:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ooi, Joyce" X-Patchwork-Id: 219988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97B2EC3A5A9 for ; Mon, 4 May 2020 08:29:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7284A21582 for ; Mon, 4 May 2020 08:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728370AbgEDI3R (ORCPT ); Mon, 4 May 2020 04:29:17 -0400 Received: from mga06.intel.com ([134.134.136.31]:46019 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728354AbgEDI3Q (ORCPT ); Mon, 4 May 2020 04:29:16 -0400 IronPort-SDR: RdV91FaB0/RgDTHNiqz0AAX7G71rWV9QHpA8CQ6xyrUG7+15yVQDXxYj3hQ30A0tggU5iiwP3p RDHuNFPDHU9g== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 01:29:15 -0700 IronPort-SDR: dbfHMXKA49/zFv6/sWpDJdQCXUw03pAVMvltBQWfAYxQ6jOqukhPxd4oFYA5HzLweYSdgxRnPz hjvqGZy37IKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,351,1583222400"; d="scan'208";a="295436191" Received: from pg-nxl3.altera.com ([10.142.129.93]) by orsmga008.jf.intel.com with ESMTP; 04 May 2020 01:29:12 -0700 From: Joyce Ooi To: Thor Thayer , "David S . Miller" Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dalon Westergreen , Joyce Ooi , Tan Ley Foon , See Chin Liang , Dinh Nguyen , Rob Herring , devicetree@vger.kernel.org Subject: [PATCHv2 10/10] net: eth: altera: update devicetree bindings documentation Date: Mon, 4 May 2020 16:25:58 +0800 Message-Id: <20200504082558.112627-11-joyce.ooi@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200504082558.112627-1-joyce.ooi@intel.com> References: <20200504082558.112627-1-joyce.ooi@intel.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dalon Westergreen Update devicetree bindings documentation to include msgdma prefetcher and ptp bindings. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Dalon Westergreen Signed-off-by: Joyce Ooi --- v2: no change --- .../devicetree/bindings/net/altera_tse.txt | 103 +++++++++++++++++---- 1 file changed, 84 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt index 0b7d4d3758ea..2f2d12603907 100644 --- a/Documentation/devicetree/bindings/net/altera_tse.txt +++ b/Documentation/devicetree/bindings/net/altera_tse.txt @@ -2,53 +2,86 @@ Required properties: - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should - be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. + be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE, + and "altr,tse-msgdma-2.0" for MSGDMA with prefetcher based + implementations. ALTR is supported for legacy device trees, but is deprecated. altr should be used for all new designs. - reg: Address and length of the register set for the device. It contains the information of registers in the same order as described by reg-names - reg-names: Should contain the reg names - "control_port": MAC configuration space region - "tx_csr": xDMA Tx dispatcher control and status space region - "tx_desc": MSGDMA Tx dispatcher descriptor space region - "rx_csr" : xDMA Rx dispatcher control and status space region - "rx_desc": MSGDMA Rx dispatcher descriptor space region - "rx_resp": MSGDMA Rx dispatcher response space region - "s1": SGDMA descriptor memory - interrupts: Should contain the TSE interrupts and it's mode. - interrupt-names: Should contain the interrupt names - "rx_irq": xDMA Rx dispatcher interrupt - "tx_irq": xDMA Tx dispatcher interrupt + "rx_irq": DMA Rx dispatcher interrupt + "tx_irq": DMA Tx dispatcher interrupt - rx-fifo-depth: MAC receive FIFO buffer depth in bytes - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes - phy-mode: See ethernet.txt in the same directory. - phy-handle: See ethernet.txt in the same directory. - phy-addr: See ethernet.txt in the same directory. A configuration should include phy-handle or phy-addr. -- altr,has-supplementary-unicast: - If present, TSE supports additional unicast addresses. - Otherwise additional unicast addresses are not supported. -- altr,has-hash-multicast-filter: - If present, TSE supports a hash based multicast filter. - Otherwise, hash-based multicast filtering is not supported. - - mdio device tree subnode: When the TSE has a phy connected to its local mdio, there must be device tree subnode with the following required properties: - - compatible: Must be "altr,tse-mdio". - #address-cells: Must be <1>. - #size-cells: Must be <0>. For each phy on the mdio bus, there must be a node with the following fields: - - reg: phy id used to communicate to phy. - device_type: Must be "ethernet-phy". The MAC address will be determined using the optional properties defined in ethernet.txt. +- altr,has-supplementary-unicast: + If present, TSE supports additional unicast addresses. + Otherwise additional unicast addresses are not supported. +- altr,has-hash-multicast-filter: + If present, TSE supports a hash based multicast filter. + Otherwise, hash-based multicast filtering is not supported. +- altr,has-ptp: + If present, TSE supports 1588 timestamping. Currently only + supported with the msgdma prefetcher. +- altr,tx-poll-cnt: + Optional cycle count for Tx prefetcher to poll descriptor + list. If not present, defaults to 128, which at 125MHz is + roughly 1usec. Only for "altr,tse-msgdma-2.0". +- altr,rx-poll-cnt: + Optional cycle count for Tx prefetcher to poll descriptor + list. If not present, defaults to 128, which at 125MHz is + roughly 1usec. Only for "altr,tse-msgdma-2.0". + +Required registers by compatibility string: + - "altr,tse-1.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "rx_csr" : DMA Rx dispatcher control and status space region + "s1": DMA descriptor memory + + - "altr,tse-msgdma-1.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "tx_desc": DMA Tx dispatcher descriptor space region + "rx_csr" : DMA Rx dispatcher control and status space region + "rx_desc": DMA Rx dispatcher descriptor space region + "rx_resp": DMA Rx dispatcher response space region + + - "altr,tse-msgdma-2.0" + "control_port": MAC configuration space region + "tx_csr": DMA Tx dispatcher control and status space region + "tx_pref": DMA Tx prefetcher configuration space region + "rx_csr" : DMA Rx dispatcher control and status space region + "rx_pref": DMA Rx prefetcher configuration space region + "tod_ctrl": Time of Day Control register only required when + timestamping support is enabled. Timestamping is + only supported with the msgdma-2.0 implementation. + +Optional properties: +- local-mac-address: See ethernet.txt in the same directory. +- max-frame-size: See ethernet.txt in the same directory. + Example: tse_sub_0_eth_tse_0: ethernet@1,00000000 { @@ -86,6 +119,11 @@ Example: device_type = "ethernet-phy"; }; + phy2: ethernet-phy@2 { + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; }; @@ -111,3 +149,30 @@ Example: altr,has-hash-multicast-filter; phy-handle = <&phy1>; }; + + + tse_sub_2_eth_tse_0: ethernet@1,00002000 { + compatible = "altr,tse-msgdma-2.0"; + reg = <0x00000001 0x00002000 0x00000400>, + <0x00000001 0x00002400 0x00000020>, + <0x00000001 0x00002420 0x00000020>, + <0x00000001 0x00002440 0x00000020>, + <0x00000001 0x00002460 0x00000020>, + <0x00000001 0x00002480 0x00000040>; + reg-names = "control_port", "rx_csr", "rx_pref","tx_csr", "tx_pref", "tod_ctrl"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 45 4>, <0 44 4>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + address-bits = <48>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "sgmii"; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + altr,has-ptp; + altr,tx-poll-cnt = <128>; + altr,rx-poll-cnt = <32>; + phy-handle = <&phy2>; + };