From patchwork Mon Sep 18 09:02:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 112867 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3429269qgf; Mon, 18 Sep 2017 02:02:30 -0700 (PDT) X-Received: by 10.98.62.196 with SMTP id y65mr31823705pfj.282.1505725350635; Mon, 18 Sep 2017 02:02:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505725350; cv=none; d=google.com; s=arc-20160816; b=agYz0B6in25lg5fUoeVQYjkw/+t3UB/3cgW6CRWx9sw2QngAY8FhOEMEoVSe27zBZr b17/8wQ2HQ1e2ivd1nrbTZkDdlQBvTXNkPf7uS1rzm+wuwKPGueJQX1QEOHLaTvB/+6b 8mU8qMvNWyqpNH/7vAN10v9iDMEHC0drccFu+5gcIxgKIQTpv70vVBKzCVVuRSUq4xGS 99lQTL9sqpVp5NH4Df8s174Ndt7KKWXwdGiOvh3xpl7wABbgtpUuCEezIsYvTxMTWxUB cF5+8Gbf4xElWQ65NCmKyLX8yXhPWRatoTYzQg/aaXyZOHSmZroBtwD6rxuFRzVkYSEb HyNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=seTiiR3zesRvCUWuYvprBeV17OfPNGjjqqm8KJ9u0q8=; b=KWSyy4+KoxSiNxDt6Hz8/HZWTCMjJ9mrtfVFLSGf9fnIBU4WqxD5mLs4ZVfq9JSKmp 0g6OqX+uwJwb187TpT/p8ZVv/CXR64WwgumzGaZGObTei0HTF4u1AN3uU3/u4/Tg3C/9 FaAFfGaAplE0y5aTfmxv/mM7guDPwnyGwDftPhOWW48sBHp67zfF7sYfcLGf1L67i+gu 3yHkYc0EccWJRrp4ww1rSFmyzgsosK78SblvJmMenOtBA6rGPBIwenhRsNySnD7HWAhi OQoOskkUT7JN7Jh/M/5DYXJ4KNccpzLn4ebvvIPt0OSvseDnAnXNecvp87TI0ZUfm4Q2 4upw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=To+oB5at; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j21si4341163pgn.554.2017.09.18.02.02.30; Mon, 18 Sep 2017 02:02:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=To+oB5at; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752831AbdIRJC3 (ORCPT + 6 others); Mon, 18 Sep 2017 05:02:29 -0400 Received: from mail-wr0-f181.google.com ([209.85.128.181]:46541 "EHLO mail-wr0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752574AbdIRJC1 (ORCPT ); Mon, 18 Sep 2017 05:02:27 -0400 Received: by mail-wr0-f181.google.com with SMTP id o42so5601714wrb.3 for ; Mon, 18 Sep 2017 02:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YZkvLLnOrDqn/tKfFrRcpNBdUpvycVHgRe5N6Taqc4s=; b=To+oB5atAao2ZmG73CgF9q+oRPnrMJszvUwvWghwhZTm2FHaHTb2Zy8Ha2BKQdH8wC 5zfIyakjnPF+MJQPRw32dmGkLNdGHHJKlrYIWQHW4wiZjemsqH/f3tU3Rc1ACYKmBLU4 HbMchMENBZzpitYW2Q7IiU1mDseG6KA0+3mmU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YZkvLLnOrDqn/tKfFrRcpNBdUpvycVHgRe5N6Taqc4s=; b=hQYFoBY4CG9nIM7VfmYJ0HRpFMNaB6EL66Yjku4gdKPlLyvHJHFLfjF8lv1CcqbU+z kt2sV3/cPdl6dUB+YSvmr+AHH1GBL5anNxvqRinPzUdu4/PnnkgRwpkMoQDDn7KSpFrJ pswvaT5hSgcsgDx12Edv5aW3TF1DyJluxqkCqHCvYfIAM/v39OQoEkfduCBHyix05MRB LYbAvIagNUBuEgRiTPwbOJm693X15Z17rVuolHe0ojapb3kkDwSN7NQ2lGqdcjnlQPCx aGSAAJo7o8ppjdUwmWNbE9DPhAOEEt8a55PjBYO0+4wp+VOmvqMcl8ZqI5m8zigk8uy6 QsjA== X-Gm-Message-State: AHPjjUh1XTkxsSqh0chxmKwNM7+nK74xqn54aT3DyTtePOy8FNbRXtfC dL+k9Tv4gdGRfgmG X-Google-Smtp-Source: ADKCNb76LzhzAXxtSXlRqBzzExIaLP7DdsoRkDH2q3ioW1WHUPXB9RqcDs0XukLqOdDBInTP8ZMqeg== X-Received: by 10.223.162.211 with SMTP id t19mr26185818wra.82.1505725345498; Mon, 18 Sep 2017 02:02:25 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.140]) by smtp.gmail.com with ESMTPSA id p80sm6201554wmf.42.2017.09.18.02.02.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Sep 2017 02:02:24 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v2 1/2] clocksource: stm32: rework driver to use only one timer Date: Mon, 18 Sep 2017 11:02:14 +0200 Message-Id: <1505725335-27081-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> References: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rework driver code to use only one timer for both clocksource and clockevent. This patch also forbid to use 16 bits timers because they are not enough accurate. Do some clean up in structure and functions names too. Signed-off-by: Benjamin Gaignard Signed-off-by: Ludovic Barre --- drivers/clocksource/timer-stm32.c | 259 +++++++++++++++++++++++--------------- 1 file changed, 155 insertions(+), 104 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..e517e24 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,175 +16,226 @@ #include #include #include +#include +#include #define TIM_CR1 0x00 #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { +struct stm32_clock_event { struct clock_event_device evtdev; unsigned periodic_top; - void __iomem *base; + void __iomem *regs; }; static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct stm32_clock_event *ce = + container_of(evtdev, struct stm32_clock_event, evtdev); + + writel_relaxed(0, ce->regs + TIM_DIER); - writel_relaxed(0, base + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *evtdev) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct stm32_clock_event *ce = + container_of(evtdev, struct stm32_clock_event, evtdev); + unsigned long cnt; + + cnt = readl_relaxed(ce->regs + TIM_CNT); + writel_relaxed(cnt + evt, ce->regs + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, ce->regs + TIM_DIER); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct stm32_clock_event *ce = + container_of(evtdev, struct stm32_clock_event, evtdev); - writel_relaxed(evt, data->base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + return stm32_clock_event_set_next_event(ce->periodic_top, evtdev); +} - return 0; +static int stm32_clock_event_set_oneshot(struct clock_event_device *evtdev) +{ + return stm32_clock_event_set_next_event(0, evtdev); } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct stm32_clock_event *ce = dev_id; + + writel_relaxed(0, ce->regs + TIM_SR); - writel_relaxed(0, data->base + TIM_SR); + if (clockevent_state_periodic(&ce->evtdev)) + stm32_clock_event_set_periodic(&ce->evtdev); - data->evtdev.event_handler(&data->evtdev); + if (clockevent_state_oneshot(&ce->evtdev)) + stm32_clock_event_shutdown(&ce->evtdev); + + ce->evtdev.event_handler(&ce->evtdev); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; +static int __init stm32_clockevent_init(struct device_node *np, + void __iomem *base, + struct clk *clk, int irq) +{ + struct stm32_clock_event *ce; + unsigned long rate; + int err; + + ce = kzalloc(sizeof(*ce), GFP_KERNEL); + if (!ce) + return -ENOMEM; + + ce->regs = base; + ce->evtdev.name = "stm32_clockevent"; + ce->evtdev.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; + ce->evtdev.set_state_shutdown = stm32_clock_event_shutdown; + ce->evtdev.set_state_periodic = stm32_clock_event_set_periodic; + ce->evtdev.set_state_oneshot = stm32_clock_event_set_oneshot; + ce->evtdev.tick_resume = stm32_clock_event_shutdown; + ce->evtdev.set_next_event = stm32_clock_event_set_next_event; + ce->evtdev.rating = 200; -static int __init stm32_clockevent_init(struct device_node *np) + rate = clk_get_rate(clk); + ce->periodic_top = DIV_ROUND_CLOSEST(rate, HZ); + + writel_relaxed(0, ce->regs + TIM_DIER); + writel_relaxed(0, ce->regs + TIM_SR); + + err = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, + "stm32 clockevent", ce); + if (err) { + kfree(ce); + return err; + } + + clockevents_config_and_register(&ce->evtdev, rate, 0x60, ~0U); + + return 0; +} + +static void __iomem *stm32_timer_cnt __read_mostly; +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct device_node *node, + void __iomem *regs, + struct clk *clk) +{ + unsigned long rate; + + rate = clk_get_rate(clk); + + writel_relaxed(~0U, regs + TIM_ARR); + writel_relaxed(0, regs + TIM_PSC); + writel_relaxed(0, regs + TIM_SR); + writel_relaxed(0, regs + TIM_DIER); + writel_relaxed(0, regs + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, regs + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, regs + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + regs + TIM_CR1); + + stm32_timer_cnt = regs + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, rate); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + rate, 250, 32, clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; + void __iomem *timer_base; + unsigned long max_arr; + struct clk *clk; + int irq, err = -EINVAL; - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; + timer_base = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(timer_base)) { + pr_err("Can't map registers\n"); + goto out; } - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) { + pr_err("Can't parse IRQ\n"); + goto out_unmap; } - rate = clk_get_rate(clk); + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) { + pr_err("Can't get timer clock\n"); + goto out_unmap; + } - rstc = of_reset_control_get(np, NULL); + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; + err = clk_prepare_enable(clk); + if (err) { + pr_err("Couldn't enable parent clock\n"); + goto out_clk; } /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + writel_relaxed(~0U, timer_base + TIM_ARR); + max_arr = readl_relaxed(timer_base + TIM_ARR); + if (max_arr != ~0U) { + err = -EINVAL; + pr_err("32 bits timer is needed\n"); + goto out_unprepare; } - writel_relaxed(0, data->base + TIM_ARR); - - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); - - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); + err = stm32_clocksource_init(node, timer_base, clk); + if (err) + goto out_unprepare; - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + err = stm32_clockevent_init(node, timer_base, clk, irq); + if (err) + goto out_unprepare; - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: +out_unprepare: clk_disable_unprepare(clk); -err_clk_enable: +out_clk: clk_put(clk); -err_clk_get: - return ret; +out_unmap: + iounmap(timer_base); +out: + return err; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Mon Sep 18 09:02:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 112868 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3429493qgf; Mon, 18 Sep 2017 02:02:44 -0700 (PDT) X-Received: by 10.98.80.85 with SMTP id e82mr32440265pfb.265.1505725364542; Mon, 18 Sep 2017 02:02:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505725364; cv=none; d=google.com; s=arc-20160816; b=DavPtXzVqFwrtOZ9L850RgcjX8Z34rvmIroDbn+bMVHS4ohn7+SblRR4DGUkhRyAlm RFAb3uV8zUtvWOkIN905Jk95TBAd5wOgKuj32L2pqat7tlla7ezWURsQx5XqwVkrREH5 sNZG6EcU02169cU+ynTiPIMrQF2DujS3IOBWoiKUL1AZ8FfK98uB80ZhGE4PGmz/8VlW Rt5guzNRy1OXXPutidB47uDEO77EMpDkK0odagDpBuLagaN8cKfnWlGXdBeQjKX+3Kk6 q/j88KaGsmcR19+L4pqv1qhYUt16HtYgg0u+dPldVxyZx4Or9qAJjIQNIjUsrK/jfaTk H3+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[209.132.180.67]) by mx.google.com with ESMTP id a59si4681282plc.638.2017.09.18.02.02.44; Mon, 18 Sep 2017 02:02:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UjJYgVxJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830AbdIRJCm (ORCPT + 6 others); Mon, 18 Sep 2017 05:02:42 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:48648 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752829AbdIRJC3 (ORCPT ); Mon, 18 Sep 2017 05:02:29 -0400 Received: by mail-wm0-f47.google.com with SMTP id r68so635623wmg.3 for ; Mon, 18 Sep 2017 02:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=UjJYgVxJHL5Z57xPlVGFEYWbLF32Acm2wxF893Mb+W8qYauS7OrPFMsNq/GOch3dsF tPNg0Y6qwNsylSMOo/bB0sLYwUBBxH0hwBV6VV4wU4lKREpWZFIP9hofighxXrAV9/yG lk/7Q3sgq+2vCnydhoilasJE8h6lX8veLbUPM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G5YIS7hIBYSgFWZ67w6lo4uUDWPfdt4dfSo7J/z81lU=; b=CmbEw/D496YAF+DPDfdDAyrd0b4jEEOoO4HdqhWayUGDilpMfq07FvM/2oYaZwX2UY 8uB1YW5HUk1iOmo4ujAYFtO8YgYJP3yuiba+GvQdFRrtQOY9QIEIFjeTdXCshV4fXk4Q Bk6BreU3YO3wRkEfmw8+9GJZUyvGrwfCJAPV07EHPZ0eQY/7gr/5fh11Ts1YywD+0tBP wta/5OvwF1omu0j6rhdTkAFzK6zIiM5U4p7as14Esoak8TLf0gbjZZ63eU4+I4YcQ9lV /slHw3hZcJ8jCYDE7ywbpUptPrfly7TwyvN8vBB7p1IElbTZiozk5qe3nJDzyc4mSFpn BTgA== X-Gm-Message-State: AHPjjUjkkgJSI+23+vzy/rYwXfJADSNCzDpJwnMP6nG3FD0Zu7relbjT +Gn5UhtAtyz4xQmDd6jBKw== X-Google-Smtp-Source: AOwi7QC8SWxcN7nI1zXCl7IC8sUvwUIEDIW1Vjvum0xGVEg7JJimBnvgPjEg0dub2JYsqYuQYjNSuw== X-Received: by 10.28.66.65 with SMTP id p62mr8516654wma.159.1505725347893; Mon, 18 Sep 2017 02:02:27 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.140]) by smtp.gmail.com with ESMTPSA id p80sm6201554wmf.42.2017.09.18.02.02.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Sep 2017 02:02:27 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v2 2/2] arm: dts: stm32: remove useless clocksource nodes Date: Mon, 18 Sep 2017 11:02:15 +0200 Message-Id: <1505725335-27081-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> References: <1505725335-27081-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16 bits timers aren't accurate enough to be used as clocksource, remove them from stm32f4 and stm32f7 devicetree. Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32f429.dtsi | 32 -------------------------------- arch/arm/boot/dts/stm32f746.dtsi | 32 -------------------------------- 2 files changed, 64 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index a8113dc..fd211cb 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -108,14 +108,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -137,14 +129,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +178,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +194,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 4506eb9..c4d0273 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -82,22 +82,6 @@ status = "disabled"; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; @@ -105,22 +89,6 @@ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>;