From patchwork Sun Sep 17 10:33:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 112831 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2536479qgf; Sun, 17 Sep 2017 03:33:59 -0700 (PDT) X-Received: by 10.99.42.11 with SMTP id q11mr28480149pgq.7.1505644439269; Sun, 17 Sep 2017 03:33:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505644439; cv=none; d=google.com; s=arc-20160816; b=M2wBkAI9Ehd9qGvrnUMF1lL9TMDLoDXGRaSHJswyBrX3OFGS8MaMKQIivrkSxuy8ek lWEAxrysyA7dDejIRDLxClMt7LmD1mshUEnYy/TKUEM0a6G/+ZXKK2xzpEc+gTklSAL2 hKaK0NVdzKv23FwbTtoqloSdADPX9FCUH5XmlY3drC3/B8xoW07jgiDWLga0ZMNgZm+Z u0j+/uTU6bACbe94FE0Jj6JA4UQfOmM7WNcep5DYKcV627wn1UuJiGDHY6ee+NLU7qfF jwaWnZ0F8MCv0lQn9vIGUtSkpI81YZ4By+fPGO1fkTwAA0LRaiIYeGe1zrLPHMB6Uzau oaWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=0iI3KX5fNeDPYgLPR7z02hvOLsuDPB61us51RiIDezM=; b=QcXoNJMRD34gpOLxJe8TRg1IOlgLLeUPMfKr7XJ4afjOFNEp4arJQjVSE32fngQvYt C5FpI3ZjHFnlfRYQ1Y77Iyhql7GAnOMUpcetNJNE2koowWPn3BQcTVMUYiQZyf0PacWc PolHDYPpgjTHKTw5+e0cjr3Ac4EKa0wfRxyfEcS16B4mEXekLqlZ4PasJC8idSha7w1S oDXuV3NiSV6l38VWkQ13QzqQmW2Tq0ZCIsM07tMa7rcr6mpnQUjn4gS/rhnQEFMuCkDb YX1qKmiG5m2YJJHiuldcIs6kCiB/0dcFPimfjcOg3oN+2tdIjdtra7E95J7oB040A1e+ 5a5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D61MZHqT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id k11sm4615245wrc.90.2017.09.17.03.33.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Sep 2017 03:33:48 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Greg Kroah-Hartman Cc: linux-kernel@vger.kernel.org, Oleksij Rempel , Srinivas Kandagatla Subject: [PATCH 1/2] nvmem: dt: document SNVS LPGPR binding Date: Sun, 17 Sep 2017 12:33:42 +0200 Message-Id: <20170917103343.18468-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170917103343.18468-1-srinivas.kandagatla@linaro.org> References: <20170917103343.18468-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Oleksij Rempel Documentation bindings for the Low Power General Purpose Register available on i.MX6 SoCs in the Secure Non-Volatile Storage. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt -- 2.11.0 diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt new file mode 100644 index 000000000000..20bc49b49799 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt @@ -0,0 +1,20 @@ +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D +Secure Non-Volatile Storage. + +This DT node should be represented as a sub-node of a "syscon", +"simple-mfd" node. + +Required properties: +- compatible: should be one of the fallowing variants: + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S + "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL + +Example: +snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6q-snvs-lpgpr"; + }; +}; From patchwork Sun Sep 17 10:33:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 112832 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2536519qgf; Sun, 17 Sep 2017 03:34:03 -0700 (PDT) X-Received: by 10.98.157.73 with SMTP id i70mr29135012pfd.268.1505644443715; Sun, 17 Sep 2017 03:34:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505644443; cv=none; d=google.com; s=arc-20160816; b=zohnfSzp9BHGY0tGvKA7N1oSOJ12yq6rmfGanNRzjMd9GqYKm9pk3S7nxsFkG6CjCb d5z7q3nQnAOAh0nkojYhLseIrl9v8vNSqWXMco6By2Bqkz6OaVmZXHaw24MKwOXmUxdi fpUTCq2i1hWfz1Rts1vbOIYYyT2vks/qcuG7D1SH7QKLpM+0WBYD/tV4MyeU/L8sUY6y t8U6YtjCfryDWefIWRiQeVgujT4glFafRmq0wg/bPMIXSQLb4h2um8kUBUCXH2TBWzV2 qWC1auU1WMXSExcOADuAidQhO8E6QpnBUevjOdMx+N5LLGAML2K96Gantnuy7vzD6aNo X35Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1IYPEm7ymKt4uhwmsUQzsyIdeFPSJUnK7Ixl9NSpNSg=; b=Jkx3dnipvPcVyBXlhLDbcrjpWECOMDUQmCV6/EtkLxGZuy+oYqEVERVq4InTjd8rYT jRxzhv2Z88RdpFv/9RCE30P+YQjiZWNOFKQC8D2OY9gqDwUmqfaFKLz1gKmt4SYcFCnP sszvfW1YyvmgNY8zjnEo06OVX+Wj8Ryp7kzbZNXG8mTiBA34ONIoQni6V43PEHNBDndr Anq2Ou+IZ/T6r3nodqCIZAcSN5Xeoq83O1sHyGxs0TTPZ9yWPZupW++VVYXS2YVa5Ui5 LTdX+sR/PsFopinZGAaUCzjVYBYNXbs5fgJ+KM0+K3LUsy6N/eZ1us1N/aERMIK9Ypz8 hIkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P6k/ErBi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[46.4.26.8]) by smtp.gmail.com with ESMTPSA id k11sm4615245wrc.90.2017.09.17.03.33.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Sep 2017 03:33:49 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Greg Kroah-Hartman Cc: linux-kernel@vger.kernel.org, Oleksij Rempel , Srinivas Kandagatla Subject: [PATCH 2/2] nvmem: add snvs_lpgpr driver Date: Sun, 17 Sep 2017 12:33:43 +0200 Message-Id: <20170917103343.18468-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170917103343.18468-1-srinivas.kandagatla@linaro.org> References: <20170917103343.18468-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Oleksij Rempel This is a driver for Low Power General Purpose Register (LPGPR) available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. It is a 32-bit read/write register located in the low power domain. Since LPGPR is located in the battery-backed power domain, LPGPR can be used by any application for retaining data during an SoC power-down mode. Signed-off-by: Oleksij Rempel Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/snvs_lpgpr.c | 156 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 168 insertions(+) create mode 100644 drivers/nvmem/snvs_lpgpr.c -- 2.11.0 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 101ced4c84be..ea3044c5d6ee 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -144,4 +144,14 @@ config MESON_EFUSE This driver can also be built as a module. If so, the module will be called nvmem_meson_efuse. +config NVMEM_SNVS_LPGPR + tristate "Support for Low Power General Purpose Register" + depends on SOC_IMX6 || COMPILE_TEST + help + This is a driver for Low Power General Purpose Register (LPGPR) available on + i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. + + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + endif diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 173140658693..4c589184acee 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o nvmem-vf610-ocotp-y := vf610-ocotp.o obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o nvmem_meson_efuse-y := meson-efuse.o +obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o +nvmem_snvs_lpgpr-y := snvs_lpgpr.o diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c new file mode 100644 index 000000000000..e5c2a4a17f03 --- /dev/null +++ b/drivers/nvmem/snvs_lpgpr.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2015 Pengutronix, Steffen Trumtrar + * Copyright (c) 2017 Pengutronix, Oleksij Rempel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#define IMX6Q_SNVS_HPLR 0x00 +#define IMX6Q_GPR_SL BIT(5) +#define IMX6Q_SNVS_LPLR 0x34 +#define IMX6Q_GPR_HL BIT(5) +#define IMX6Q_SNVS_LPGPR 0x68 + +struct snvs_lpgpr_cfg { + int offset; + int offset_hplr; + int offset_lplr; +}; + +struct snvs_lpgpr_priv { + struct device_d *dev; + struct regmap *regmap; + struct nvmem_config cfg; + const struct snvs_lpgpr_cfg *dcfg; +}; + +static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = { + .offset = IMX6Q_SNVS_LPGPR, + .offset_hplr = IMX6Q_SNVS_HPLR, + .offset_lplr = IMX6Q_SNVS_LPLR, +}; + +static int snvs_lpgpr_write(void *context, unsigned int offset, void *val, + size_t bytes) +{ + struct snvs_lpgpr_priv *priv = context; + const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; + unsigned int lock_reg; + int ret; + + ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); + if (ret < 0) + return ret; + + if (lock_reg & IMX6Q_GPR_SL) + return -EPERM; + + ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); + if (ret < 0) + return ret; + + if (lock_reg & IMX6Q_GPR_HL) + return -EPERM; + + return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, + bytes / 4); +} + +static int snvs_lpgpr_read(void *context, unsigned int offset, void *val, + size_t bytes) +{ + struct snvs_lpgpr_priv *priv = context; + const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; + + return regmap_bulk_read(priv->regmap, dcfg->offset + offset, + val, bytes / 4); +} + +static int snvs_lpgpr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct device_node *syscon_node; + struct snvs_lpgpr_priv *priv; + struct nvmem_config *cfg; + struct nvmem_device *nvmem; + const struct snvs_lpgpr_cfg *dcfg; + + if (!node) + return -ENOENT; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dcfg = of_device_get_match_data(dev); + if (!dcfg) + return -EINVAL; + + syscon_node = of_get_parent(node); + if (!syscon_node) + return -ENODEV; + + priv->regmap = syscon_node_to_regmap(syscon_node); + of_node_put(syscon_node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->dcfg = dcfg; + + cfg = &priv->cfg; + cfg->priv = priv; + cfg->name = dev_name(dev); + cfg->dev = dev; + cfg->stride = 4, + cfg->word_size = 4, + cfg->size = 4, + cfg->owner = THIS_MODULE, + cfg->reg_read = snvs_lpgpr_read, + cfg->reg_write = snvs_lpgpr_write, + + nvmem = nvmem_register(cfg); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +static int snvs_lpgpr_remove(struct platform_device *pdev) +{ + struct nvmem_device *nvmem = platform_get_drvdata(pdev); + + return nvmem_unregister(nvmem); +} + +static const struct of_device_id snvs_lpgpr_dt_ids[] = { + { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q }, + { .compatible = "fsl,imx6ul-snvs-lpgpr", + .data = &snvs_lpgpr_cfg_imx6q }, + { }, +}; +MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids); + +static struct platform_driver snvs_lpgpr_driver = { + .probe = snvs_lpgpr_probe, + .remove = snvs_lpgpr_remove, + .driver = { + .name = "snvs_lpgpr", + .of_match_table = snvs_lpgpr_dt_ids, + }, +}; +module_platform_driver(snvs_lpgpr_driver); + +MODULE_AUTHOR("Oleksij Rempel "); +MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage"); +MODULE_LICENSE("GPL v2");