From patchwork Fri Sep 15 23:35:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 112765 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1168347qgf; Fri, 15 Sep 2017 16:35:36 -0700 (PDT) X-Received: by 10.84.233.70 with SMTP id k6mr6020737plt.138.1505518536074; Fri, 15 Sep 2017 16:35:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505518536; cv=none; d=google.com; s=arc-20160816; b=VJUSk81BdYXett6pfN+Nwa6T7sKti/ROszcLUiliU3enJL8DpXXqOdob9ZWpiw2iF/ Y9YWU5DPR55luQFrtW3NS8KgE7lrcHRUOcxlsNxhIRoL8WAxOVhfdOYgGUurjDpXh3OX NDKFX83AwCkdfp7kO1ep8cOlpFpiY/TY3SOl7MpeKwOdGKJJJ7A/bOdMb99b4hde8a8+ 7MkwN2TvKhcUxfJt/F1nqDwZOWlX3Do18SMah7rvbmJJT1qR9HtP/pOtxqiLh1eMHpQB xpt/GXIDwVTUG/zOc0kJWlrbgdL+LgwIxKxgmco24EcEry477a4HbYaxJBXE71KHNqlE vl9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=RrJEhCMjMI6Ti3hC63AnfauZMLl8/I4jjGQRdP3UgCc=; b=ZnSn+Q/NCe7BAZgfY9JQUOkDod6vdkOQjw9Q/3R5jK+46cMc1cN3NcqompAtRKesGO VEyPBXdsYBTdSVJkWG8iSv0qfxUqUciYuzObbBCPQBZ+aZoVxhtVa0jrYRySQoqkMPoT /hrhZ1g2A8dDuwsPMtG9BOaxG83Ry31l7THQ/jMdY7fW5H7qzSk5XFbsjsAs1kS+KLqG 36hSU0VzLHdcE1yhbSomqx5XmZVB7KT5lO2+eIXdCxim2PXuXxcOeECr3ldsFywTBw28 21ag7/fLj4PS4QUCXKCTNm5drSSKSgCPfgOCgFjnuuz7CYfOw8Vqswwbq0j4stu9lUuS 0X5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JpvwjBs+; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u63si1252494pgb.248.2017.09.15.16.35.35; Fri, 15 Sep 2017 16:35:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JpvwjBs+; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751621AbdIOXfe (ORCPT + 9 others); Fri, 15 Sep 2017 19:35:34 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:52044 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751593AbdIOXfc (ORCPT ); Fri, 15 Sep 2017 19:35:32 -0400 Received: by mail-pf0-f173.google.com with SMTP id b70so2177224pfl.8 for ; Fri, 15 Sep 2017 16:35:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dMN2e9183XTHf+ZicZvF5PkAcf3bJ4w04dIcRIxAdLw=; b=JpvwjBs+xSOQJlKY9TkgZjJGWEPE3rM6MfJ9Pgq5LjDn3ClsmR7pfxX20DgC4ZI5Kx YtN/lVW4m1Zy+6F/E0X1ggYKrglneT7mZKAOvOq2q87CP/Dn/23+N5eFw0Q+/n745qKn PpSu7GS1ov3yYSGzuNu/HZR2el3n9JDLHDlss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dMN2e9183XTHf+ZicZvF5PkAcf3bJ4w04dIcRIxAdLw=; b=nICZgj5TXoMkvq6KNC0VICkqjCYqmcm02NPqax02N9bR2b3aa78QFKe/84eww11EQy lanR2fT9RNct8pwFfg/5Qkir0SwM5NxKIVwJ3Psa2uuCK2+r1lOUhCKS/3PB6LEc19Z9 j+BFiPLnWzNbCauqQDi6P4vzGAjL1J6Q9yWfJOcwu42k+ESvCCAb0kvXMsgET3J6ZcS5 6I3XLVjsWKqO0GXStVCTXbvf6z0YKa6CIy+LnnyGgNLQVsFAl7KgB64RMceYDoQ8Jnco aJhz4XFCRFCWodKAE2+DiTCmGuUjgJxOlvfQyKdlhQX1OAOiYEs68Q+ahWKiAPlii0Kj IwQg== X-Gm-Message-State: AHPjjUj60TBWz/Kmx4Y39qI1z00/Q4QafWPpHiIAoNa/WWoPY+ioSHi+ yjZJrWY6OPujSWBs X-Google-Smtp-Source: AOwi7QBmAIwjQx+9YiwMp9J7k8maVhuZzk8jbkmqggry3qQFGRVlNpiAtYJxVR7FKLvBf5KnhVAxLA== X-Received: by 10.98.192.18 with SMTP id x18mr1194822pff.2.1505518531501; Fri, 15 Sep 2017 16:35:31 -0700 (PDT) Received: from localhost.localdomain (ip68-111-217-79.sd.sd.cox.net. [68.111.217.79]) by smtp.gmail.com with ESMTPSA id 78sm3924751pfk.70.2017.09.15.16.35.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Sep 2017 16:35:30 -0700 (PDT) From: Bjorn Andersson To: Adrian Hunter , Ulf Hansson , Rob Herring , Mark Rutland Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Venkat Gopalakrishnan , Ritesh Harjani , devicetree@vger.kernel.org Subject: [PATCH v2 2/2] mmc: sdhci-msm: Enable delay circuit calibration clocks Date: Fri, 15 Sep 2017 16:35:24 -0700 Message-Id: <20170915233524.1375-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170915233524.1375-1-bjorn.andersson@linaro.org> References: <20170915233524.1375-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The delay circuit used to support HS400 is calibrated based on two additional clocks. When these clocks are not available and FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on some platforms this doesn't work properly and below dump can be seen in the kernel log. mmc0: Reset 0x1 never completed. mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00001102 mmc0: sdhci: Blk size: 0x00004000 | Blk cnt: 0x00000000 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 mmc0: sdhci: Present: 0x01f80000 | Host ctl: 0x00000000 mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000002 mmc0: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 mmc0: sdhci: Int enab: 0x00000000 | Sig enab: 0x00000000 mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc0: sdhci: Caps: 0x742dc8b2 | Caps_1: 0x00008007 mmc0: sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc0: sdhci: Host ctl2: 0x00000000 mmc0: sdhci: ============================================ Add support for the additional calibration clocks to allow these platforms to be configured appropriately. Cc: Venkat Gopalakrishnan Cc: Ritesh Harjani Signed-off-by: Bjorn Andersson --- Changes since v1: - Add new clocks to DT binding Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 2 ++ drivers/mmc/host/sdhci-msm.c | 12 +++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 0576264eab5e..5d9c3cd1bdaa 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -18,6 +18,8 @@ Required properties: "core" - SDC MMC clock (MCLK) (required) "bus" - SDCC bus voter clock (optional) "xo" - TCXO clock (optional) + "cal" - reference clock for RCLK delay calibration (optional) + "sleep" - sleep clock for RCLK delay calibration (optional) Example: diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index b9ca1b1ef9a8..ea330e8169dc 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -129,7 +129,7 @@ struct sdhci_msm_host { int pwr_irq; /* power irq */ struct clk *bus_clk; /* SDHC bus voter clock */ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ - struct clk_bulk_data bulk_clks[2]; /* core, iface clocks */ + struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */ unsigned long clk_rate; struct mmc_host *mmc; bool use_14lpp_dll_reset; @@ -1183,6 +1183,16 @@ static int sdhci_msm_probe(struct platform_device *pdev) if (ret) dev_warn(&pdev->dev, "core clock boost failed\n"); + clk = devm_clk_get(&pdev->dev, "cal"); + if (IS_ERR(clk)) + clk = NULL; + msm_host->bulk_clks[2].clk = clk; + + clk = devm_clk_get(&pdev->dev, "sleep"); + if (IS_ERR(clk)) + clk = NULL; + msm_host->bulk_clks[3].clk = clk; + ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), msm_host->bulk_clks); if (ret)