From patchwork Wed May 27 16:49:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 218419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C210C433DF for ; Wed, 27 May 2020 16:49:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B2992071A for ; Wed, 27 May 2020 16:49:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="kaN1n5mm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730954AbgE0Qt5 (ORCPT ); Wed, 27 May 2020 12:49:57 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:47272 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730674AbgE0Qt4 (ORCPT ); Wed, 27 May 2020 12:49:56 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04RGnpR4104912; Wed, 27 May 2020 11:49:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590598191; bh=KFHYeJgmNCFuSOWGbpbyVsKGCw+e9zxhMfRv6681lZg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kaN1n5mmLnd4knfZhyLwUOwXpX2tPAF4mVZasKNrPSzO1/nU/8USIAIDOuGYW2+xF x4jbE8DqYpdC7UpuVwrx0/9igSDCnT0bd9OkYxCRa8DgG0HkIu3bZn8q1lYEfeI3kv Sz4wLaeeYuojFCJEWgqgUPmMgesdC8q1RAolu4mU= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 04RGnpwn058215 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 27 May 2020 11:49:51 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 27 May 2020 11:49:50 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 27 May 2020 11:49:50 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04RGnoD9085684; Wed, 27 May 2020 11:49:50 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v4 2/4] net: phy: Add a helper to return the index for of the internal delay Date: Wed, 27 May 2020 11:49:32 -0500 Message-ID: <20200527164934.28651-3-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200527164934.28651-1-dmurphy@ti.com> References: <20200527164934.28651-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add a helper function that will return the index in the array for the passed in internal delay value. The helper requires the array, size and delay value. The helper will then return the index for the exact match or return the index for the index to the closest smaller value. Signed-off-by: Dan Murphy --- drivers/net/phy/phy_device.c | 51 ++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 6b30d205642f..3f3bd0fea53c 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -2661,6 +2661,57 @@ void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause) } EXPORT_SYMBOL(phy_get_pause); +/** + * phy_get_delay_index - returns the index of the internal delay + * @phydev: phy_device struct + * @delay_values: array of delays the PHY supports + * @size: the size of the delay array + * @int_delay: the internal delay to be looked up + * + * Returns the index within the array of internal delay passed in. + * The array must be in ascending order. + * Return errno if the delay is invalid or cannot be found. + */ +s32 phy_get_delay_index(struct phy_device *phydev, const int *delay_values, + int size, int int_delay) +{ + int i; + + if (int_delay < 0) + return -EINVAL; + + if (size <= 0) + return -EINVAL; + + if (int_delay < delay_values[0] || int_delay > delay_values[size - 1]) { + phydev_err(phydev, "Delay %d is out of range\n", int_delay); + return -EINVAL; + } + + if (int_delay == delay_values[0]) + return 0; + + for (i = 1; i < size; i++) { + if (int_delay == delay_values[i]) + return i; + + /* Find an approximate index by looking up the table */ + if (int_delay > delay_values[i - 1] && + int_delay < delay_values[i]) { + if (int_delay - delay_values[i - 1] < + delay_values[i] - int_delay) + return i - 1; + else + return i; + } + } + + phydev_err(phydev, "error finding internal delay index for %d\n", + int_delay); + return -EINVAL; +} +EXPORT_SYMBOL(phy_get_delay_index); + static bool phy_drv_supports_irq(struct phy_driver *phydrv) { return phydrv->config_intr && phydrv->ack_interrupt; diff --git a/include/linux/phy.h b/include/linux/phy.h index 2bcdf19ed3b4..2058ed11f7dd 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1408,6 +1408,8 @@ void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); bool phy_validate_pause(struct phy_device *phydev, struct ethtool_pauseparam *pp); void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); +int phy_get_delay_index(struct phy_device *phydev, const int *delay_values, + int size, int delay); void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, bool *tx_pause, bool *rx_pause); From patchwork Wed May 27 16:49:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 218418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60AEEC433E1 for ; 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Wed, 27 May 2020 11:49:56 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v4 4/4] net: dp83869: Add RGMII internal delay configuration Date: Wed, 27 May 2020 11:49:34 -0500 Message-ID: <20200527164934.28651-5-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200527164934.28651-1-dmurphy@ti.com> References: <20200527164934.28651-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add RGMII internal delay configuration for Rx and Tx. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83869.c | 82 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index cfb22a21a2e6..ba1e3d599888 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -64,6 +64,10 @@ #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) +/* RGMIIDCTL */ +#define DP83869_RGMII_CLK_DELAY_SHIFT 4 +#define DP83869_CLK_DELAY_DEF 7 + /* STRAP_STS1 bits */ #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) #define DP83869_STRAP_STS1_RESERVED BIT(11) @@ -78,9 +82,6 @@ #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) #define DP83869_PHYCR_RESERVED_MASK BIT(11) -/* RGMIIDCTL bits */ -#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 - /* IO_MUX_CFG bits */ #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f @@ -99,6 +100,10 @@ #define DP83869_OP_MODE_MII BIT(5) #define DP83869_SGMII_RGMII_BRIDGE BIT(6) +static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, + 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000}; + enum { DP83869_PORT_MIRRORING_KEEP, DP83869_PORT_MIRRORING_EN, @@ -108,6 +113,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + s32 rx_id_delay; + s32 tx_id_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -232,6 +239,22 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + ret = of_property_read_u32(of_node, "rx-internal-delay-ps", + &dp83869->rx_id_delay); + if (ret) { + dp83869->rx_id_delay = + dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; + ret = 0; + } + + ret = of_property_read_u32(of_node, "tx-internal-delay-ps", + &dp83869->tx_id_delay); + if (ret) { + dp83869->tx_id_delay = + dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; + ret = 0; + } + return ret; } #else @@ -367,10 +390,35 @@ static int dp83869_configure_mode(struct phy_device *phydev, return ret; } +static int dp83869_get_delay(struct phy_device *phydev) +{ + struct dp83869_private *dp83869 = phydev->priv; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); + int tx_delay; + int rx_delay; + + tx_delay = phy_get_delay_index(phydev, &dp83869_internal_delay[0], + delay_size, dp83869->tx_id_delay); + if (tx_delay < 0) { + phydev_err(phydev, "Tx internal delay is invalid\n"); + return tx_delay; + } + + rx_delay = phy_get_delay_index(phydev, &dp83869_internal_delay[0], + delay_size, dp83869->rx_id_delay); + if (rx_delay < 0) { + phydev_err(phydev, "Rx internal delay is invalid\n"); + return rx_delay; + } + + return rx_delay | tx_delay << DP83869_RGMII_CLK_DELAY_SHIFT; +} + static int dp83869_config_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; int ret, val; + int delay; ret = dp83869_configure_mode(phydev, dp83869); if (ret) @@ -394,6 +442,34 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + delay = dp83869_get_delay(phydev); + if (delay < 0) + return delay; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + delay); + if (ret) + return ret; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, + val); + } + return ret; }