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Fri, 15 Sep 2017 10:42:09 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , stable@vger.kernel.org Subject: [PATCH v2] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Date: Fri, 15 Sep 2017 11:41:53 +0200 Message-id: <1505468516-3324-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNIsWRmVeSWpSXmKPExsWy7djP87pFC3ZHGvw4zmWxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWiwUbHzE6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZJ+9oF3ziq7h6vIulgXEvTxcjJ4eEgInEnykfWCFsMYkL99azdTFycQgJ LGOUOLpsKzOE85lRouffGRaYjhlv5iFUvd/ymwXCaWCSuHr8GSNIFZuAoUTX2y42EFtEwEHi 86fXjCBFzAJ/GSX+7V/HDpIQFkiUeHroKpjNIqAq0bKhF+wQXgF3id2TTkOtk5M4eWwy1IFv WSX2/U6BsF0kJv06CBUXlnh1fAs7hC0j0dlxkAnC7meUaGrVhrBnMEqce8sLYVtLHD5+EayX WYBPYtK26UB/cgDFeSU62oQgSjwkPi8/C3WCo8TEtZfBbCGBWImPx54zTmCUWsDIsIpRJLW0 ODc9tdhQrzgxt7g0L10vOT93EyMwCk//O/5+B+PT5pBDjAIcjEo8vDdW7ooUYk0sK67MPcQo wcGsJMJ7ZO7uSCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8tlFtkUIC6YklqdmpqQWpRTBZJg5O qQZGl60BGyTKRdhfMF7wut9p6z3pzqoFccv85HpMuC79kebn2P7DqUNPrn+WcN7DNflyeXe+ N9s/cWy/8GdKxP8iNqXwxG2Ncr32s/czCHFFXvtwz84+ReBJ/pLvb85zTljVLuHlVBFvdf2G RYtb21E1k8nMjKls7w4u2bU5zcV83lc/jViVHyVKLMUZiYZazEXFiQA2SbVHvgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGJMWRmVeSWpSXmKPExsVy+t/xa7qFC3ZHGjzfq2axccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWiwUbHzE6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZJ+9oF3ziq7h6vIulgXEvTxcjJ4eEgInEjDfz2CBsMYkL99YD2VwcQgJL GCVOHNzPBOE0MUm8nXENrIpNwFCi620XmC0i4CDx+dNrRpAiZoG/jBJ/7vWBJYQFEiWeHrrK DmKzCKhKtGzoZQWxeQXcJXZPOs0CsU5O4uSxyawTGLkXMDKsYhRJLS3OTc8tNtQrTswtLs1L 10vOz93ECAyNbcd+bt7BeGlj8CFGAQ5GJR5egQm7IoVYE8uKK3MPMUpwMCuJ8B6ZuztSiDcl sbIqtSg/vqg0J7X4EKM0B4uSOG/vntWRQgLpiSWp2ampBalFMFkmDk6pBsbkryG1l/6ceHzu 70WH591x7rwTXs/8kfxmeX+htFLB7HOSHpPDHtjnMTDmyTCws2ZXXF/odGrdJTVW5WpNT0fG a9/DrPlXxfOe4JC2iWzgm71WdxbH9CrFtdvYJxk1Fpj+Xt9gH6WdfCrj/a3FOybuZrt+eLPq ef6K1Zq+n050yR+/YF3uHqzEUpyRaKjFXFScCACSSujPCQIAAA== X-CMS-MailID: 20170915094209eucas1p1c959442cce50aea9553e4b73a36ab8a0 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20170915094209eucas1p1c959442cce50aea9553e4b73a36ab8a0 X-RootMTR: 20170915094209eucas1p1c959442cce50aea9553e4b73a36ab8a0 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable. Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") CC: stable@vger.kernel.org # v4.13 Signed-off-by: Marek Szyprowski --- Changelog: v2: - wait until PLL is properly locked --- drivers/clk/samsung/clk-exynos4.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Acked-by: Sylwester Nawrocki diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..d8d3cb67b402 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -294,6 +294,18 @@ enum exynos4_plls { #define PLL_ENABLED (1 << 31) #define PLL_LOCKED (1 << 29) +static void exynos4_clk_enable_pll(u32 reg) +{ + u32 pll_con = readl(reg_base + reg); + pll_con |= PLL_ENABLED; + writel(pll_con, reg_base + reg); + + while (!(pll_con & PLL_LOCKED)) { + cpu_relax(); + pll_con = readl(reg_base + reg); + } +} + static void exynos4_clk_wait_for_pll(u32 reg) { u32 pll_con; @@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) samsung_clk_save(reg_base, exynos4_save_pll, ARRAY_SIZE(exynos4_clk_pll_regs)); + exynos4_clk_enable_pll(EPLL_CON0); + exynos4_clk_enable_pll(VPLL_CON0); + if (exynos4_soc == EXYNOS4210) { samsung_clk_save(reg_base, exynos4_save_soc, ARRAY_SIZE(exynos4210_clk_save));