From patchwork Thu Sep 14 17:08:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112583 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1002792qgf; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBtyGcAsiNkKntHpF2ISfTO/PJD5msVbfIMuih+cQN6cxQ6nOuR2XW3sgtLZBVjVJBMr1vQ X-Received: by 10.36.201.196 with SMTP id h187mr1078944itg.42.1505409080145; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409080; cv=none; d=google.com; s=arc-20160816; b=ukLRaVO+8PlkowLIDxW7EAhvb6dbxOAxYwoYE6EI27ppX65pc1v2VFv3DCf+OrQMHL JlhKJ5MpN6cZb+Y30PHeVLnWLAWIeu84eVUtvbCq4U8ZVQVd7cTyB9FFH/Zg/nzpGjiS Fi/AE5tX3nLBgx8/g49HeUquElTqF0+L5QVuaapuB+SL026Ejz14QZa8VTWw8MwOty5Q qKoIvJA18DvVvOK/bJsDdIPUhfewXIqUNzFNzmvw2Cj6BtqQa4gwphuA2mTZqSM80DoC dyUO0cFtqjBax+9S6KSBv4x4K/PNUw1URGItIUs+W4BFR3Noz3o9VnsQ1jkxT+tNlDLJ buWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ce+lvpHHNU9A+uetqB2GLz3wEVC6NCeBS/kzAlY6YKo=; b=k3oLKNJrcbAInPRk0kov4/FA1ioUvf6BkKaj08I8iG4G41jrUw2MtxPOj9lliWmeRz i0rTMoS/qwA/x0RdQU8b9a3rcGhDRttLa0rne5zA4PTnaO6CBptdtmhsMBNJvD4vvW+R HAT8Kz+6x31FaJ7wPiVUmdwTLJoKQxTj1miN1Ro8PkiJUtGswoqQacVW/lBe4J8KTP8R tnGMJvtbtZYgyxcYkA89Zd5titafIe7EN33ea0E7ejQA6rWyAQt8i+r0KnL5bYAJ/jDw xrd8aOcHJt35lZR/LiA9meXz7VOzG5+tWgCNRBh0lRkSK1XsVAHZW++j00YF7roGT1n/ m38Q== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g21si486575itg.121.2017.09.14.10.11.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:20 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdZ-0008DG-1F; Thu, 14 Sep 2017 17:09:13 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdX-0008Bi-GU for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:11 +0000 Received: from [85.158.137.68] by server-14.bemta-3.messagelabs.com id FA/0B-01910-6B7BAB95; Thu, 14 Sep 2017 17:09:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTXfL9l2 RBiffMlss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnTr8xhLfhrWrF42TfmBsanGl2MXBxCApsZ JfYeW8kC4ZxmlFh26TRrFyMnB5uApsSdz5+YQGwRAWmJa58vM4LYzALVEv8XnmQDsYUFQiXeP NnBDGKzCKhK7JlyAqyeV8BSYtK6nSwgtoSAvMSutotgMzkFrCR2/74CVi8EVLPrzlf2CYzcCx gZVjFqFKcWlaUW6RqZ6SUVZaZnlOQmZuboGhoY6+WmFhcnpqfmJCYV6yXn525iBHq4noGBcQd jw16/Q4ySHExKorx7dXdGCvEl5adUZiQWZ8QXleakFh9ilOHgUJLgnb5tV6SQYFFqempFWmYO MNRg0hIcPEoivHkgad7igsTc4sx0iNQpRl2Ojpt3/zAJseTl56VKifPWgRQJgBRllObBjYCF/ SVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrxVIFN4MvNK4Da9AjqCCeiIM6d3gBxRkoiQkm pgrOrzFo+x22NbvkliF5PA9aAms713A1b9eP14vhFfnrXVx7VzQ7TnbJjf+V7+qoeM2scZSYs uPpGuuXw/yynxa/LVsCdxnnM0wkzi71VfaePdfEQ5+PXWer1go0lX+ljmKn35vJll/nMVBeE7 3z/fkDDjzBX9/O3j/ulNsqzvbSri7dU9e6v+K7EUZyQaajEXFScCAGusfOx2AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1505408947!107232161!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48579 invoked from network); 14 Sep 2017 17:09:07 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-16.tower-31.messagelabs.com with SMTP; 14 Sep 2017 17:09:07 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 239BC1435; Thu, 14 Sep 2017 10:09:07 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11B323F483; Thu, 14 Sep 2017 10:09:05 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:55 +0100 Message-Id: <20170914170859.30553-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v3 1/5] xen/arm: traps: Export a bunch of helpers to handle emulation X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" A follow-up patch will move some parts of traps.c in separate files. The will require to use helpers that are currently statically defined. Export the following helpers: - inject_undef64_exception - inject_undef_exception - check_conditional_instr - advance_pc - handle_raz_wi - handle_wo_wi - handle_ro_raz Note that asm-arm/arm32/traps.h is empty but it is to keep parity with the arm64 counterpart. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Cc: volodymyr_babchuk@epam.com Changes in v3: - Replicate comment on top of each prototypes when useful Changes in v2: - Fixup guards - Add newline for clarity --- xen/arch/arm/traps.c | 43 +++++++++++++++++++-------------------- xen/include/asm-arm/arm32/traps.h | 13 ++++++++++++ xen/include/asm-arm/arm64/traps.h | 15 ++++++++++++++ xen/include/asm-arm/traps.h | 39 +++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+), 22 deletions(-) create mode 100644 xen/include/asm-arm/arm32/traps.h create mode 100644 xen/include/asm-arm/arm64/traps.h create mode 100644 xen/include/asm-arm/traps.h diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6f32f700e5..1c334a7b99 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -547,7 +548,7 @@ static vaddr_t exception_handler64(struct cpu_user_regs *regs, vaddr_t offset) } /* Inject an undefined exception into a 64 bit guest */ -static void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) { vaddr_t handler; const union hsr esr = { @@ -620,8 +621,7 @@ static void inject_iabt64_exception(struct cpu_user_regs *regs, #endif -static void inject_undef_exception(struct cpu_user_regs *regs, - const union hsr hsr) +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr) { if ( is_32bit_domain(current->domain) ) inject_undef32_exception(regs); @@ -1714,8 +1714,7 @@ static const unsigned short cc_map[16] = { 0 /* NV */ }; -static int check_conditional_instr(struct cpu_user_regs *regs, - const union hsr hsr) +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long cpsr, cpsr_cond; int cond; @@ -1777,7 +1776,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, return 1; } -static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long itbits, cond, cpsr = regs->cpsr; @@ -1818,11 +1817,11 @@ static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) } /* Read as zero and write ignore */ -static void handle_raz_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_raz_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1836,12 +1835,12 @@ static void handle_raz_wi(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -/* Write only as write ignore */ -static void handle_wo_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1856,11 +1855,11 @@ static void handle_wo_wi(struct cpu_user_regs *regs, } /* Read only as read as zero */ -static void handle_ro_raz(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_ro_raz(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); diff --git a/xen/include/asm-arm/arm32/traps.h b/xen/include/asm-arm/arm32/traps.h new file mode 100644 index 0000000000..e3c4a8b473 --- /dev/null +++ b/xen/include/asm-arm/arm32/traps.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARM32_TRAPS__ +#define __ASM_ARM32_TRAPS__ + +#endif /* __ASM_ARM32_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h new file mode 100644 index 0000000000..e5e5a4a036 --- /dev/null +++ b/xen/include/asm-arm/arm64/traps.h @@ -0,0 +1,15 @@ +#ifndef __ASM_ARM64_TRAPS__ +#define __ASM_ARM64_TRAPS__ + +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); + +#endif /* __ASM_ARM64_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h new file mode 100644 index 0000000000..22ad070679 --- /dev/null +++ b/xen/include/asm-arm/traps.h @@ -0,0 +1,39 @@ +#ifndef __ASM_ARM_TRAPS__ +#define __ASM_ARM_TRAPS__ + +#include + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#endif + +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); + +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); + +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr); + +/* read as zero and write ignore */ +void handle_raz_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +/* read only as read as zero */ +void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +#endif /* __ASM_ARM_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + From patchwork Thu Sep 14 17:08:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112586 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1002984qgf; Thu, 14 Sep 2017 10:11:31 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCZrfvsqkx/OqALbngPwtS8du1oeDnNTjr5y4AZtYgJEB3cT2bVV6+RNMveUnqVxS4aCc8X X-Received: by 10.36.121.202 with SMTP id z193mr1174539itc.110.1505409091146; Thu, 14 Sep 2017 10:11:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409091; cv=none; d=google.com; s=arc-20160816; b=Gat3vY1pvOKtnW5r/1VwxkZuy9ZSykjF/fnKTNUWepBrZ3q2JARuH8g2IsSC9/ZMKm j0mPjPyVURBVnXgckN2MD3tRIN9vewkzNcC0ZA1xrnU00FbiLMkkSYbM0e2BAJOJKwyD 1O/FDspRc8bR/bEXy4pNVoPzm5qt5eMqH0h62rVR/CihGa3n9TDTt0+/IqwAi3WjBlUG JVpkyundEGKE/Yvcd5zqlxEjZKbQvAS1s9doU/3SPPbe7I4t2OQuXpQ7ajvkgSw0dUDV rzu7mVwqwNYBnpPS1ArRiZvS1rWqvQG8Q+lelHihVuPzgBAclLuGG5vflrn4Pw2ohSt7 B6dw== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id k15si12890845ioo.124.2017.09.14.10.11.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:31 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdX-0008C0-Lz; Thu, 14 Sep 2017 17:09:11 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdW-0008Be-V8 for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:11 +0000 Received: from [85.158.139.211] by server-13.bemta-5.messagelabs.com id 30/AF-01754-6B7BAB95; Thu, 14 Sep 2017 17:09:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRWlGSWpSXmKPExsVysyfVTXfr9l2 RBvvbFSyWfFzM4sDocXT3b6YAxijWzLyk/IoE1oxr+66xF6wqrnjcPZmtgbEvuIuRi0NIYDOj xMH/S9kgnNOMEldvrWDtYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWSBO4v2iRhYQW1jAU2Lr7 3/MXYwcHCwCqhJXfpaAhHkFLCUe/lgLVi4hIC+xq+0i2EhOASuJ3b+vMIPYQkA1u+58ZZ/AyL 2AkWEVo3pxalFZapGuqV5SUWZ6RkluYmaOrqGBqV5uanFxYnpqTmJSsV5yfu4mRqB3GYBgB+O XfudDjJIcTEqivHt1d0YK8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuCN2bYrUkiwKDU9tSItMwcY ZjBpCQ4eJRHePJA0b3FBYm5xZjpE6hSjMcexTZf/MHF03Lz7h0mIJS8/L1VKnPfHVqBSAZDSj NI8uEGw8L/EKCslzMsIdJoQT0FqUW5mCar8K0ZxDkYlYd4qkIU8mXklcPteAZ3CBHTKmdM7QE 4pSURISTUwegRNW/Erye8E64UlnMJLtd1Wf9QJ6YzmTPi6cbnI28tBtrlfqxX4yj13vTu9bcW 6Pzeu5u3XfpM9c1J4FFuz/Pm8r14v65svP33TsPuiXegukV+zBV/z+Bze8fJzELcwb9PxpJVW skkP90uoePbeWMIfHNr+amJH4qHJonX+iwJLy7PPaLiwKLEUZyQaajEXFScCAL5cABF6AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1505408948!97576844!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6930 invoked from network); 14 Sep 2017 17:09:09 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-206.messagelabs.com with SMTP; 14 Sep 2017 17:09:09 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7136C16A0; Thu, 14 Sep 2017 10:09:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F7C53F483; Thu, 14 Sep 2017 10:09:07 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:56 +0100 Message-Id: <20170914170859.30553-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 2/5] xen/arm: Move sysreg emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The sysreg emulation is 64-bit specific and surrounded by #ifdef. Move them in a separate file arm/arm64/vsysreg.c to shrink down a bit traps.c No functional change. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/vsysreg.c | 229 ++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 198 -------------------------------- xen/include/asm-arm/arm64/traps.h | 3 + 4 files changed, 233 insertions(+), 198 deletions(-) create mode 100644 xen/arch/arm/arm64/vsysreg.c diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 149b6b3901..718fe44455 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_LIVEPATCH) += livepatch.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o +obj-y += vsysreg.o diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c new file mode 100644 index 0000000000..c57ac12503 --- /dev/null +++ b/xen/arch/arm/arm64/vsysreg.c @@ -0,0 +1,229 @@ +/* + * xen/arch/arm/arm64/sysreg.c + * + * Emulate system registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr) +{ + int regidx = hsr.sysreg.reg; + struct vcpu *v = current; + + switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) + { + /* + * HCR_EL2.TACR + * + * ARMv8 (DDI 0487A.d): D7.2.1 + */ + case HSR_SYSREG_ACTLR_EL1: + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( hsr.sysreg.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TDRA + * + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + */ + case HSR_SYSREG_MDRAR_EL1: + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDOSA + * + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * OSLSR_EL1 + * DBGPRCR_EL1 + */ + case HSR_SYSREG_OSLAR_EL1: + return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_OSDLR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * MDCCINT_EL1 + * DBGDTR_EL0 + * DBGDTRRX_EL0 + * DBGDTRTX_EL0 + * OSDTRRX_EL1 + * OSDTRTX_EL1 + * OSECCR_EL1 + * DBGCLAIMSET_EL1 + * DBGCLAIMCLR_EL1 + * DBGAUTHSTATUS_EL1 + */ + case HSR_SYSREG_MDSCR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_MDCCSR_EL0: + /* + * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that + * register as RAZ/WI above. So RO at both EL0 and EL1. + */ + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): + HSR_SYSREG_DBG_CASES(DBGBCR): + HSR_SYSREG_DBG_CASES(DBGWVR): + HSR_SYSREG_DBG_CASES(DBGWCR): + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TPM + * + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR_EL0 + * PMEVTYPER_EL0 + * PMCCFILTR_EL0 + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + case HSR_SYSREG_PMINTENSET_EL1: + case HSR_SYSREG_PMINTENCLR_EL1: + /* + * Accessible from EL1 only, but if EL0 trap happens handle as + * undef. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMUSERENR_EL0: + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMCR_EL0: + case HSR_SYSREG_PMCNTENSET_EL0: + case HSR_SYSREG_PMCNTENCLR_EL0: + case HSR_SYSREG_PMOVSCLR_EL0: + case HSR_SYSREG_PMSWINC_EL0: + case HSR_SYSREG_PMSELR_EL0: + case HSR_SYSREG_PMCEID0_EL0: + case HSR_SYSREG_PMCEID1_EL0: + case HSR_SYSREG_PMCCNTR_EL0: + case HSR_SYSREG_PMXEVTYPER_EL0: + case HSR_SYSREG_PMXEVCNTR_EL0: + case HSR_SYSREG_PMOVSSET_EL0: + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * !CNTHCTL_EL2.EL1PCEN + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_SYSREG_CNTP_CTL_EL0: + case HSR_SYSREG_CNTP_TVAL_EL0: + case HSR_SYSREG_CNTP_CVAL_EL0: + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_SYSREG_ICC_SGI1R_EL1: + case HSR_SYSREG_ICC_ASGI1R_EL1: + case HSR_SYSREG_ICC_SGI0R_EL1: + + if ( !vgic_emulate(regs, hsr) ) + return inject_undef64_exception(regs, hsr.len); + break; + + /* + * ICC_SRE_EL2.Enable = 0 + * + * GIC Architecture Specification (IHI 0069C): Section 8.1.9 + */ + case HSR_SYSREG_ICC_SRE_EL1: + /* + * Trapped when the guest is using GICv2 whilst the platform + * interrupt controller is GICv3. In this case, the register + * should be emulate as RAZ/WI to tell the guest to use the GIC + * memory mapped interface (i.e GICv2 compatibility). + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - Reserved control space for IMPLEMENTATION DEFINED functionality. + * + * CPTR_EL2.TTA + * + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_sysreg sysreg = hsr.sysreg; + + gdprintk(XENLOG_ERR, + "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", + sysreg.read ? "mrs" : "msr", + sysreg.op0, sysreg.op1, + sysreg.crn, sysreg.crm, + sysreg.op2, + sysreg.read ? "=>" : "<=", + sysreg.reg, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", + hsr.bits & HSR_SYSREG_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + + regs->pc += 4; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1c334a7b99..f00aa48892 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2295,204 +2295,6 @@ static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) inject_undef_exception(regs, hsr); } -#ifdef CONFIG_ARM_64 -static void do_sysreg(struct cpu_user_regs *regs, - const union hsr hsr) -{ - int regidx = hsr.sysreg.reg; - struct vcpu *v = current; - - switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) - { - /* - * HCR_EL2.TACR - * - * ARMv8 (DDI 0487A.d): D7.2.1 - */ - case HSR_SYSREG_ACTLR_EL1: - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( hsr.sysreg.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TDRA - * - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - */ - case HSR_SYSREG_MDRAR_EL1: - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDOSA - * - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * OSLSR_EL1 - * DBGPRCR_EL1 - */ - case HSR_SYSREG_OSLAR_EL1: - return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_OSDLR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 - * OSDTRRX_EL1 - * OSDTRTX_EL1 - * OSECCR_EL1 - * DBGCLAIMSET_EL1 - * DBGCLAIMCLR_EL1 - * DBGAUTHSTATUS_EL1 - */ - case HSR_SYSREG_MDSCR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_MDCCSR_EL0: - /* - * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that - * register as RAZ/WI above. So RO at both EL0 and EL1. - */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - HSR_SYSREG_DBG_CASES(DBGBVR): - HSR_SYSREG_DBG_CASES(DBGBCR): - HSR_SYSREG_DBG_CASES(DBGWVR): - HSR_SYSREG_DBG_CASES(DBGWCR): - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TPM - * - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR_EL0 - * PMEVTYPER_EL0 - * PMCCFILTR_EL0 - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - case HSR_SYSREG_PMINTENSET_EL1: - case HSR_SYSREG_PMINTENCLR_EL1: - /* - * Accessible from EL1 only, but if EL0 trap happens handle as - * undef. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMUSERENR_EL0: - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMCR_EL0: - case HSR_SYSREG_PMCNTENSET_EL0: - case HSR_SYSREG_PMCNTENCLR_EL0: - case HSR_SYSREG_PMOVSCLR_EL0: - case HSR_SYSREG_PMSWINC_EL0: - case HSR_SYSREG_PMSELR_EL0: - case HSR_SYSREG_PMCEID0_EL0: - case HSR_SYSREG_PMCEID1_EL0: - case HSR_SYSREG_PMCCNTR_EL0: - case HSR_SYSREG_PMXEVTYPER_EL0: - case HSR_SYSREG_PMXEVCNTR_EL0: - case HSR_SYSREG_PMOVSSET_EL0: - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * !CNTHCTL_EL2.EL1PCEN - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_SYSREG_CNTP_CTL_EL0: - case HSR_SYSREG_CNTP_TVAL_EL0: - case HSR_SYSREG_CNTP_CVAL_EL0: - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_SYSREG_ICC_SGI1R_EL1: - case HSR_SYSREG_ICC_ASGI1R_EL1: - case HSR_SYSREG_ICC_SGI0R_EL1: - - if ( !vgic_emulate(regs, hsr) ) - return inject_undef64_exception(regs, hsr.len); - break; - - /* - * ICC_SRE_EL2.Enable = 0 - * - * GIC Architecture Specification (IHI 0069C): Section 8.1.9 - */ - case HSR_SYSREG_ICC_SRE_EL1: - /* - * Trapped when the guest is using GICv2 whilst the platform - * interrupt controller is GICv3. In this case, the register - * should be emulate as RAZ/WI to tell the guest to use the GIC - * memory mapped interface (i.e GICv2 compatibility). - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - Reserved control space for IMPLEMENTATION DEFINED functionality. - * - * CPTR_EL2.TTA - * - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_sysreg sysreg = hsr.sysreg; - - gdprintk(XENLOG_ERR, - "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", - sysreg.read ? "mrs" : "msr", - sysreg.op0, sysreg.op1, - sysreg.crn, sysreg.crm, - sysreg.op2, - sysreg.read ? "=>" : "<=", - sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", - hsr.bits & HSR_SYSREG_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - - regs->pc += 4; -} -#endif - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h index e5e5a4a036..2379b578cb 100644 --- a/xen/include/asm-arm/arm64/traps.h +++ b/xen/include/asm-arm/arm64/traps.h @@ -3,6 +3,9 @@ void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr); + #endif /* __ASM_ARM64_TRAPS__ */ /* * Local variables: From patchwork Thu Sep 14 17:08:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112587 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1003089qgf; Thu, 14 Sep 2017 10:11:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBqxNshWeLsJcZbB9IxEvO7uPhqZGyvmrcYa6BIeqAtrC/WjDqnO2/Ym/jP3VTUnxmRfVrt X-Received: by 10.107.57.70 with SMTP id g67mr4359848ioa.224.1505409097889; Thu, 14 Sep 2017 10:11:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409097; cv=none; d=google.com; s=arc-20160816; b=noFMU4dpB4gC7hoN1bOu9AUIQO70wbxrJ30iW3u/VNNSAPhEhiOzMaiBOLEW0wnteU CwpBtIX+FcqRllOfKbPDjoSXCfX4FKWF/A4digXgc+1jRaSLPKvGa/CtQfP+vkjeYpHJ lfyy+GItgYYE+JaH99WMnd6e9KBFmP4MBHRYwURgevV65VbdZmZHM7OCBXeaxAfCiGM5 AXvG+Lkl563vVe1m5lwEP0iGZUO16qjOn/4p2xTPU1CN6hIg7g/3PaQLST0E6xF6Kmqk 1JVuiFVofQ3/wjzyIP8LOfP2qNh7II7l2dqMVUw1zjU6xs8Hmo7p/VGy+mztzKNwZzi+ YVYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=BgEahah9+A3/nFxx5vLGn7bleva39MZrWvU/ITtpWvg=; b=Mzz0x/Z/gk0NWJCgvxC/K/ekTWqDpaum46fk0tPj3El6luuvSNCd3W+93LuWV1jmdZ l+KoknSbUKHpeIurXlTrlKQkFBkAtOvxvQnfdU3DaiXYvW9H+BY9m+JG2S8/CFbEGRn1 SmZzpAPwj/lp2gqi8lph8rnOr+r3rRaZVRUZ+obWqpq1/SQTL9UEbYTJeA0bpugytzNX okpXqZYvziBgYE2MmY2WWF4eDxZQC3xf/k2tMeEJg1Bimm6C5iEtEUq5VEd+uRyOUk7h gfiQY/It2N+gNqnTlAcaQ9LbKwNRxSEK/SpzGqpVOMenGV6SBWl+eFLGTweaOGVYKTo+ jtuA== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l7si5639231ioe.326.2017.09.14.10.11.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:37 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXda-0008Ei-Ft; Thu, 14 Sep 2017 17:09:14 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdY-0008Co-Mh for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:12 +0000 Received: from [193.109.254.147] by server-11.bemta-6.messagelabs.com id E0/11-03616-8B7BAB95; Thu, 14 Sep 2017 17:09:12 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRWlGSWpSXmKPExsVysyfVTXfb9l2 RBt0nzS2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oyd17ezFZy5wVjxd9lXlgbGrlmMXYxcHEIC mxklfk3ZzgbhnGaUmPrmD3sXIycHm4CmxJ3Pn5hAbBEBaYlrny8zgtjMAnES7xc1soDYwgL+E vtnvQerYRFQlbjzZQVYnFfAUuL9tV+sILaEgLzErraLYDangJXE7t9XmEFsIaCaXXe+sk9g5F 7AyLCKUb04tagstUjXXC+pKDM9oyQ3MTNH19DATC83tbg4MT01JzGpWC85P3cTI9DHDECwg3H mZf9DjJIcTEqivHt1d0YK8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuCN2bYrUkiwKDU9tSItMwcY bDBpCQ4eJRHePJA0b3FBYm5xZjpE6hSjLkfHzbt/mIRY8vLzUqXEeX9sBSoSACnKKM2DGwEL/ EuMslLCvIxARwnxFKQW5WaWoMq/YhTnYFQS5rUBWcWTmVcCt+kV0BFMQEecOb0D5IiSRISUVA Oj5+zqyk/W3V+vVlddE67afmPTTP8bWZ4SltuDOiVyFHrfWBjWB7ZvcLdoVWIrCKnXd62Z08Q y+ZrHxtadRVqKF3XzmU+n7nw1p7Ts0/78txtOX21NPV2tf0x8lsCXF5a3z/2bJGpZ69pnUKgz afqMCZExz1+n+7y4u6qY7eylnJ6Y1rQt2a+UWIozEg21mIuKEwF2CSPhdwIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1505408950!107286816!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26514 invoked from network); 14 Sep 2017 17:09:10 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-27.messagelabs.com with SMTP; 14 Sep 2017 17:09:10 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF07016A3; Thu, 14 Sep 2017 10:09:09 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD1473F483; Thu, 14 Sep 2017 10:09:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:57 +0100 Message-Id: <20170914170859.30553-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 3/5] xen/arm: Move co-processor emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The co-processor emulation is quite big and pretty much standalone. Move it in a separate file to shrink down the size of traps.c. At the same time remove unused cpregs.h. No functional change. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by --- xen/arch/arm/Makefile | 1 + xen/arch/arm/traps.c | 421 ----------------------------------------- xen/arch/arm/vcpreg.c | 451 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/traps.h | 8 + 4 files changed, 460 insertions(+), 421 deletions(-) create mode 100644 xen/arch/arm/vcpreg.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 282d2c2949..17bff98033 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -45,6 +45,7 @@ obj-y += smpboot.o obj-y += sysctl.o obj-y += time.o obj-y += traps.o +obj-y += vcpreg.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index f00aa48892..5e6bc3173f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -38,7 +38,6 @@ #include #include -#include #include #include #include @@ -1875,426 +1874,6 @@ void handle_ro_raz(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -static void do_cp15_32(struct cpu_user_regs *regs, - const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct vcpu *v = current; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG32(CNTP_CTL): - case HSR_CPREG32(CNTP_TVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.TACR / HCR.TAC - * - * ARMv7 (DDI 0406C.b): B1.14.6 - * ARMv8 (DDI 0487A.d): G6.2.1 - */ - case HSR_CPREG32(ACTLR): - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( cp32.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TPM - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR - * PMEVTYPER - * PMCCFILTR - * - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - /* We could trap ID_DFR0 and tell the guest we don't support - * performance monitoring, but Linux doesn't check the ID_DFR0. - * Therefore it will read PMCR. - * - * We tell the guest we have 0 counters. Unfortunately we must - * always support PMCCNTR (the cyle counter): we just RAZ/WI for all - * PM register, which doesn't crash the kernel at least - */ - case HSR_CPREG32(PMUSERENR): - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMINTENSET): - case HSR_CPREG32(PMINTENCLR): - /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMCR): - case HSR_CPREG32(PMCNTENSET): - case HSR_CPREG32(PMCNTENCLR): - case HSR_CPREG32(PMOVSR): - case HSR_CPREG32(PMSWINC): - case HSR_CPREG32(PMSELR): - case HSR_CPREG32(PMCEID0): - case HSR_CPREG32(PMCEID1): - case HSR_CPREG32(PMCCNTR): - case HSR_CPREG32(PMXEVTYPER): - case HSR_CPREG32(PMXEVCNTR): - case HSR_CPREG32(PMOVSSET): - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv7 (DDI 0406C.b): B1.14.3 - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} - * (Cache and TCM lockdown registers) - * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} - * (VMSA CP15 c10 registers) - * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} - * (VMSA CP15 c11 registers) - * - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - advance_pc(regs, hsr); -} - -static void do_cp15_64(struct cpu_user_regs *regs, - const union hsr hsr) -{ - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP64_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG64(CNTP_CVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_CPREG64(ICC_SGI1R): - case HSR_CPREG64(ICC_ASGI1R): - case HSR_CPREG64(ICC_SGI0R): - if ( !vgic_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_cp64 cp64 = hsr.cp64; - - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - advance_pc(regs, hsr); -} - -static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct domain *d = current->domain; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGOSLSR - * DBGPRCR - */ - case HSR_CPREG32(DBGOSLAR): - return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(DBGOSDLR): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint - * DBGWFAR - * DBGDTRTXext - * DBGDTRRXext, - * DBGBXVR - * DBGCLAIMSET - * DBGCLAIMCLR - * DBGAUTHSTATUS - * DBGDEVID - * DBGDEVID1 - * DBGDEVID2 - * DBGOSECCR - */ - case HSR_CPREG32(DBGDIDR): - { - uint32_t val; - - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - if ( !cp32.read ) - return inject_undef_exception(regs, hsr); - - /* Implement the minimum requirements: - * - Number of watchpoints: 1 - * - Number of breakpoints: 2 - * - Version: ARMv7 v7.1 - * - Variant and Revision bits match MDIR - */ - val = (1 << 24) | (5 << 16); - val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); - set_user_reg(regs, regidx, val); - - break; - } - - case HSR_CPREG32(DBGDSCRINT): - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGDSCREXT): - /* - * Implement debug status and control register as RAZ/WI. - * The OS won't use Hardware debug if MDBGen not set. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGVCR): - case HSR_CPREG32(DBGBVR0): - case HSR_CPREG32(DBGBCR0): - case HSR_CPREG32(DBGWVR0): - case HSR_CPREG32(DBGWCR0): - case HSR_CPREG32(DBGBVR1): - case HSR_CPREG32(DBGBCR1): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (32-bit accesses) - * DBGDSAR (32-bit accesses) - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - - advance_pc(regs, hsr); -} - -static void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (64-bit accesses) - * DBGDSAR (64-bit accesses) - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); -} - -static void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) -{ - struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - - inject_undef_exception(regs, hsr); -} - -static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp cp = hsr.cp; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - ASSERT(!cp.tas); /* We don't trap SIMD instruction */ - gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); - inject_undef_exception(regs, hsr); -} - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c new file mode 100644 index 0000000000..f3b08403fb --- /dev/null +++ b/xen/arch/arm/vcpreg.c @@ -0,0 +1,451 @@ +/* + * xen/arch/arm/arm64/vcpreg.c + * + * Emulate co-processor registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct vcpu *v = current; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG32(CNTP_CTL): + case HSR_CPREG32(CNTP_TVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.TACR / HCR.TAC + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487A.d): G6.2.1 + */ + case HSR_CPREG32(ACTLR): + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( cp32.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TPM + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR + * PMEVTYPER + * PMCCFILTR + * + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + /* We could trap ID_DFR0 and tell the guest we don't support + * performance monitoring, but Linux doesn't check the ID_DFR0. + * Therefore it will read PMCR. + * + * We tell the guest we have 0 counters. Unfortunately we must + * always support PMCCNTR (the cyle counter): we just RAZ/WI for all + * PM register, which doesn't crash the kernel at least + */ + case HSR_CPREG32(PMUSERENR): + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMINTENSET): + case HSR_CPREG32(PMINTENCLR): + /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMCR): + case HSR_CPREG32(PMCNTENSET): + case HSR_CPREG32(PMCNTENCLR): + case HSR_CPREG32(PMOVSR): + case HSR_CPREG32(PMSWINC): + case HSR_CPREG32(PMSELR): + case HSR_CPREG32(PMCEID0): + case HSR_CPREG32(PMCEID1): + case HSR_CPREG32(PMCCNTR): + case HSR_CPREG32(PMXEVTYPER): + case HSR_CPREG32(PMXEVCNTR): + case HSR_CPREG32(PMOVSSET): + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv7 (DDI 0406C.b): B1.14.3 + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} + * (Cache and TCM lockdown registers) + * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} + * (VMSA CP15 c10 registers) + * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} + * (VMSA CP15 c11 registers) + * + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + advance_pc(regs, hsr); +} + +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP64_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG64(CNTP_CVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_CPREG64(ICC_SGI1R): + case HSR_CPREG64(ICC_ASGI1R): + case HSR_CPREG64(ICC_SGI0R): + if ( !vgic_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_cp64 cp64 = hsr.cp64; + + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + advance_pc(regs, hsr); +} + +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct domain *d = current->domain; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGOSLSR + * DBGPRCR + */ + case HSR_CPREG32(DBGOSLAR): + return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSDLR): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * DBGDCCINT + * DBGDTRRXint + * DBGDTRTXint + * DBGWFAR + * DBGDTRTXext + * DBGDTRRXext, + * DBGBXVR + * DBGCLAIMSET + * DBGCLAIMCLR + * DBGAUTHSTATUS + * DBGDEVID + * DBGDEVID1 + * DBGDEVID2 + * DBGOSECCR + */ + case HSR_CPREG32(DBGDIDR): + { + uint32_t val; + + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + if ( !cp32.read ) + return inject_undef_exception(regs, hsr); + + /* Implement the minimum requirements: + * - Number of watchpoints: 1 + * - Number of breakpoints: 2 + * - Version: ARMv7 v7.1 + * - Variant and Revision bits match MDIR + */ + val = (1 << 24) | (5 << 16); + val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); + set_user_reg(regs, regidx, val); + + break; + } + + case HSR_CPREG32(DBGDSCRINT): + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGDSCREXT): + /* + * Implement debug status and control register as RAZ/WI. + * The OS won't use Hardware debug if MDBGen not set. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGVCR): + case HSR_CPREG32(DBGBVR0): + case HSR_CPREG32(DBGBCR0): + case HSR_CPREG32(DBGWVR0): + case HSR_CPREG32(DBGWCR0): + case HSR_CPREG32(DBGBVR1): + case HSR_CPREG32(DBGBCR1): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (32-bit accesses) + * DBGDSAR (32-bit accesses) + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (64-bit accesses) + * DBGDSAR (64-bit accesses) + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); +} + +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) +{ + struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGDTRTXint + * DBGDTRRXint + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + + inject_undef_exception(regs, hsr); +} + +void do_cp(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp cp = hsr.cp; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + ASSERT(!cp.tas); /* We don't trap SIMD instruction */ + gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); + inject_undef_exception(regs, hsr); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 22ad070679..7508af80c7 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -27,6 +27,14 @@ void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, const union hsr hsr, int min_el); +/* Co-processor registers emulation (see arch/arm/vcpreg.c). */ +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp(struct cpu_user_regs *regs, const union hsr hsr); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: From patchwork Thu Sep 14 17:08:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112584 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1002797qgf; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDo5afH4lYRk15S8w7KFWSg1EIXDj1tC/jGjC/vAOuUr5JDLZaUyeHfoSF4QBjjrKJe9lW7 X-Received: by 10.36.39.199 with SMTP id g190mr1239394ita.73.1505409080819; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409080; cv=none; d=google.com; s=arc-20160816; b=0AVxeO6v2O8bA1f5FtgbmY1kLvUYst4QSlG56d/+2nBpzn1F5/uf94WGtl8kDAtKzb JOWfiybFTRppAIIZcJIkaDsoEP3j7ryKr4S+4ByWFs0LsFZ4lrFQgCl4MeR4Zn2ydIRP 170kDY1mVEXptH3nysTdTuBlvKxFpCnbFIC4HA+7XcQWi6GmSU15L9qb7R7/fewxntQa rIfdfEKxL2KKw0HUnrlJ0Ib1zGMh/SBhXpa4/EqtCQeqnwQRPd++23CBBhai1kp66G8V ro1VjdOTUqn/nWWoxkRdM01sQ/omjmUMkz4YolA16CJ2pYMA+tEbCx7yvHW1A8/n/HAM lrWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZzwxnQ3pN5A7wxONIgHi+8hj4DoR4Fko2qlOPVjlxT0=; b=S7tYeogJbmL6P93oqOXKhIFPln8+WjQ3Zh/iX7dwB5rEm78I+Kb7Io5udvyhQEGH0B GaZjcryo+VWA8NsLyeybYcYmIPxY1JeUVQ3u6KZ0fI3bBODFdONZYpKuUJ25Qghsscqm CqIkaXUWGTzmF9dngKwtvy/t7TG8CqTWYYtBvxP9/lh9MhPX2NUuIVEDRz/tgfRfRhBN ELVqbB7mKuVp/DdWT1UX5ckmYgsXZoKl5VoDcjo+CcOIG7E8eJmPE8Jjc2WmiviXwc/3 4heTdIQWDXNrKZp+kQNicnz5wxT63ePm/KBCwBXyjiPmB+k7IhwB1vg3JzAvRgatm9NM Qg4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n23si15462904iod.141.2017.09.14.10.11.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:20 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXda-0008EA-83; Thu, 14 Sep 2017 17:09:14 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdY-0008Cr-PY for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:12 +0000 Received: from [85.158.143.35] by server-5.bemta-6.messagelabs.com id 2D/85-03454-8B7BAB95; Thu, 14 Sep 2017 17:09:12 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTXf79l2 RBtNvqFss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBltVyoKZgpUdC24wtjA+Je3i5GLQ0hgM6PE 7SMXmLoYOYGc04wSH0/bg9hsApoSdz5/AouLCEhLXPt8mRHEZhaIk3i/qJEFxBYWcJNo/HGWD cRmEVCV6Pn9CCzOK2Ap8fJfHzOILSEgL7Gr7SIriM0pYCWx+/cVZohdlhK77nxln8DIvYCRYR WjRnFqUVlqka6xgV5SUWZ6RkluYmaOrqGBmV5uanFxYnpqTmJSsV5yfu4mRqB3GYBgB+PftYG HGCU5mJREeffq7owU4kvKT6nMSCzOiC8qzUktPsQow8GhJMF7Y9uuSCHBotT01Iq0zBxgmMGk JTh4lER480DSvMUFibnFmekQqVOMuhwdN+/+YRJiycvPS5US560DKRIAKcoozYMbAQv5S4yyU sK8jEBHCfEUpBblZpagyr9iFOdgVBLm3QQyhSczrwRu0yugI5iAjjhzegfIESWJCCmpBkatJ9 5BZZH12/q2zz78Mf3WKe1LUw5yNykzmr2Kvdtzv3D5ZY2uOrX4qM9Ty6b0y/lkBmQzX388MfH phndTz1RPaGEXnDJ7/2U7k8Lmw7OF+cMXLD1Z0sbYm/6l60JkUdUkp2SJ+EkTXu+3m3I/IuWu YMWB/Nm6GpzrewpDkqxuJvyJLvLiz1NiKc5INNRiLipOBADHaXKVdAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1505408951!82766513!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 40260 invoked from network); 14 Sep 2017 17:09:11 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-21.messagelabs.com with SMTP; 14 Sep 2017 17:09:11 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8F4D16A0; Thu, 14 Sep 2017 10:09:10 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0689D3F483; Thu, 14 Sep 2017 10:09:09 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:58 +0100 Message-Id: <20170914170859.30553-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 4/5] xen/arm: Move sysregs.h in arm64 sub-directory X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" sysregs.h contains only code protected by #ifdef CONFIG_ARM_64. Move it in arm64 sub-directory to reflect that and remove the #ifdef. At the same time, fixup the guards. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by --- xen/include/asm-arm/arm64/processor.h | 2 ++ xen/include/asm-arm/{ => arm64}/sysregs.h | 10 +++------- xen/include/asm-arm/processor.h | 1 - 3 files changed, 5 insertions(+), 8 deletions(-) rename xen/include/asm-arm/{ => arm64}/sysregs.h (98%) diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index 24f836b023..c18ab7203d 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,6 +3,8 @@ #include +#include + #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h similarity index 98% rename from xen/include/asm-arm/sysregs.h rename to xen/include/asm-arm/arm64/sysregs.h index 887368e248..084d2a1e5d 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -1,7 +1,5 @@ -#ifndef __ASM_ARM_SYSREGS_H -#define __ASM_ARM_SYSREGS_H - -#ifdef CONFIG_ARM_64 +#ifndef __ASM_ARM_ARM64_SYSREGS_H +#define __ASM_ARM_ARM64_SYSREGS_H #include @@ -168,9 +166,7 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) -#endif - -#endif +#endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* * Local variables: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 9f7a42f86b..d791c12c9c 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -2,7 +2,6 @@ #define __ASM_ARM_PROCESSOR_H #include -#include #ifndef __ASSEMBLY__ #include #endif From patchwork Thu Sep 14 17:08:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112585 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1002966qgf; Thu, 14 Sep 2017 10:11:30 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDuQ7waeP3u/uaRbmL1wzxbAi0SupqWXxnWYS83jOoD2LDifDfFxeK81epDzQE2O81ez6Dq X-Received: by 10.107.20.20 with SMTP id 20mr4381288iou.229.1505409090018; Thu, 14 Sep 2017 10:11:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409090; cv=none; d=google.com; s=arc-20160816; b=ryvuYATJ8vBxwcf82WtR4Exspk1CT9DqAQ1YU1/gyV53cc8ob4EAs6+Mv/kCVKQN07 8NxKMOqNp7eXIAloL71Etym30ulhOCCqlwcO1U/sm+uGFw7o43UOE9iaCzKjTeSK1uRt jYfU50/QErjZbEiw4r9XaO8/tDUpQpqcz4XCI9/UX7aQ9ZGiD/wACd+ih3FRmT4nPvPh hurVTva4eBv6UIE1MRfS7fu3R1bi1vgsyJT4T042tkJw6IAIhG19rRWKVtWXXLZXgILU VfNdsrMhT+ZsqyF8YXVAUzjUpsUpGsAx0L0pjzvxkVKwk7Hl7GTpTeuCVBk/U2qFyPZw pGOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=oEKH7gBvLmgwetrp7SOWm2QdFrNpUX4SyoJIeg0j9bg=; b=h4tbOaQ8gChh3loDAyltyey0fae55V06IwK9pZ9xU01/TxgXwoNuB2tnxhODCkNl2U msuBF3PMro7n3ED9MECEQZ4JrKpYAbvChTOWMZChDpHTt8XD0kz8Q3KkWotHSrNnS8CX UcLPoiaitwMbWFiNC6Gaq9b00QPM6lwoYq+N8e9PHnISyPKdgxOgn1n0/tl8FECIDlYw h9dsSA6+y7mA2xv7PdS0zhpMiWLlrg/4MxtMgXOnmlFQBFE8CdkIwOSGB5u51iXD/bwA kfpQ+feCZewboP2HHeOUQcwcXBURRQHaeZfhhP55coaXj2KOtTQgN+IeAKYCSB7eBFaR UDvw== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x1si5989310iof.254.2017.09.14.10.11.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:29 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdb-0008Ga-SF; Thu, 14 Sep 2017 17:09:15 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXda-0008E7-HJ for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:14 +0000 Received: from [85.158.137.68] by server-1.bemta-3.messagelabs.com id A8/C3-02048-9B7BAB95; Thu, 14 Sep 2017 17:09:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTXfn9l2 RBsevslgs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBltV/ezFpyWqbg97Q9zA+MqiS5GLg4hgc2M Es+uXGGHcE4zSrx/voqti5GTg01AU+LO509MILaIgLTEtc+XGUFsZoE4ifeLGllAbGEBG4lVh 86xdjFycLAIqEoc3xIHYvIKWEocbTUBqZAQkJfY1XaRFcTmFLCS2P37CjOILQRUsuvOV/YJjN wLGBlWMWoUpxaVpRbpGlroJRVlpmeU5CZm5ugaGhjr5aYWFyemp+YkJhXrJefnbmIEereegYF xB+Pv056HGCU5mJREeffq7owU4kvKT6nMSCzOiC8qzUktPsQow8GhJMErBAwWIcGi1PTUirTM HGCYwaQlOHiURHjztgGleYsLEnOLM9MhUqcYdTk6bt79wyTEkpeflyolzvsdpEgApCijNA9uB CzkLzHKSgnzMjIwMAjxFKQW5WaWoMq/YhTnYFQS5v0AMoUnM68EbtMroCOYgI44c3oHyBEliQ gpqQbGjIXG7ZI9LXe/Hl/6fr75FUnF0C65pJ22rck7al199wh18Ht8iLif/VN9qbPva7s1r7j lVt4Q7lEKtl4y9YL9VAsJUd8nu2rFZfz3X5IImD8jyuLUrs1LFHee8jl2Q+iAn9XKB6uO2d// zrKmIsi2/+jhdY1dLt/XXb3Dfjfroab9huJAI59gJZbijERDLeai4kQAq1P2DnQCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-10.tower-31.messagelabs.com!1505408952!114150108!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10513 invoked from network); 14 Sep 2017 17:09:12 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-31.messagelabs.com with SMTP; 14 Sep 2017 17:09:12 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F1361435; Thu, 14 Sep 2017 10:09:12 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30BAE3F483; Thu, 14 Sep 2017 10:09:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:59 +0100 Message-Id: <20170914170859.30553-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 5/5] xen/arm: Limit the scope of cpregs.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, cpregs.h is indirectly included every files of the hypervisor even for arm64. However, the only use for arm64 is when emulating co-processors. For arm32, all users of processor.h expect cpregs.h to be included in order to access co-processors. So move the inclusion in asm-arm/arm32/processor.h. cpregs.h will also be directly included in the co-processors emulation to accommodate arm64. This is drastically reducing the exposure of cpregs.h to any source file on arm64. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v3: - Expand the rationale about this patch - Add Stefano's acked-by Changes in v2: - Update commit message --- xen/arch/arm/smp.c | 1 - xen/arch/arm/vcpreg.c | 1 + xen/arch/arm/vgic-v3.c | 1 + xen/arch/arm/vtimer.c | 2 ++ xen/include/asm-arm/arm32/processor.h | 2 ++ xen/include/asm-arm/percpu.h | 1 - xen/include/asm-arm/processor.h | 1 - 7 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index e7df0874d6..554f4992e6 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,6 +1,5 @@ #include #include -#include #include #include #include diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index f3b08403fb..e363183ba8 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -18,6 +18,7 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index cbeac28b28..a0cf993d13 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 9c7e8f441c..0460962f08 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include #include #include +#include /* * Check if regs is allowed access, user_gate is tail end of a diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index 68cc82147e..fb330812af 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H +#include + #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index 7968532462..cdf64e0f77 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,7 +4,6 @@ #ifndef __ASSEMBLY__ #include -#include #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index d791c12c9c..cd45e5f48f 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -1,7 +1,6 @@ #ifndef __ASM_ARM_PROCESSOR_H #define __ASM_ARM_PROCESSOR_H -#include #ifndef __ASSEMBLY__ #include #endif