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Thu, 14 Sep 2017 15:37:48 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , stable@vger.kernel.org Subject: [PATCH] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Date: Thu, 14 Sep 2017 16:37:21 +0200 Message-id: <1505399852-4787-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLIsWRmVeSWpSXmKPExsWy7djP87q2U3ZFGjx4IWuxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWiwUbHzE6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZf2afYC14wFvxdtJb1gbGM9xdjJwcEgImEkfXLmOEsMUkLtxbz9bFyMUh JLCUUaJ363lWCOczo8TeK48ZYTom9k5mh0gsY5RY8uQlM4TTwCSx59dUdpAqNgFDia63XWwg toiAg8TnT68ZQYqYBf4ySvzbvw6sSFggTmJ5RwuYzSKgKnH79WewBl4Bd4kft/exQqyTkzh5 bDLYHRICH1kl2g4tYYJIuEg83/kHyhaWeHV8CzuELSNxeXI3C4TdzyjR1KoNYc9glDj3lhfC tpY4fPwi2AJmAT6JSdumA73AARTnlehoE4Io8ZDY1w9zg6PE1XXLwcYLCcRKTNv/nHECo9QC RoZVjCKppcW56anFpnrFibnFpXnpesn5uZsYgZF4+t/xrzsYlx6zOsQowMGoxMNrabMzUog1 say4MvcQowQHs5IIr+vEXZFCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeW2j2iKFBNITS1KzU1ML UotgskwcnFINjNrzUiZNYZ4/z7Htj4IKW/intE49lcjda5Z+cy/Kyfqcu+BE+ZlnbgZfrL49 99/wYGEHN++fikWeLk2m+7z37w7Pk5HezjSpbu+1LObvR/ZXJE1W9sub3MZ+p5i5YcXR/1bJ OZefBNrtnq19ebKIxR5jHZ9vRt0tz5JevLjTw213MO/Qtz2Wi5RYijMSDbWYi4oTAUvyFUvA AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOJMWRmVeSWpSXmKPExsVy+t/xK7q2U3ZFGnyayGixccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLwm3ZWiwUbHzE6cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZf2afYC14wFvxdtJb1gbGM9xdjJwcEgImEhN7J7ND2GISF+6tZ+ti5OIQ EljCKLHkTxc7hNPEJNH2bDMzSBWbgKFE19suNhBbRMBB4vOn14wgRcwCfxkl/tzrA0sIC8RJ LO9oARvLIqAqcfv1Z7A4r4C7xI/b+1gh1slJnDw2mXUCI/cCRoZVjCKppcW56bnFRnrFibnF pXnpesn5uZsYgcGx7djPLTsYu94FH2IU4GBU4uF9YLkzUog1say4MvcQowQHs5IIr+vEXZFC vCmJlVWpRfnxRaU5qcWHGKU5WJTEeXv3rI4UEkhPLEnNTk0tSC2CyTJxcEo1MKpeW3H2wMbf dbpKknHruE9XBWoE8767sf/s33utFVX5JZGrc2eFKAtMvV7a1MV1TNNu1dVdiptP2Zdeinj4 MXjDxXNCfdcjDySVlf2du/Ay94SZOXeUTO7cyVOus3v6Ye1rj8N2KSXHZl52fLDop+aS3bd8 PooErkgRMm5d8fl3hv38torkk7eUWIozEg21mIuKEwGUfDH6CgIAAA== X-CMS-MailID: 20170914143749eucas1p1f3206ff81fabc945ffc79cbddb45afc9 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20170914143749eucas1p1f3206ff81fabc945ffc79cbddb45afc9 X-RootMTR: 20170914143749eucas1p1f3206ff81fabc945ffc79cbddb45afc9 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable. Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") CC: stable@vger.kernel.org # v4.13 Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..d2fa36bef7d1 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -294,6 +294,15 @@ enum exynos4_plls { #define PLL_ENABLED (1 << 31) #define PLL_LOCKED (1 << 29) +static void exynos4_clk_enable_pll(u32 reg) +{ + u32 pll_con; + + pll_con = readl(reg_base + reg); + pll_con |= PLL_ENABLED; + writel(pll_con, reg_base + reg); +} + static void exynos4_clk_wait_for_pll(u32 reg) { u32 pll_con; @@ -315,6 +324,9 @@ static int exynos4_clk_suspend(void) samsung_clk_save(reg_base, exynos4_save_pll, ARRAY_SIZE(exynos4_clk_pll_regs)); + exynos4_clk_enable_pll(EPLL_CON0); + exynos4_clk_enable_pll(VPLL_CON0); + if (exynos4_soc == EXYNOS4210) { samsung_clk_save(reg_base, exynos4_save_soc, ARRAY_SIZE(exynos4210_clk_save));