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Wed, 11 Mar 2020 12:18:41 +0000 From: To: CC: , , , , , , , , Subject: [PATCH v5 01/17] wilc1000: add hif.h Thread-Topic: [PATCH v5 01/17] wilc1000: add hif.h Thread-Index: AQHV958yXyXB7giAEUeJSrkRyyuM3Q== Date: Wed, 11 Mar 2020 12:18:40 +0000 Message-ID: <20200311121809.5610-2-ajay.kathat@microchip.com> References: <20200311121809.5610-1-ajay.kathat@microchip.com> In-Reply-To: <20200311121809.5610-1-ajay.kathat@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [121.244.27.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1dba8de8-aa35-4e93-e751-08d7c5b65649 x-ms-traffictypediagnostic: BYAPR11MB2805: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:127; x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(26005); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ocIbQrfou7wdB8rhxqUky5Yhj/jqBtxgIDj+e0JHozo1V/vDbZdpXYvmGalVPH/I8plKUcvAeL7cWDzcy8OdcAgKWEPz6Q2/8VZUAdatS8MKQmLzLbRS+TqlTT/zsn7D13JRQ00nP6eX4qveytfgOQ79OoHIpujh19vKE0GIFpB3rxMZ7VEhPQNEzvNgoJlI1TmfsmRKFJ7ifZRTXxtgQPmaOLcSY8zGrZWCzn5KB5BcBU1vDsxHMnaUcqr9AzTNA3XGPwke62F26aeUi24yqkr/uJVCsrcBbJuoRwE/zr5/iDlKzCN8/io0w3l7ryZJs9gchJ5F2LTK9riPkZmAMaeN9pScChFP/5yGdEyGCURG7Gb6evAZyyu/S7c79HANmZIOdd/k6DqTIpPEWAtz+BXTDOSg4D0wy4p3y1h6rbnIZMaCdoDj99Au2BTP+AFx x-ms-exchange-antispam-messagedata: ZhnTUJhrnHsviCA4st0zHJF04wCxrK1H9b0FKN5cMx0baSwgo/XjG3l8W5YNTbj+I4kn4rYUGeuOW/zwwHY5BJRrkOZOdeS6Ps0C46GY39A7kmEMHZ9zTb6xq1oWC3J1PmC3Q7PpekfXnermTui9/w== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1dba8de8-aa35-4e93-e751-08d7c5b65649 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:40.4826 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UnSrzUhb//k/hdx/9HubtRKJhdq65VcJMuTALPN9EThA5zatTmvA8jYacL9/jgVyR1eQDSWc8QBLyKoSNmbRBmfZUcktjMCk8v2vwXj5KSE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/hif.h' to 'drivers/net/wireless/microchip/wilc1000/hif.h'. Signed-off-by: Ajay Singh --- drivers/net/wireless/microchip/wilc1000/hif.h | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/hif.h diff --git a/drivers/net/wireless/microchip/wilc1000/hif.h b/drivers/net/wireless/microchip/wilc1000/hif.h new file mode 100644 index 000000000000..db9179171f05 --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/hif.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries + * All rights reserved. + */ + +#ifndef WILC_HIF_H +#define WILC_HIF_H +#include +#include "wlan_if.h" + +enum { + WILC_IDLE_MODE = 0x0, + WILC_AP_MODE = 0x1, + WILC_STATION_MODE = 0x2, + WILC_GO_MODE = 0x3, + WILC_CLIENT_MODE = 0x4 +}; + +#define WILC_MAX_NUM_PROBED_SSID 10 + +#define WILC_TX_MIC_KEY_LEN 8 +#define WILC_RX_MIC_KEY_LEN 8 + +#define WILC_ADD_STA_LENGTH 40 +#define WILC_NUM_CONCURRENT_IFC 2 + +enum { + WILC_SET_CFG = 0, + WILC_GET_CFG +}; + +#define WILC_MAX_ASSOC_RESP_FRAME_SIZE 256 + +struct rf_info { + u8 link_speed; + s8 rssi; + u32 tx_cnt; + u32 rx_cnt; + u32 tx_fail_cnt; +}; + +enum host_if_state { + HOST_IF_IDLE = 0, + HOST_IF_SCANNING = 1, + HOST_IF_CONNECTING = 2, + HOST_IF_WAITING_CONN_RESP = 3, + HOST_IF_CONNECTED = 4, + HOST_IF_P2P_LISTEN = 5, + HOST_IF_FORCE_32BIT = 0xFFFFFFFF +}; + +struct cfg_param_attr { + u32 flag; + u16 short_retry_limit; + u16 long_retry_limit; + u16 frag_threshold; + u16 rts_threshold; +}; + +enum cfg_param { + WILC_CFG_PARAM_RETRY_SHORT = BIT(0), + WILC_CFG_PARAM_RETRY_LONG = BIT(1), + WILC_CFG_PARAM_FRAG_THRESHOLD = BIT(2), + WILC_CFG_PARAM_RTS_THRESHOLD = BIT(3) +}; + +enum scan_event { + SCAN_EVENT_NETWORK_FOUND = 0, + SCAN_EVENT_DONE = 1, + SCAN_EVENT_ABORTED = 2, + SCAN_EVENT_FORCE_32BIT = 0xFFFFFFFF +}; + +enum conn_event { + CONN_DISCONN_EVENT_CONN_RESP = 0, + CONN_DISCONN_EVENT_DISCONN_NOTIF = 1, + CONN_DISCONN_EVENT_FORCE_32BIT = 0xFFFFFFFF +}; + +enum { + WILC_HIF_SDIO = 0, + WILC_HIF_SPI = BIT(0) +}; + +enum { + WILC_MAC_STATUS_INIT = -1, + WILC_MAC_STATUS_DISCONNECTED = 0, + WILC_MAC_STATUS_CONNECTED = 1 +}; + +struct wilc_rcvd_net_info { + s8 rssi; + u8 ch; + u16 frame_len; + struct ieee80211_mgmt *mgmt; +}; + +struct wilc_user_scan_req { + void (*scan_result)(enum scan_event evt, + struct wilc_rcvd_net_info *info, void *priv); + void *arg; + u32 ch_cnt; +}; + +struct wilc_conn_info { + u8 bssid[ETH_ALEN]; + u8 security; + enum authtype auth_type; + u8 ch; + u8 *req_ies; + size_t req_ies_len; + u8 *resp_ies; + u16 resp_ies_len; + u16 status; + void (*conn_result)(enum conn_event evt, u8 status, void *priv_data); + void *arg; + void *param; +}; + +struct wilc_remain_ch { + u16 ch; + u32 duration; + void (*expired)(void *priv, u64 cookie); + void *arg; + u32 cookie; +}; + +struct wilc; +struct host_if_drv { + struct wilc_user_scan_req usr_scan_req; + struct wilc_conn_info conn_info; + struct wilc_remain_ch remain_on_ch; + u64 p2p_timeout; + + enum host_if_state hif_state; + + u8 assoc_bssid[ETH_ALEN]; + + struct timer_list scan_timer; + struct wilc_vif *scan_timer_vif; + + struct timer_list connect_timer; + struct wilc_vif *connect_timer_vif; + + struct timer_list remain_on_ch_timer; + struct wilc_vif *remain_on_ch_timer_vif; + + bool ifc_up; + u8 assoc_resp[WILC_MAX_ASSOC_RESP_FRAME_SIZE]; +}; + +struct wilc_vif; +int wilc_remove_wep_key(struct wilc_vif *vif, u8 index); +int wilc_set_wep_default_keyid(struct wilc_vif *vif, u8 index); +int wilc_add_wep_key_bss_sta(struct wilc_vif *vif, const u8 *key, u8 len, + u8 index); +int wilc_add_wep_key_bss_ap(struct wilc_vif *vif, const u8 *key, u8 len, + u8 index, u8 mode, enum authtype auth_type); +int wilc_add_ptk(struct wilc_vif *vif, const u8 *ptk, u8 ptk_key_len, + const u8 *mac_addr, const u8 *rx_mic, const u8 *tx_mic, + u8 mode, u8 cipher_mode, u8 index); +s32 wilc_get_inactive_time(struct wilc_vif *vif, const u8 *mac, + u32 *out_val); +int wilc_add_rx_gtk(struct wilc_vif *vif, const u8 *rx_gtk, u8 gtk_key_len, + u8 index, u32 key_rsc_len, const u8 *key_rsc, + const u8 *rx_mic, const u8 *tx_mic, u8 mode, + u8 cipher_mode); +int wilc_set_pmkid_info(struct wilc_vif *vif, struct wilc_pmkid_attr *pmkid); +int wilc_get_mac_address(struct wilc_vif *vif, u8 *mac_addr); +int wilc_set_join_req(struct wilc_vif *vif, u8 *bssid, const u8 *ies, + size_t ies_len); +int wilc_disconnect(struct wilc_vif *vif); +int wilc_set_mac_chnl_num(struct wilc_vif *vif, u8 channel); +int wilc_get_rssi(struct wilc_vif *vif, s8 *rssi_level); +int wilc_scan(struct wilc_vif *vif, u8 scan_source, u8 scan_type, + u8 *ch_freq_list, u8 ch_list_len, + void (*scan_result_fn)(enum scan_event, + struct wilc_rcvd_net_info *, void *), + void *user_arg, struct cfg80211_scan_request *request); +int wilc_hif_set_cfg(struct wilc_vif *vif, + struct cfg_param_attr *cfg_param); +int wilc_init(struct net_device *dev, struct host_if_drv **hif_drv_handler); +int wilc_deinit(struct wilc_vif *vif); +int wilc_add_beacon(struct wilc_vif *vif, u32 interval, u32 dtim_period, + struct cfg80211_beacon_data *params); +int wilc_del_beacon(struct wilc_vif *vif); +int wilc_add_station(struct wilc_vif *vif, const u8 *mac, + struct station_parameters *params); +int wilc_del_allstation(struct wilc_vif *vif, u8 mac_addr[][ETH_ALEN]); +int wilc_del_station(struct wilc_vif *vif, const u8 *mac_addr); +int wilc_edit_station(struct wilc_vif *vif, const u8 *mac, + struct station_parameters *params); +int wilc_set_power_mgmt(struct wilc_vif *vif, bool enabled, u32 timeout); +int wilc_setup_multicast_filter(struct wilc_vif *vif, u32 enabled, u32 count, + u8 *mc_list); +int wilc_remain_on_channel(struct wilc_vif *vif, u64 cookie, + u32 duration, u16 chan, + void (*expired)(void *, u64), + void *user_arg); +int wilc_listen_state_expired(struct wilc_vif *vif, u64 cookie); +void wilc_frame_register(struct wilc_vif *vif, u16 frame_type, bool reg); +int wilc_set_operation_mode(struct wilc_vif *vif, int index, u8 mode, + u8 ifc_id); +int wilc_get_statistics(struct wilc_vif *vif, struct rf_info *stats); +int wilc_get_vif_idx(struct wilc_vif *vif); +int wilc_set_tx_power(struct wilc_vif *vif, u8 tx_power); +int wilc_get_tx_power(struct wilc_vif *vif, u8 *tx_power); +void wilc_scan_complete_received(struct wilc *wilc, u8 *buffer, u32 length); +void wilc_network_info_received(struct wilc *wilc, u8 *buffer, u32 length); +void wilc_gnrl_async_info_received(struct wilc *wilc, u8 *buffer, u32 length); +void *wilc_parse_join_bss_param(struct cfg80211_bss *bss, + struct cfg80211_crypto_settings *crypto); +#endif From patchwork Wed Mar 11 12:18:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32906C2BB58 for ; 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x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(30864003)(26005)(579004)(559001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ErZMQN2DZ29OApy0AeMR9HkP4vDEQ4uueyT69uqUmwo+gD2jv8lWPzAAGQpKXW3AaGKUZugFPiVh8ZUeeHqMwxIei6MbgyKXFJ7+41+k1IfqbdKBxWTP4jwHgRqulu4ApYuGEHi1seO9XpdEXFEwF8c8p/Lp/m/GcbqvCwg0QRsRVRdicmummv6ukRGE1khF9FLitThcvevAXjiH8altPH7n2Wi/JyWOa3n9q4pNXxG29F5EUwtRYi+h/nIgst7ESyNEh9qEfp5dqfrPAOnOPFhEdazbTxp5emd/eLKK1XQPBhx8ufPZ52Df4SQCm4b3axT90jCo93PBV/RZZNGIxWreGH4Ew4O0jd/4rDEkYWBy1Oq9mGnLoKs4iSG87+pr6/1LmtmumJkFKY+ePah8lbm2DWDrl06bhUkN+B8/w4pICcL4yMZqE9am3P0dNUqq x-ms-exchange-antispam-messagedata: ZxTuoDm/sZazsHgJJfYw2EdZ4Aw7HqhHHmMOaqB0wiCwRdGvseZz5IT4rTJiEd20ZPAxm+SLta7dNvhxa7yx9OArIHXRqiF1OGx7Siun7kBpySoEZa3Rl4dn3K5bJQorKFV7jYtT6Moibm6afdZkPQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 2c264f30-1f97-4d48-adf1-08d7c5b656d4 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:42.6293 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AmxyjPD9ViCvkaJT32aGOJCHTGfEs3/MbDLDXQR2Fd5kY7EnXKPvcPYGsDuH47KAKLZm14g0mjofOH1JZPUVdOwpvfWSQLaQZz5AvCR/q9I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/wlan_if.h' to 'drivers/net/wireless/microchip/wilc1000/wlan_if.h'. Signed-off-by: Ajay Singh --- .../net/wireless/microchip/wilc1000/wlan_if.h | 803 ++++++++++++++++++ 1 file changed, 803 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/wlan_if.h diff --git a/drivers/net/wireless/microchip/wilc1000/wlan_if.h b/drivers/net/wireless/microchip/wilc1000/wlan_if.h new file mode 100644 index 000000000000..f85fd575136d --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/wlan_if.h @@ -0,0 +1,803 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#ifndef WILC_WLAN_IF_H +#define WILC_WLAN_IF_H + +#include +#include "fw.h" + +/******************************************** + * + * Wlan Configuration ID + * + ********************************************/ + +enum bss_types { + WILC_FW_BSS_TYPE_INFRA = 0, + WILC_FW_BSS_TYPE_INDEPENDENT, + WILC_FW_BSS_TYPE_AP, +}; + +enum { + WILC_FW_OPER_MODE_B_ONLY = 0, /* 1, 2 M, otherwise 5, 11 M */ + WILC_FW_OPER_MODE_G_ONLY, /* 6,12,24 otherwise 9,18,36,48,54 */ + WILC_FW_OPER_MODE_G_MIXED_11B_1, /* 1,2,5.5,11 otherwise all on */ + WILC_FW_OPER_MODE_G_MIXED_11B_2, /* 1,2,5,11,6,12,24 otherwise all on */ +}; + +enum { + WILC_FW_PREAMBLE_SHORT = 0, /* Short Preamble */ + WILC_FW_PREAMBLE_LONG = 1, /* Long Preamble */ + WILC_FW_PREAMBLE_AUTO = 2, /* Auto Preamble Selection */ +}; + +enum { + WILC_FW_PASSIVE_SCAN = 0, + WILC_FW_ACTIVE_SCAN = 1, +}; + +enum { + WILC_FW_NO_POWERSAVE = 0, + WILC_FW_MIN_FAST_PS = 1, + WILC_FW_MAX_FAST_PS = 2, + WILC_FW_MIN_PSPOLL_PS = 3, + WILC_FW_MAX_PSPOLL_PS = 4 +}; + +enum chip_ps_states { + WILC_CHIP_WAKEDUP = 0, + WILC_CHIP_SLEEPING_AUTO = 1, + WILC_CHIP_SLEEPING_MANUAL = 2 +}; + +enum bus_acquire { + WILC_BUS_ACQUIRE_ONLY = 0, + WILC_BUS_ACQUIRE_AND_WAKEUP = 1, +}; + +enum bus_release { + WILC_BUS_RELEASE_ONLY = 0, + WILC_BUS_RELEASE_ALLOW_SLEEP = 1, +}; + +enum { + WILC_FW_NO_ENCRYPT = 0, + WILC_FW_ENCRYPT_ENABLED = BIT(0), + WILC_FW_WEP = BIT(1), + WILC_FW_WEP_EXTENDED = BIT(2), + WILC_FW_WPA = BIT(3), + WILC_FW_WPA2 = BIT(4), + WILC_FW_AES = BIT(5), + WILC_FW_TKIP = BIT(6) +}; + +enum { + WILC_FW_SEC_NO = WILC_FW_NO_ENCRYPT, + WILC_FW_SEC_WEP = WILC_FW_WEP | WILC_FW_ENCRYPT_ENABLED, + WILC_FW_SEC_WEP_EXTENDED = WILC_FW_WEP_EXTENDED | WILC_FW_SEC_WEP, + WILC_FW_SEC_WPA = WILC_FW_WPA | WILC_FW_ENCRYPT_ENABLED, + WILC_FW_SEC_WPA_AES = WILC_FW_AES | WILC_FW_SEC_WPA, + WILC_FW_SEC_WPA_TKIP = WILC_FW_TKIP | WILC_FW_SEC_WPA, + WILC_FW_SEC_WPA2 = WILC_FW_WPA2 | WILC_FW_ENCRYPT_ENABLED, + WILC_FW_SEC_WPA2_AES = WILC_FW_AES | WILC_FW_SEC_WPA2, + WILC_FW_SEC_WPA2_TKIP = WILC_FW_TKIP | WILC_FW_SEC_WPA2 +}; + +enum authtype { + WILC_FW_AUTH_OPEN_SYSTEM = 1, + WILC_FW_AUTH_SHARED_KEY = 2, + WILC_FW_AUTH_ANY = 3, + WILC_FW_AUTH_IEEE8021 = 5 +}; + +enum site_survey { + WILC_FW_SITE_SURVEY_1CH = 0, + WILC_FW_SITE_SURVEY_ALL_CH = 1, + WILC_FW_SITE_SURVEY_OFF = 2 +}; + +enum { + WILC_FW_ACK_POLICY_NORMAL = 0, + WILC_FW_ACK_NO_POLICY, +}; + +enum { + WILC_FW_REKEY_POLICY_DISABLE = 1, + WILC_FW_REKEY_POLICY_TIME_BASE, + WILC_FW_REKEY_POLICY_PKT_BASE, + WILC_FW_REKEY_POLICY_TIME_PKT_BASE +}; + +enum { + WILC_FW_FILTER_NO = 0x00, + WILC_FW_FILTER_AP_ONLY = 0x01, + WILC_FW_FILTER_STA_ONLY = 0x02 +}; + +enum { + WILC_FW_11N_PROT_AUTO = 0, /* Auto */ + WILC_FW_11N_NO_PROT, /* Do not use any protection */ + WILC_FW_11N_PROT_ERP, /* Protect all ERP frame exchanges */ + WILC_FW_11N_PROT_HT, /* Protect all HT frame exchanges */ + WILC_FW_11N_PROT_GF /* Protect all GF frame exchanges */ +}; + +enum { + WILC_FW_ERP_PROT_SELF_CTS, + WILC_FW_ERP_PROT_RTS_CTS, +}; + +enum { + WILC_FW_11N_OP_MODE_HT_MIXED = 1, + WILC_FW_11N_OP_MODE_HT_ONLY_20MHZ, + WILC_FW_11N_OP_MODE_HT_ONLY_20_40MHZ, +}; + +enum { + WILC_FW_OBBS_NONHT_NO_DETECT = 0, + WILC_FW_OBBS_NONHT_DETECT_ONLY = 1, + WILC_FW_OBBS_NONHT_DETECT_PROTECT = 2, + WILC_FW_OBBS_NONHT_DETECT_PROTECT_REPORT = 3, +}; + +enum { + WILC_FW_HT_PROT_RTS_CTS_NONHT = 0, /* RTS-CTS at non-HT rate */ + WILC_FW_HT_PROT_FIRST_FRAME_NONHT, /* First frame at non-HT rate */ + WILC_FW_HT_PROT_LSIG_TXOP, /* LSIG TXOP Protection */ + WILC_FW_HT_PROT_FIRST_FRAME_MIXED, /* First frame at Mixed format */ +}; + +enum { + WILC_FW_SMPS_MODE_STATIC = 1, + WILC_FW_SMPS_MODE_DYNAMIC = 2, + WILC_FW_SMPS_MODE_MIMO = 3, /* power save disable */ +}; + +enum { + WILC_FW_TX_RATE_AUTO = 0, + WILC_FW_TX_RATE_MBPS_1 = 1, + WILC_FW_TX_RATE_MBPS_2 = 2, + WILC_FW_TX_RATE_MBPS_5_5 = 5, + WILC_FW_TX_RATE_MBPS_11 = 11, + WILC_FW_TX_RATE_MBPS_6 = 6, + WILC_FW_TX_RATE_MBPS_9 = 9, + WILC_FW_TX_RATE_MBPS_12 = 12, + WILC_FW_TX_RATE_MBPS_18 = 18, + WILC_FW_TX_RATE_MBPS_24 = 24, + WILC_FW_TX_RATE_MBPS_36 = 36, + WILC_FW_TX_RATE_MBPS_48 = 48, + WILC_FW_TX_RATE_MBPS_54 = 54 +}; + +enum { + WILC_FW_DEFAULT_SCAN = 0, + WILC_FW_USER_SCAN = BIT(0), + WILC_FW_OBSS_PERIODIC_SCAN = BIT(1), + WILC_FW_OBSS_ONETIME_SCAN = BIT(2) +}; + +enum { + WILC_FW_ACTION_FRM_IDX = 0, + WILC_FW_PROBE_REQ_IDX = 1 +}; + +enum wid_type { + WID_CHAR = 0, + WID_SHORT = 1, + WID_INT = 2, + WID_STR = 3, + WID_BIN_DATA = 4, + WID_BIN = 5, +}; + +struct wid { + u16 id; + enum wid_type type; + s32 size; + s8 *val; +}; + +enum { + WID_NIL = 0xffff, + + /* + * BSS Type + * ----------------------------------------------------------- + * Configuration : Infrastructure Independent Access Point + * Values to set : 0 1 2 + * ----------------------------------------------------------- + */ + WID_BSS_TYPE = 0x0000, + + /* + * Transmit Rate + * ----------------------------------------------------------- + * Configuration : 1 2 5.5 11 6 9 12 18 24 36 48 54 + * Values to set : 1 2 5 11 6 9 12 18 24 36 48 54 + * ----------------------------------------------------------- + */ + WID_CURRENT_TX_RATE = 0x0001, + + /* + * Channel + * ----------------------------------------------------------- + * Configuration(g) : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 + * Values to set : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 + * ----------------------------------------------------------- + */ + WID_CURRENT_CHANNEL = 0x0002, + + /* + * Preamble + * ----------------------------------------------------------- + * Configuration : short long Auto + * Values to set : 0 1 2 + * ----------------------------------------------------------- + */ + WID_PREAMBLE = 0x0003, + + /* + * 11g operating mode (ignored if 11g not present) + * ----------------------------------------------------------- + * Configuration : HighPerf Compat(RSet #1) Compat(RSet #2) + * Values to set : 1 2 3 + * ----------------------------------------------------------- + */ + WID_11G_OPERATING_MODE = 0x0004, + + /* + * Mac status (response only) + * ----------------------------------------------------------- + * Configuration : disconnect connect + * Values to get : 0 1 + * ----------------------------------------------------------- + */ + WID_STATUS = 0x0005, + + /* + * Scan type + * ----------------------------------------------------------- + * Configuration : Passive Scanning Active Scanning + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_SCAN_TYPE = 0x0007, + + /* + * Key Id (WEP default key Id) + * ----------------------------------------------------------- + * Configuration : Any value between 0 to 3 + * Values to set : Same value. Default is 0 + * ----------------------------------------------------------- + */ + WID_KEY_ID = 0x0009, + + /* + * QoS Enable + * ----------------------------------------------------------- + * Configuration : QoS Disable WMM Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_QOS_ENABLE = 0x000A, + + /* + * Power Management + * ----------------------------------------------------------- + * Configuration : NO_POWERSAVE MIN_POWERSAVE MAX_POWERSAVE + * Values to set : 0 1 2 + * ----------------------------------------------------------- + */ + WID_POWER_MANAGEMENT = 0x000B, + + /* + * WEP/802 11I Configuration + * ----------------------------------------------------------- + * Configuration:Disable WP40 WP104 WPA-AES WPA-TKIP RSN-AES RSN-TKIP + * Values (0x) : 00 03 07 29 49 31 51 + * Configuration:WPA-AES+TKIP RSN-AES+TKIP + * Values (0x) : 69 71 + * ----------------------------------------------------------- + */ + WID_11I_MODE = 0x000C, + + /* + * WEP Configuration: Used in BSS STA mode only when WEP is enabled + * ----------------------------------------------------------- + * Configuration : Open System Shared Key Any Type | 802.1x Auth + * Values (0x) : 01 02 03 | BIT2 + * ----------------------------------------------------------- + */ + WID_AUTH_TYPE = 0x000D, + + /* + * Site Survey Type + * ----------------------------------------------------------- + * Configuration : Values to set + * Survey 1 Channel : 0 + * survey all Channels : 1 + * Disable Site Survey : 2 + * ----------------------------------------------------------- + */ + WID_SITE_SURVEY = 0x000E, + + /* + * Listen Interval + * ----------------------------------------------------------- + * Configuration : Any value between 1 to 255 + * Values to set : Same value. Default is 3 + * ----------------------------------------------------------- + */ + WID_LISTEN_INTERVAL = 0x000F, + + /* + * DTIM Period + * ----------------------------------------------------------- + * Configuration : Any value between 1 to 255 + * Values to set : Same value. Default is 3 + * ----------------------------------------------------------- + */ + WID_DTIM_PERIOD = 0x0010, + + /* + * ACK Policy + * ----------------------------------------------------------- + * Configuration : Normal Ack No Ack + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_ACK_POLICY = 0x0011, + + /* + * Reset MAC (Set only) + * ----------------------------------------------------------- + * Configuration : Don't Reset Reset No Request + * Values to set : 0 1 2 + * ----------------------------------------------------------- + */ + WID_RESET = 0x0012, + + /* + * Broadcast SSID Option: Setting this will adhere to "" SSID element + * ----------------------------------------------------------- + * Configuration : Enable Disable + * Values to set : 1 0 + * ----------------------------------------------------------- + */ + WID_BCAST_SSID = 0x0015, + + /* + * Disconnect (Station) + * ----------------------------------------------------------- + * Configuration : Association ID + * Values to set : Association ID + * ----------------------------------------------------------- + */ + WID_DISCONNECT = 0x0016, + + /* + * 11a Tx Power Level + * ----------------------------------------------------------- + * Configuration : Sets TX Power (Higher the value greater the power) + * Values to set : Any value between 0 and 63 (inclusive Default 48) + * ----------------------------------------------------------- + */ + WID_TX_POWER_LEVEL_11A = 0x0018, + + /* + * Group Key Update Policy Selection + * ----------------------------------------------------------- + * Configuration : Disabled timeBased packetBased timePacketBased + * Values to set : 1 2 3 4 + * ----------------------------------------------------------- + */ + WID_REKEY_POLICY = 0x0019, + + /* + * Allow Short Slot + * ----------------------------------------------------------- + * Configuration : Disallow Short Slot Allow Short Slot + * (Enable Only Long Slot) (Enable Short Slot if applicable) + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_SHORT_SLOT_ALLOWED = 0x001A, + + WID_PHY_ACTIVE_REG = 0x001B, + + /* + * 11b Tx Power Level + * ----------------------------------------------------------- + * Configuration : Sets TX Power (Higher the value greater the power) + * Values to set : Any value between 0 and 63 (inclusive Default 48) + * ----------------------------------------------------------- + */ + WID_TX_POWER_LEVEL_11B = 0x001D, + + /* + * Scan Request + * ----------------------------------------------------------- + * Configuration : Request default scan + * Values to set : 0 + * ----------------------------------------------------------- + */ + WID_START_SCAN_REQ = 0x001E, + + /* + * Rssi (get only) + * ----------------------------------------------------------- + * Configuration : + * Values to get : Rssi value + * ----------------------------------------------------------- + */ + WID_RSSI = 0x001F, + + /* + * Join Request + * ----------------------------------------------------------- + * Configuration : Request to join + * Values to set : index of scan result + * ----------------------------------------------------------- + */ + WID_JOIN_REQ = 0x0020, + + WID_LINKSPEED = 0x0026, + + /* + * Enable User Control of TX Power + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_USER_CONTROL_ON_TX_POWER = 0x0027, + + WID_MEMORY_ACCESS_8BIT = 0x0029, + + /* + * Enable Auto RX Sensitivity feature + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_AUTO_RX_SENSITIVITY = 0x0032, + + /* + * Receive Buffer Based Ack + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_DATAFLOW_CONTROL = 0x0033, + + /* + * Scan Filter + * ----------------------------------------------------------- + * Configuration : Class No filter AP only Station Only + * Values to set : 0 1 2 + * Configuration : Priority High Rssi Low Rssi Detect + * Values to set : 0 0x4 0x0 + * Configuration : Channel filter off filter on + * Values to set : 0 0x10 + * ----------------------------------------------------------- + */ + WID_SCAN_FILTER = 0x0036, + + /* + * Link Loss Threshold (measure in the beacon period) + * ----------------------------------------------------------- + * Configuration : Any value between 10 and 254(Set to 255 disable) + * Values to set : Same value. Default is 10 + * ----------------------------------------------------------- + */ + WID_LINK_LOSS_THRESHOLD = 0x0037, + + WID_ABORT_RUNNING_SCAN = 0x003E, + + /* NMAC Character WID list */ + WID_WPS_START = 0x0043, + + /* + * Protection mode for MAC + * ----------------------------------------------------------- + * Configuration : Auto No protection ERP HT GF + * Values to set : 0 1 2 3 4 + * ----------------------------------------------------------- + */ + WID_11N_PROT_MECH = 0x0080, + + /* + * ERP Protection type for MAC + * ----------------------------------------------------------- + * Configuration : Self-CTS RTS-CTS + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_11N_ERP_PROT_TYPE = 0x0081, + + /* + * HT Option Enable + * ----------------------------------------------------------- + * Configuration : HT Enable HT Disable + * Values to set : 1 0 + * ----------------------------------------------------------- + */ + WID_11N_ENABLE = 0x0082, + + /* + * 11n Operating mode (Note that 11g operating mode will also be + * used in addition to this, if this is set to HT Mixed mode) + * ----------------------------------------------------------- + * Configuration : HT Mixed HT Only-20MHz HT Only-20/40MHz + * Values to set : 1 2 3 + * ----------------------------------------------------------- + */ + WID_11N_OPERATING_MODE = 0x0083, + + /* + * 11n OBSS non-HT STA Detection flag + * ----------------------------------------------------------- + * Configuration : Do not detect + * Values to set : 0 + * Configuration : Detect, do not protect or report + * Values to set : 1 + * Configuration : Detect, protect and do not report + * Values to set : 2 + * Configuration : Detect, protect and report to other BSS + * Values to set : 3 + * ----------------------------------------------------------- + */ + WID_11N_OBSS_NONHT_DETECTION = 0x0084, + + /* + * 11n HT Protection Type + * ----------------------------------------------------------- + * Configuration : RTS-CTS First Frame Exchange at non-HT-rate + * Values to set : 0 1 + * Configuration : LSIG TXOP First Frame Exchange in Mixed Fmt + * Values to set : 2 3 + * ----------------------------------------------------------- + */ + WID_11N_HT_PROT_TYPE = 0x0085, + + /* + * 11n RIFS Protection Enable Flag + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_11N_RIFS_PROT_ENABLE = 0x0086, + + /* + * SMPS Mode + * ----------------------------------------------------------- + * Configuration : Static Dynamic MIMO (Power Save Disabled) + * Values to set : 1 2 3 + * ----------------------------------------------------------- + */ + WID_11N_SMPS_MODE = 0x0087, + + /* + * Current transmit MCS + * ----------------------------------------------------------- + * Configuration : MCS Index for data rate + * Values to set : 0 to 7 + * ----------------------------------------------------------- + */ + WID_11N_CURRENT_TX_MCS = 0x0088, + + WID_11N_PRINT_STATS = 0x0089, + + /* + * 11n Short GI Enable Flag + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_11N_SHORT_GI_ENABLE = 0x008D, + + /* + * 11n RIFS Enable Flag + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_RIFS_MODE = 0x0094, + + /* + * TX Abort Feature + * ----------------------------------------------------------- + * Configuration : Disable Self CTS Enable Self CTS + * Values to set : 0 1 + * Configuration : Disable TX Abort Enable TX Abort + * Values to set : 2 3 + * Configuration : Enable HW TX Abort Enable SW TX Abort + * Values to set : 4 5 + * ----------------------------------------------------------- + */ + WID_TX_ABORT_CONFIG = 0x00A1, + + WID_REG_TSSI_11B_VALUE = 0x00A6, + WID_REG_TSSI_11G_VALUE = 0x00A7, + WID_REG_TSSI_11N_VALUE = 0x00A8, + WID_TX_CALIBRATION = 0x00A9, + WID_DSCR_TSSI_11B_VALUE = 0x00AA, + WID_DSCR_TSSI_11G_VALUE = 0x00AB, + WID_DSCR_TSSI_11N_VALUE = 0x00AC, + + /* + * Immediate Block-Ack Support + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 0 1 + * ----------------------------------------------------------- + */ + WID_11N_IMMEDIATE_BA_ENABLED = 0x00AF, + + /* + * TXOP Disable Flag + * ----------------------------------------------------------- + * Configuration : Disable Enable + * Values to set : 1 0 + * ----------------------------------------------------------- + */ + WID_11N_TXOP_PROT_DISABLE = 0x00B0, + + WID_TX_POWER_LEVEL_11N = 0x00B1, + + /* Custom Character WID list */ + /* SCAN Complete notification WID*/ + WID_SCAN_COMPLETE = 0x00C9, + + WID_DEL_BEACON = 0x00CA, + + WID_LOG_TERMINAL_SWITCH = 0x00CD, + WID_TX_POWER = 0x00CE, + /* EMAC Short WID list */ + /* RTS Threshold */ + /* + * ----------------------------------------------------------- + * Configuration : Any value between 256 to 2347 + * Values to set : Same value. Default is 2347 + * ----------------------------------------------------------- + */ + WID_RTS_THRESHOLD = 0x1000, + + /* + * Fragmentation Threshold + * ----------------------------------------------------------- + * Configuration : Any value between 256 to 2346 + * Values to set : Same value. Default is 2346 + * ----------------------------------------------------------- + */ + WID_FRAG_THRESHOLD = 0x1001, + + WID_SHORT_RETRY_LIMIT = 0x1002, + WID_LONG_RETRY_LIMIT = 0x1003, + WID_BEACON_INTERVAL = 0x1006, + WID_MEMORY_ACCESS_16BIT = 0x1008, + WID_PASSIVE_SCAN_TIME = 0x100D, + WID_JOIN_START_TIMEOUT = 0x100F, + WID_ASOC_TIMEOUT = 0x1011, + WID_11I_PROTOCOL_TIMEOUT = 0x1012, + WID_EAPOL_RESPONSE_TIMEOUT = 0x1013, + + /* NMAC Short WID list */ + WID_11N_SIG_QUAL_VAL = 0x1085, + WID_CCA_THRESHOLD = 0x1087, + + /* Custom Short WID list */ + + /* EMAC Integer WID list */ + WID_FAILED_COUNT = 0x2000, + WID_RETRY_COUNT = 0x2001, + WID_MULTIPLE_RETRY_COUNT = 0x2002, + WID_FRAME_DUPLICATE_COUNT = 0x2003, + WID_ACK_FAILURE_COUNT = 0x2004, + WID_RECEIVED_FRAGMENT_COUNT = 0x2005, + WID_MCAST_RECEIVED_FRAME_COUNT = 0x2006, + WID_FCS_ERROR_COUNT = 0x2007, + WID_SUCCESS_FRAME_COUNT = 0x2008, + WID_HUT_TX_COUNT = 0x200A, + WID_TX_FRAGMENT_COUNT = 0x200B, + WID_TX_MULTICAST_FRAME_COUNT = 0x200C, + WID_RTS_SUCCESS_COUNT = 0x200D, + WID_RTS_FAILURE_COUNT = 0x200E, + WID_WEP_UNDECRYPTABLE_COUNT = 0x200F, + WID_REKEY_PERIOD = 0x2010, + WID_REKEY_PACKET_COUNT = 0x2011, + WID_1X_SERV_ADDR = 0x2012, + WID_STACK_IP_ADDR = 0x2013, + WID_STACK_NETMASK_ADDR = 0x2014, + WID_HW_RX_COUNT = 0x2015, + WID_MEMORY_ADDRESS = 0x201E, + WID_MEMORY_ACCESS_32BIT = 0x201F, + + /* NMAC Integer WID list */ + /* Custom Integer WID list */ + WID_GET_INACTIVE_TIME = 0x2084, + /* EMAC String WID list */ + WID_SSID = 0x3000, + WID_FIRMWARE_VERSION = 0x3001, + WID_OPERATIONAL_RATE_SET = 0x3002, + WID_BSSID = 0x3003, + WID_WEP_KEY_VALUE = 0x3004, + WID_11I_PSK = 0x3008, + WID_11E_P_ACTION_REQ = 0x3009, + WID_1X_KEY = 0x300A, + WID_HARDWARE_VERSION = 0x300B, + WID_MAC_ADDR = 0x300C, + WID_HUT_DEST_ADDR = 0x300D, + WID_PHY_VERSION = 0x300F, + WID_SUPP_USERNAME = 0x3010, + WID_SUPP_PASSWORD = 0x3011, + WID_SITE_SURVEY_RESULTS = 0x3012, + WID_RX_POWER_LEVEL = 0x3013, + WID_SET_STA_MAC_INACTIVE_TIME = 0x3017, + WID_ADD_WEP_KEY = 0x3019, + WID_REMOVE_WEP_KEY = 0x301A, + WID_ADD_PTK = 0x301B, + WID_ADD_RX_GTK = 0x301C, + WID_ADD_TX_GTK = 0x301D, + WID_REMOVE_KEY = 0x301E, + WID_ASSOC_REQ_INFO = 0x301F, + WID_ASSOC_RES_INFO = 0x3020, + WID_MANUFACTURER = 0x3026, /* Added for CAPI tool */ + WID_MODEL_NAME = 0x3027, /* Added for CAPI tool */ + WID_MODEL_NUM = 0x3028, /* Added for CAPI tool */ + WID_DEVICE_NAME = 0x3029, /* Added for CAPI tool */ + + /* NMAC String WID list */ + WID_SET_OPERATION_MODE = 0x3079, + WID_11N_P_ACTION_REQ = 0x3080, + WID_HUT_TEST_ID = 0x3081, + WID_PMKID_INFO = 0x3082, + WID_FIRMWARE_INFO = 0x3083, + WID_REGISTER_FRAME = 0x3084, + WID_DEL_ALL_STA = 0x3085, + WID_REMAIN_ON_CHAN = 0x3996, + WID_SSID_PROBE_REQ = 0x3997, + WID_JOIN_REQ_EXTENDED = 0x3998, + + WID_IP_ADDRESS = 0x3999, + + /* Custom String WID list */ + + /* EMAC Binary WID list */ + WID_UAPSD_CONFIG = 0x4001, + WID_UAPSD_STATUS = 0x4002, + WID_WMM_AP_AC_PARAMS = 0x4003, + WID_WMM_STA_AC_PARAMS = 0x4004, + WID_NETWORK_INFO = 0x4005, + WID_STA_JOIN_INFO = 0x4006, + WID_CONNECTED_STA_LIST = 0x4007, + + /* NMAC Binary WID list */ + WID_11N_AUTORATE_TABLE = 0x4080, + + WID_SCAN_CHANNEL_LIST = 0x4084, + + WID_INFO_ELEMENT_PROBE = 0x4085, + WID_INFO_ELEMENT_ASSOCIATE = 0x4086, + WID_ADD_STA = 0X4087, + WID_REMOVE_STA = 0X4088, + WID_EDIT_STA = 0X4089, + WID_ADD_BEACON = 0x408a, + + WID_SETUP_MULTICAST_FILTER = 0x408b, + + /* Miscellaneous WIDs */ + WID_ALL = 0x7FFE, + WID_MAX = 0xFFFF +}; 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Wed, 11 Mar 2020 12:18:44 +0000 From: To: CC: , , , , , , , , Subject: [PATCH v5 05/17] wilc1000: add wlan_cfg.c Thread-Topic: [PATCH v5 05/17] wilc1000: add wlan_cfg.c Thread-Index: AQHV9580CYLMO2Q5IkGwqsvCJkRN4g== Date: Wed, 11 Mar 2020 12:18:43 +0000 Message-ID: <20200311121809.5610-6-ajay.kathat@microchip.com> References: <20200311121809.5610-1-ajay.kathat@microchip.com> In-Reply-To: <20200311121809.5610-1-ajay.kathat@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [121.244.27.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 20a5ba02-33bb-4c90-1746-08d7c5b657bd x-ms-traffictypediagnostic: BYAPR11MB2805: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:343; x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(26005); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: yrjP6fsaOacaZpCCpLbuztYajThH+Raniow9UQdf6ogcGgCsCjeMaPPkkHXdFqffWIHuwm7Q4gZ0EYCSR7EK7pXM08CRraS4vOOwb52qe1vwUYY4t+N2PF1bts1cm3Ea77iEklcUuKt38NcyWvVPb4vWjtV8a7Y6g5PiFxLGTwoiRyezp0G+oM+92PfXw80RbD4DrjBo00yDXccW6lGDceOkvJJ6YOcOq138enykDoEEnf3CWcoAF5ppvtKCIyUTPbSN7dqfxDTNu5LgS5px73oeg8R7wYB+lLvFq3R/gQzGsjU9ZxCRCxP4ZgMYbjw5HNEWRldc5pHkSuMyZQ06eOyZM42TMO9fMX0PexMEWEOoqLNhz55J/bcn/lRfMX22MqQ/z1WYlyAQzPHgiReTKYooZvpvlt7oHxp1ErOJrY9mA3EjDg3eMMXwDyrZXeJb x-ms-exchange-antispam-messagedata: UuYRTT19Eb+KcZznl7lqjbChMzQR4Hqy+dND6BmsBSVdF6gG245HYAXo5+nKLfd6pbOGjxVi4qCZM1OAWbmSqHKJwGyWNT+8UqSrZuORCVbHVfrDlzs/vSrs0HQJYnN89JaAxRKJArF9S1pbGcsEzQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 20a5ba02-33bb-4c90-1746-08d7c5b657bd X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:43.7807 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /pUsAB0HVfxaKZW5mVg9Cra/DO69oEOgmQDfYNTKaP5eidTFuqR8cWK27X1pE/CWDSs86j7S4xkzKOj/SC372m59SXz/+cbhDClMsYfuB80= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/wlan_cfg.c' to 'drivers/net/wireless/microchip/wilc1000/wlan_cfg.c'. Signed-off-by: Ajay Singh --- .../wireless/microchip/wilc1000/wlan_cfg.c | 413 ++++++++++++++++++ 1 file changed, 413 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/wlan_cfg.c diff --git a/drivers/net/wireless/microchip/wilc1000/wlan_cfg.c b/drivers/net/wireless/microchip/wilc1000/wlan_cfg.c new file mode 100644 index 000000000000..fe2a7ed8e5cd --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/wlan_cfg.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#include +#include "wlan_if.h" +#include "wlan.h" +#include "wlan_cfg.h" +#include "netdev.h" + +enum cfg_cmd_type { + CFG_BYTE_CMD = 0, + CFG_HWORD_CMD = 1, + CFG_WORD_CMD = 2, + CFG_STR_CMD = 3, + CFG_BIN_CMD = 4 +}; + +static const struct wilc_cfg_byte g_cfg_byte[] = { + {WID_STATUS, 0}, + {WID_RSSI, 0}, + {WID_LINKSPEED, 0}, + {WID_NIL, 0} +}; + +static const struct wilc_cfg_hword g_cfg_hword[] = { + {WID_NIL, 0} +}; + +static const struct wilc_cfg_word g_cfg_word[] = { + {WID_FAILED_COUNT, 0}, + {WID_RECEIVED_FRAGMENT_COUNT, 0}, + {WID_SUCCESS_FRAME_COUNT, 0}, + {WID_GET_INACTIVE_TIME, 0}, + {WID_NIL, 0} + +}; + +static const struct wilc_cfg_str g_cfg_str[] = { + {WID_FIRMWARE_VERSION, NULL}, + {WID_MAC_ADDR, NULL}, + {WID_ASSOC_RES_INFO, NULL}, + {WID_NIL, NULL} +}; + +#define WILC_RESP_MSG_TYPE_CONFIG_REPLY 'R' +#define WILC_RESP_MSG_TYPE_STATUS_INFO 'I' +#define WILC_RESP_MSG_TYPE_NETWORK_INFO 'N' +#define WILC_RESP_MSG_TYPE_SCAN_COMPLETE 'S' + +/******************************************** + * + * Configuration Functions + * + ********************************************/ + +static int wilc_wlan_cfg_set_byte(u8 *frame, u32 offset, u16 id, u8 val8) +{ + if ((offset + 4) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + put_unaligned_le16(1, &frame[offset + 2]); + frame[offset + 4] = val8; + return 5; +} + +static int wilc_wlan_cfg_set_hword(u8 *frame, u32 offset, u16 id, u16 val16) +{ + if ((offset + 5) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + put_unaligned_le16(2, &frame[offset + 2]); + put_unaligned_le16(val16, &frame[offset + 4]); + + return 6; +} + +static int wilc_wlan_cfg_set_word(u8 *frame, u32 offset, u16 id, u32 val32) +{ + if ((offset + 7) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + put_unaligned_le16(4, &frame[offset + 2]); + put_unaligned_le32(val32, &frame[offset + 4]); + + return 8; +} + +static int wilc_wlan_cfg_set_str(u8 *frame, u32 offset, u16 id, u8 *str, + u32 size) +{ + if ((offset + size + 4) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + put_unaligned_le16(size, &frame[offset + 2]); + if (str && size != 0) + memcpy(&frame[offset + 4], str, size); + + return (size + 4); +} + +static int wilc_wlan_cfg_set_bin(u8 *frame, u32 offset, u16 id, u8 *b, u32 size) +{ + u32 i; + u8 checksum = 0; + + if ((offset + size + 5) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + put_unaligned_le16(size, &frame[offset + 2]); + + if ((b) && size != 0) { + memcpy(&frame[offset + 4], b, size); + for (i = 0; i < size; i++) + checksum += frame[offset + i + 4]; + } + + frame[offset + size + 4] = checksum; + + return (size + 5); +} + +/******************************************** + * + * Configuration Response Functions + * + ********************************************/ + +static void wilc_wlan_parse_response_frame(struct wilc *wl, u8 *info, int size) +{ + u16 wid; + u32 len = 0, i = 0; + struct wilc_cfg *cfg = &wl->cfg; + + while (size > 0) { + i = 0; + wid = get_unaligned_le16(info); + + switch (FIELD_GET(WILC_WID_TYPE, wid)) { + case WID_CHAR: + while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) + i++; + + if (cfg->b[i].id == wid) + cfg->b[i].val = info[4]; + + len = 3; + break; + + case WID_SHORT: + while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) + i++; + + if (cfg->hw[i].id == wid) + cfg->hw[i].val = get_unaligned_le16(&info[4]); + + len = 4; + break; + + case WID_INT: + while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) + i++; + + if (cfg->w[i].id == wid) + cfg->w[i].val = get_unaligned_le32(&info[4]); + + len = 6; + break; + + case WID_STR: + while (cfg->s[i].id != WID_NIL && cfg->s[i].id != wid) + i++; + + if (cfg->s[i].id == wid) + memcpy(cfg->s[i].str, &info[2], info[2] + 2); + + len = 2 + info[2]; + break; + + default: + break; + } + size -= (2 + len); + info += (2 + len); + } +} + +static void wilc_wlan_parse_info_frame(struct wilc *wl, u8 *info) +{ + u32 wid, len; + + wid = get_unaligned_le16(info); + + len = info[2]; + + if (len == 1 && wid == WID_STATUS) { + int i = 0; + + while (wl->cfg.b[i].id != WID_NIL && + wl->cfg.b[i].id != wid) + i++; + + if (wl->cfg.b[i].id == wid) + wl->cfg.b[i].val = info[3]; + } +} + +/******************************************** + * + * Configuration Exported Functions + * + ********************************************/ + +int wilc_wlan_cfg_set_wid(u8 *frame, u32 offset, u16 id, u8 *buf, int size) +{ + u8 type = FIELD_GET(WILC_WID_TYPE, id); + int ret = 0; + + switch (type) { + case CFG_BYTE_CMD: + if (size >= 1) + ret = wilc_wlan_cfg_set_byte(frame, offset, id, *buf); + break; + + case CFG_HWORD_CMD: + if (size >= 2) + ret = wilc_wlan_cfg_set_hword(frame, offset, id, + *((u16 *)buf)); + break; + + case CFG_WORD_CMD: + if (size >= 4) + ret = wilc_wlan_cfg_set_word(frame, offset, id, + *((u32 *)buf)); + break; + + case CFG_STR_CMD: + ret = wilc_wlan_cfg_set_str(frame, offset, id, buf, size); + break; + + case CFG_BIN_CMD: + ret = wilc_wlan_cfg_set_bin(frame, offset, id, buf, size); + break; + } + + return ret; +} + +int wilc_wlan_cfg_get_wid(u8 *frame, u32 offset, u16 id) +{ + if ((offset + 2) >= WILC_MAX_CFG_FRAME_SIZE) + return 0; + + put_unaligned_le16(id, &frame[offset]); + + return 2; +} + +int wilc_wlan_cfg_get_val(struct wilc *wl, u16 wid, u8 *buffer, + u32 buffer_size) +{ + u8 type = FIELD_GET(WILC_WID_TYPE, wid); + int i, ret = 0; + struct wilc_cfg *cfg = &wl->cfg; + + i = 0; + if (type == CFG_BYTE_CMD) { + while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) + i++; + + if (cfg->b[i].id == wid) { + memcpy(buffer, &cfg->b[i].val, 1); + ret = 1; + } + } else if (type == CFG_HWORD_CMD) { + while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) + i++; + + if (cfg->hw[i].id == wid) { + memcpy(buffer, &cfg->hw[i].val, 2); + ret = 2; + } + } else if (type == CFG_WORD_CMD) { + while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) + i++; + + if (cfg->w[i].id == wid) { + memcpy(buffer, &cfg->w[i].val, 4); + ret = 4; + } + } else if (type == CFG_STR_CMD) { + while (cfg->s[i].id != WID_NIL && cfg->s[i].id != wid) + i++; + + if (cfg->s[i].id == wid) { + u16 size = get_unaligned_le16(cfg->s[i].str); + + if (buffer_size >= size) { + memcpy(buffer, &cfg->s[i].str[2], size); + ret = size; + } + } + } + return ret; +} + +void wilc_wlan_cfg_indicate_rx(struct wilc *wilc, u8 *frame, int size, + struct wilc_cfg_rsp *rsp) +{ + u8 msg_type; + u8 msg_id; + + msg_type = frame[0]; + msg_id = frame[1]; /* seq no */ + frame += 4; + size -= 4; + rsp->type = 0; + + switch (msg_type) { + case WILC_RESP_MSG_TYPE_CONFIG_REPLY: + wilc_wlan_parse_response_frame(wilc, frame, size); + rsp->type = WILC_CFG_RSP; + rsp->seq_no = msg_id; + break; + + case WILC_RESP_MSG_TYPE_STATUS_INFO: + wilc_wlan_parse_info_frame(wilc, frame); + rsp->type = WILC_CFG_RSP_STATUS; + rsp->seq_no = msg_id; + /* call host interface info parse as well */ + wilc_gnrl_async_info_received(wilc, frame - 4, size + 4); + break; + + case WILC_RESP_MSG_TYPE_NETWORK_INFO: + wilc_network_info_received(wilc, frame - 4, size + 4); + break; + + case WILC_RESP_MSG_TYPE_SCAN_COMPLETE: + wilc_scan_complete_received(wilc, frame - 4, size + 4); + break; + + default: + rsp->seq_no = msg_id; + break; + } +} + +int wilc_wlan_cfg_init(struct wilc *wl) +{ + struct wilc_cfg_str_vals *str_vals; + int i = 0; + + wl->cfg.b = kmemdup(g_cfg_byte, sizeof(g_cfg_byte), GFP_KERNEL); + if (!wl->cfg.b) + return -ENOMEM; + + wl->cfg.hw = kmemdup(g_cfg_hword, sizeof(g_cfg_hword), GFP_KERNEL); + if (!wl->cfg.hw) + goto out_b; + + wl->cfg.w = kmemdup(g_cfg_word, sizeof(g_cfg_word), GFP_KERNEL); + if (!wl->cfg.w) + goto out_hw; + + wl->cfg.s = kmemdup(g_cfg_str, sizeof(g_cfg_str), GFP_KERNEL); + if (!wl->cfg.s) + goto out_w; + + str_vals = kzalloc(sizeof(*str_vals), GFP_KERNEL); + if (!str_vals) + goto out_s; + + wl->cfg.str_vals = str_vals; + /* store the string cfg parameters */ + wl->cfg.s[i].id = WID_FIRMWARE_VERSION; + wl->cfg.s[i].str = str_vals->firmware_version; + i++; + wl->cfg.s[i].id = WID_MAC_ADDR; + wl->cfg.s[i].str = str_vals->mac_address; + i++; + wl->cfg.s[i].id = WID_ASSOC_RES_INFO; + wl->cfg.s[i].str = str_vals->assoc_rsp; + i++; + wl->cfg.s[i].id = WID_NIL; + wl->cfg.s[i].str = NULL; + return 0; + +out_s: + kfree(wl->cfg.s); +out_w: + kfree(wl->cfg.w); +out_hw: + kfree(wl->cfg.hw); +out_b: + kfree(wl->cfg.b); + return -ENOMEM; +} + +void wilc_wlan_cfg_deinit(struct wilc *wl) +{ + kfree(wl->cfg.b); + kfree(wl->cfg.hw); + kfree(wl->cfg.w); + kfree(wl->cfg.s); + kfree(wl->cfg.str_vals); +} From patchwork Wed Mar 11 12:18:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CF4DC18E5C for ; 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x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(6666004)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(26005); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 4wxXvjeHc7B1Oc4dBQwFymCSW4rIKfqDp37bEDEFdobOeT7uzjl335+X0DH83JACS+8uPDHJObBolv2Z1NIOaPWqmodLKNURGcYevI6DylB/Rihhnbp0Wuh37HgGKx14CPXX2vKcR14LMr+y6T1HUklqJuljMyRoGSq0d0rMiukAxIQIehUIhm0swFzZZ57f+grdXN7MCxkjmxLso9v8Xzu2bxXltm88F8pKJQkdHQeSFhi5YqUrOTTUcQ8c4/NSAC+zJgwJ1409M9zvR3QRmpCyBvedJAEhUyEgLF+7iU2kvfOBgmVPjlHbtBrqNbM436MnK3XHK3QnnFaMZK5KJ6UqkLyPIJsHSZPw+pBQDW0M9brl+hohDrRig11fAZrO9SYKGtgOhI0mCc6k+KSlPQKK/vV0VQ+PsDM5uC8UJ7ZhKW+tuyLQT2cEJS2acdOV x-ms-exchange-antispam-messagedata: oyh7TjuEdiZgmQ12Gy8gvFTzLdICf3gaFP/+pkNmotA00KPpsmHNrvfmErbXuQGKRiCHnJksATADh6+fvl6PnPWfT8NLhEsamiaDs6ryIZbu1AgVk1n02N9YG95u21XJ5zx6zCWtTSl9kS7z89W5DQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0fb5f593-f19c-40f0-bad3-08d7c5b65ea4 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:45.8135 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oVaeEoChkEdbAWb/L3tuuTCdht0KFGbMhDGKb8WveH33N5Vo/iRLOElK6fBKJ7Q3CvoSvHEeyy6QFJjCB+oJny6ZBJE0Y3hADpYtjMnthmw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/netdev.h' to 'drivers/net/wireless/microchip/wilc1000/netdev.h'. Signed-off-by: Ajay Singh --- .../net/wireless/microchip/wilc1000/netdev.h | 294 ++++++++++++++++++ 1 file changed, 294 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/netdev.h diff --git a/drivers/net/wireless/microchip/wilc1000/netdev.h b/drivers/net/wireless/microchip/wilc1000/netdev.h new file mode 100644 index 000000000000..61cbec674a62 --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/netdev.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#ifndef WILC_NETDEV_H +#define WILC_NETDEV_H + +#include +#include +#include +#include +#include +#include + +#include "hif.h" +#include "wlan.h" +#include "wlan_cfg.h" + +#define FLOW_CONTROL_LOWER_THRESHOLD 128 +#define FLOW_CONTROL_UPPER_THRESHOLD 256 + +#define PMKID_FOUND 1 +#define NUM_STA_ASSOCIATED 8 + +#define NUM_REG_FRAME 2 + +#define TCP_ACK_FILTER_LINK_SPEED_THRESH 54 +#define DEFAULT_LINK_SPEED 72 + +struct wilc_wfi_stats { + unsigned long rx_packets; + unsigned long tx_packets; + unsigned long rx_bytes; + unsigned long tx_bytes; + u64 rx_time; + u64 tx_time; + +}; + +struct wilc_wfi_key { + u8 *key; + u8 *seq; + int key_len; + int seq_len; + u32 cipher; +}; + +struct wilc_wfi_wep_key { + u8 *key; + u8 key_len; + u8 key_idx; +}; + +struct sta_info { + u8 sta_associated_bss[WILC_MAX_NUM_STA][ETH_ALEN]; +}; + +/* Parameters needed for host interface for remaining on channel */ +struct wilc_wfi_p2p_listen_params { + struct ieee80211_channel *listen_ch; + u32 listen_duration; + u64 listen_cookie; +}; + +static const u32 wilc_cipher_suites[] = { + WLAN_CIPHER_SUITE_WEP40, + WLAN_CIPHER_SUITE_WEP104, + WLAN_CIPHER_SUITE_TKIP, + WLAN_CIPHER_SUITE_CCMP, + WLAN_CIPHER_SUITE_AES_CMAC +}; + +#define CHAN2G(_channel, _freq, _flags) { \ + .band = NL80211_BAND_2GHZ, \ + .center_freq = (_freq), \ + .hw_value = (_channel), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ +} + +static const struct ieee80211_channel wilc_2ghz_channels[] = { + CHAN2G(1, 2412, 0), + CHAN2G(2, 2417, 0), + CHAN2G(3, 2422, 0), + CHAN2G(4, 2427, 0), + CHAN2G(5, 2432, 0), + CHAN2G(6, 2437, 0), + CHAN2G(7, 2442, 0), + CHAN2G(8, 2447, 0), + CHAN2G(9, 2452, 0), + CHAN2G(10, 2457, 0), + CHAN2G(11, 2462, 0), + CHAN2G(12, 2467, 0), + CHAN2G(13, 2472, 0), + CHAN2G(14, 2484, 0) +}; + +#define RATETAB_ENT(_rate, _hw_value, _flags) { \ + .bitrate = (_rate), \ + .hw_value = (_hw_value), \ + .flags = (_flags), \ +} + +static struct ieee80211_rate wilc_bitrates[] = { + RATETAB_ENT(10, 0, 0), + RATETAB_ENT(20, 1, 0), + RATETAB_ENT(55, 2, 0), + RATETAB_ENT(110, 3, 0), + RATETAB_ENT(60, 9, 0), + RATETAB_ENT(90, 6, 0), + RATETAB_ENT(120, 7, 0), + RATETAB_ENT(180, 8, 0), + RATETAB_ENT(240, 9, 0), + RATETAB_ENT(360, 10, 0), + RATETAB_ENT(480, 11, 0), + RATETAB_ENT(540, 12, 0) +}; + +struct wilc_priv { + struct wireless_dev wdev; + struct cfg80211_scan_request *scan_req; + + struct wilc_wfi_p2p_listen_params remain_on_ch_params; + u64 tx_cookie; + + bool cfg_scanning; + + u8 associated_bss[ETH_ALEN]; + struct sta_info assoc_stainfo; + struct sk_buff *skb; + struct net_device *dev; + struct host_if_drv *hif_drv; + struct wilc_pmkid_attr pmkid_list; + u8 wep_key[4][WLAN_KEY_LEN_WEP104]; + u8 wep_key_len[4]; + + /* The real interface that the monitor is on */ + struct net_device *real_ndev; + struct wilc_wfi_key *wilc_gtk[WILC_MAX_NUM_STA]; + struct wilc_wfi_key *wilc_ptk[WILC_MAX_NUM_STA]; + u8 wilc_groupkey; + + /* mutexes */ + struct mutex scan_req_lock; + bool p2p_listen_state; + int scanned_cnt; + + u64 inc_roc_cookie; +}; + +struct frame_reg { + u16 type; + bool reg; +}; + +#define MAX_TCP_SESSION 25 +#define MAX_PENDING_ACKS 256 + +struct ack_session_info { + u32 seq_num; + u32 bigger_ack_num; + u16 src_port; + u16 dst_port; + u16 status; +}; + +struct pending_acks { + u32 ack_num; + u32 session_index; + struct txq_entry_t *txqe; +}; + +struct tcp_ack_filter { + struct ack_session_info ack_session_info[2 * MAX_TCP_SESSION]; + struct pending_acks pending_acks[MAX_PENDING_ACKS]; + u32 pending_base; + u32 tcp_session; + u32 pending_acks_idx; + bool enabled; +}; + +struct wilc_vif { + u8 idx; + u8 iftype; + int monitor_flag; + int mac_opened; + struct frame_reg frame_reg[NUM_REG_FRAME]; + struct net_device_stats netstats; + struct wilc *wilc; + u8 bssid[ETH_ALEN]; + struct host_if_drv *hif_drv; + struct net_device *ndev; + u8 mode; + struct timer_list during_ip_timer; + struct timer_list periodic_rssi; + struct rf_info periodic_stat; + struct tcp_ack_filter ack_filter; + bool connecting; + struct wilc_priv priv; + struct list_head list; + struct cfg80211_bss *bss; +}; + +struct wilc { + struct wiphy *wiphy; + const struct wilc_hif_func *hif_func; + int io_type; + s8 mac_status; + struct clk *rtc_clk; + bool initialized; + int dev_irq_num; + int close; + u8 vif_num; + struct list_head vif_list; + + /* protect vif list */ + struct mutex vif_mutex; + struct srcu_struct srcu; + u8 open_ifcs; + + /* protect head of transmit queue */ + struct mutex txq_add_to_head_cs; + + /* protect txq_entry_t transmit queue */ + spinlock_t txq_spinlock; + + /* protect rxq_entry_t receiver queue */ + struct mutex rxq_cs; + + /* lock to protect hif access */ + struct mutex hif_cs; + + struct completion cfg_event; + struct completion sync_event; + struct completion txq_event; + struct completion txq_thread_started; + + struct task_struct *txq_thread; + + int quit; + + /* lock to protect issue of wid command to firmware */ + struct mutex cfg_cmd_lock; + struct wilc_cfg_frame cfg_frame; + u32 cfg_frame_offset; + u8 cfg_seq_no; + + u8 *rx_buffer; + u32 rx_buffer_offset; + u8 *tx_buffer; + + struct txq_entry_t txq_head; + int txq_entries; + + struct rxq_entry_t rxq_head; + + const struct firmware *firmware; + + struct device *dev; + bool suspend_event; + + int clients_count; + struct workqueue_struct *hif_workqueue; + enum chip_ps_states chip_ps_state; + struct wilc_cfg cfg; + void *bus_data; + struct net_device *monitor_dev; + + /* deinit lock */ + struct mutex deinit_lock; + u8 sta_ch; + u8 op_ch; + struct ieee80211_channel channels[ARRAY_SIZE(wilc_2ghz_channels)]; + struct ieee80211_rate bitrates[ARRAY_SIZE(wilc_bitrates)]; + struct ieee80211_supported_band band; + u32 cipher_suites[ARRAY_SIZE(wilc_cipher_suites)]; +}; + +struct wilc_wfi_mon_priv { + struct net_device *real_ndev; +}; + +void wilc_frmw_to_host(struct wilc *wilc, u8 *buff, u32 size, u32 pkt_offset); +void wilc_mac_indicate(struct wilc *wilc); +void wilc_netdev_cleanup(struct wilc *wilc); +void wilc_wfi_mgmt_rx(struct wilc *wilc, u8 *buff, u32 size); +void wilc_wlan_set_bssid(struct net_device *wilc_netdev, u8 *bssid, u8 mode); +struct wilc_vif *wilc_netdev_ifc_init(struct wilc *wl, const char *name, + int vif_type, enum nl80211_iftype type, + bool rtnl_locked); +#endif From patchwork Wed Mar 11 12:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5B6BC2BB8B for ; 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x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(6666004)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(26005); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: wM6GELdp1obpytVFj6ezXVB6ryzCPwJUMO3NyX6JfH5Vuok0sBaDbpmuGpuPHQRF4S5E81JyGpuE9thDpRgK3JAVUEqGwaYUEzt82eQCyP5hH0rqrF/W+EdYbfbyCXQxJNADdmLvNuhlj7iUiKtF2A9sILzd0bwA1deI3jlWSczhBk1OYUMSqogEEHb0ruDvfLAoeBbFfRN9Nmb5cIhbAr7doqe9dGGc1lN5OcKOrtet0SC3rh64H9+9Fr7lMPKHo8wkYuHRjCgYIDcD/8dXiNUAKB6H4rtRNS5MNKdEuc9DseJL+Z1vynb7AnhmBZICIwgUh/4Uc5PE+ERS06AYs+/jexvdnLNs3HonNotUPf7h2cS99XgjZimv2q/wA9SQzgh4VRMUlovYxeG4rj00TB2QbXn8/WGaTGpKwbGylY+LvFOR2l5jP+ZXjaABbObj x-ms-exchange-antispam-messagedata: h0IJAVkClOAvjK9IkVg4qpbRwI8TrVDkxcjKksqFQfSDcDxtPzgbBZP+fHF4MwNTl2ALZ7K3veiMK2ZU+fbAbVIbRoP/RtpvzYXynnwqb9IGam3q5Xww5pHoczzwjvszQxDcE6pkRrXYFIpu/cUXnQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e610eaec-f34d-48ad-c0bb-08d7c5b65f0a X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:47.1508 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0HqgRwXWqhC5oINNKtyOU6gvb1BBtJBnbQi5oqg0kEGyAu+UOpRaPqpx5ip+QhVN/k7Ti3HHukUUWStsr5Jq/xseGJDsFLoDm8cCPWd/TIU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/mon.c' to 'drivers/net/wireless/microchip/wilc1000/mon.c'. Signed-off-by: Ajay Singh --- drivers/net/wireless/microchip/wilc1000/mon.c | 260 ++++++++++++++++++ 1 file changed, 260 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/mon.c diff --git a/drivers/net/wireless/microchip/wilc1000/mon.c b/drivers/net/wireless/microchip/wilc1000/mon.c new file mode 100644 index 000000000000..60331417bd98 --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/mon.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#include "cfg80211.h" + +struct wilc_wfi_radiotap_hdr { + struct ieee80211_radiotap_header hdr; + u8 rate; +} __packed; + +struct wilc_wfi_radiotap_cb_hdr { + struct ieee80211_radiotap_header hdr; + u8 rate; + u8 dump; + u16 tx_flags; +} __packed; + +#define TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_TX_FLAGS)) + +void wilc_wfi_monitor_rx(struct net_device *mon_dev, u8 *buff, u32 size) +{ + u32 header, pkt_offset; + struct sk_buff *skb = NULL; + struct wilc_wfi_radiotap_hdr *hdr; + struct wilc_wfi_radiotap_cb_hdr *cb_hdr; + + if (!mon_dev) + return; + + if (!netif_running(mon_dev)) + return; + + /* Get WILC header */ + header = get_unaligned_le32(buff - HOST_HDR_OFFSET); + /* + * The packet offset field contain info about what type of management + * the frame we are dealing with and ack status + */ + pkt_offset = FIELD_GET(WILC_PKT_HDR_OFFSET_FIELD, header); + + if (pkt_offset & IS_MANAGMEMENT_CALLBACK) { + /* hostapd callback mgmt frame */ + + skb = dev_alloc_skb(size + sizeof(*cb_hdr)); + if (!skb) + return; + + skb_put_data(skb, buff, size); + + cb_hdr = skb_push(skb, sizeof(*cb_hdr)); + memset(cb_hdr, 0, sizeof(*cb_hdr)); + + cb_hdr->hdr.it_version = 0; /* PKTHDR_RADIOTAP_VERSION; */ + + cb_hdr->hdr.it_len = cpu_to_le16(sizeof(*cb_hdr)); + + cb_hdr->hdr.it_present = cpu_to_le32(TX_RADIOTAP_PRESENT); + + cb_hdr->rate = 5; + + if (pkt_offset & IS_MGMT_STATUS_SUCCES) { + /* success */ + cb_hdr->tx_flags = IEEE80211_RADIOTAP_F_TX_RTS; + } else { + cb_hdr->tx_flags = IEEE80211_RADIOTAP_F_TX_FAIL; + } + + } else { + skb = dev_alloc_skb(size + sizeof(*hdr)); + + if (!skb) + return; + + skb_put_data(skb, buff, size); + hdr = skb_push(skb, sizeof(*hdr)); + memset(hdr, 0, sizeof(struct wilc_wfi_radiotap_hdr)); + hdr->hdr.it_version = 0; /* PKTHDR_RADIOTAP_VERSION; */ + hdr->hdr.it_len = cpu_to_le16(sizeof(*hdr)); + hdr->hdr.it_present = cpu_to_le32 + (1 << IEEE80211_RADIOTAP_RATE); + hdr->rate = 5; + } + + skb->dev = mon_dev; + skb_reset_mac_header(skb); + skb->ip_summed = CHECKSUM_UNNECESSARY; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = htons(ETH_P_802_2); + memset(skb->cb, 0, sizeof(skb->cb)); + + netif_rx(skb); +} + +struct tx_complete_mon_data { + int size; + void *buff; +}; + +static void mgmt_tx_complete(void *priv, int status) +{ + struct tx_complete_mon_data *pv_data = priv; + /* + * in case of fully hosting mode, the freeing will be done + * in response to the cfg packet + */ + kfree(pv_data->buff); + + kfree(pv_data); +} + +static int mon_mgmt_tx(struct net_device *dev, const u8 *buf, size_t len) +{ + struct tx_complete_mon_data *mgmt_tx = NULL; + + if (!dev) + return -EFAULT; + + netif_stop_queue(dev); + mgmt_tx = kmalloc(sizeof(*mgmt_tx), GFP_ATOMIC); + if (!mgmt_tx) + return -ENOMEM; + + mgmt_tx->buff = kmemdup(buf, len, GFP_ATOMIC); + if (!mgmt_tx->buff) { + kfree(mgmt_tx); + return -ENOMEM; + } + + mgmt_tx->size = len; + + wilc_wlan_txq_add_mgmt_pkt(dev, mgmt_tx, mgmt_tx->buff, mgmt_tx->size, + mgmt_tx_complete); + + netif_wake_queue(dev); + return 0; +} + +static netdev_tx_t wilc_wfi_mon_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + u32 rtap_len, ret = 0; + struct wilc_wfi_mon_priv *mon_priv; + struct sk_buff *skb2; + struct wilc_wfi_radiotap_cb_hdr *cb_hdr; + u8 srcadd[ETH_ALEN]; + u8 bssid[ETH_ALEN]; + + mon_priv = netdev_priv(dev); + if (!mon_priv) + return -EFAULT; + + rtap_len = ieee80211_get_radiotap_len(skb->data); + if (skb->len < rtap_len) + return -1; + + skb_pull(skb, rtap_len); + + if (skb->data[0] == 0xc0 && is_broadcast_ether_addr(&skb->data[4])) { + skb2 = dev_alloc_skb(skb->len + sizeof(*cb_hdr)); + if (!skb2) + return -ENOMEM; + + skb_put_data(skb2, skb->data, skb->len); + + cb_hdr = skb_push(skb2, sizeof(*cb_hdr)); + memset(cb_hdr, 0, sizeof(struct wilc_wfi_radiotap_cb_hdr)); + + cb_hdr->hdr.it_version = 0; /* PKTHDR_RADIOTAP_VERSION; */ + + cb_hdr->hdr.it_len = cpu_to_le16(sizeof(*cb_hdr)); + + cb_hdr->hdr.it_present = cpu_to_le32(TX_RADIOTAP_PRESENT); + + cb_hdr->rate = 5; + cb_hdr->tx_flags = 0x0004; + + skb2->dev = dev; + skb_reset_mac_header(skb2); + skb2->ip_summed = CHECKSUM_UNNECESSARY; + skb2->pkt_type = PACKET_OTHERHOST; + skb2->protocol = htons(ETH_P_802_2); + memset(skb2->cb, 0, sizeof(skb2->cb)); + + netif_rx(skb2); + + return 0; + } + skb->dev = mon_priv->real_ndev; + + ether_addr_copy(srcadd, &skb->data[10]); + ether_addr_copy(bssid, &skb->data[16]); + /* + * Identify if data or mgmt packet, if source address and bssid + * fields are equal send it to mgmt frames handler + */ + if (!(memcmp(srcadd, bssid, 6))) { + ret = mon_mgmt_tx(mon_priv->real_ndev, skb->data, skb->len); + if (ret) + netdev_err(dev, "fail to mgmt tx\n"); + dev_kfree_skb(skb); + } else { + ret = wilc_mac_xmit(skb, mon_priv->real_ndev); + } + + return ret; +} + +static const struct net_device_ops wilc_wfi_netdev_ops = { + .ndo_start_xmit = wilc_wfi_mon_xmit, + +}; + +struct net_device *wilc_wfi_init_mon_interface(struct wilc *wl, + const char *name, + struct net_device *real_dev) +{ + struct wilc_wfi_mon_priv *priv; + + /* If monitor interface is already initialized, return it */ + if (wl->monitor_dev) + return wl->monitor_dev; + + wl->monitor_dev = alloc_etherdev(sizeof(struct wilc_wfi_mon_priv)); + if (!wl->monitor_dev) + return NULL; + + wl->monitor_dev->type = ARPHRD_IEEE80211_RADIOTAP; + strncpy(wl->monitor_dev->name, name, IFNAMSIZ); + wl->monitor_dev->name[IFNAMSIZ - 1] = 0; + wl->monitor_dev->netdev_ops = &wilc_wfi_netdev_ops; + wl->monitor_dev->needs_free_netdev = true; + + if (register_netdevice(wl->monitor_dev)) { + netdev_err(real_dev, "register_netdevice failed\n"); + return NULL; + } + priv = netdev_priv(wl->monitor_dev); + if (!priv) + return NULL; + + priv->real_ndev = real_dev; + + return wl->monitor_dev; +} + +void wilc_wfi_deinit_mon_interface(struct wilc *wl, bool rtnl_locked) +{ + if (!wl->monitor_dev) + return; + + if (rtnl_locked) + unregister_netdevice(wl->monitor_dev); + else + unregister_netdev(wl->monitor_dev); + wl->monitor_dev = NULL; +} From patchwork Wed Mar 11 12:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C14ACC2BB58 for ; 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x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(6666004)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(30864003)(26005)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 3y9fk2tbtN835vg4bQMlyuKa+ozQcNtwr7U5S7x/YqUk4l8jyToz1b/mCsRfI1epkEfhl1ENfulrjLYNr/E2EKzbOD7j+0YSrkJaDJDBwdbFovTiVf0h2Z5v22DkUTFRvmKHxZFlP+PDi/O2+ps6emV/38pmkhZ7cN47em4196wOd4njEKsNFuw4RQugatOwCc2rCYxRY/X1cv+ra1AADu+UoqANdJRmTJ893jSFKOCcwRHh0IBlNp47padqq9MzBu8pzhtYvRxG8C/jY+F+EY5LwpmX+dj3tax03CjSHU5VZVAL1e5o8V/P2dUrWl0gAeQRdmAMRMhkpENOaEeDxX04o9DdsnO5NB4L1hiqhFx1TgoMdmJrG9rNG5NUPoWChCtiwOz+odm/+83NLA2+kQkn6QiYAF7S9tGhI6FsJQYfhJphhY0/RPScqZi5Ns4J x-ms-exchange-antispam-messagedata: F6eXvHxzcGlNG+326/ybE8EXE133cLdWltsilNrFp3sjEVsidQMl1QFFBWow4Ix98jj5sJZ9khfIIWqLZo7YqOOX4Xz1RJ/w9o+zcykPzsPlmt8pBrqC0BI7MBYd19ZajGNO9e2BmRroOZoI8OSUYg== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: b3c76904-13f0-4fb8-59c9-08d7c5b65f38 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:47.7734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hHQsjmwzvcxRZiUyxEtfq+yUbiLJpK7cUMhj/3RWZMhFWPkRiA1c6F41YAFf0oGNGQcWtiGQ8Sa72zowdUQJzf9j4vvDITzTDZi1gdX7mWU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/spi.c' to 'drivers/net/wireless/microchip/wilc1000/spi.c'. Signed-off-by: Ajay Singh --- drivers/net/wireless/microchip/wilc1000/spi.c | 988 ++++++++++++++++++ 1 file changed, 988 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/spi.c diff --git a/drivers/net/wireless/microchip/wilc1000/spi.c b/drivers/net/wireless/microchip/wilc1000/spi.c new file mode 100644 index 000000000000..d77582c55326 --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/spi.c @@ -0,0 +1,988 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#include +#include + +#include "netdev.h" +#include "cfg80211.h" + +struct wilc_spi { + int crc_off; +}; + +static const struct wilc_hif_func wilc_hif_spi; + +/******************************************** + * + * Crc7 + * + ********************************************/ + +static const u8 crc7_syndrome_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, + 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, + 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, + 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, + 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, + 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, + 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, + 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, + 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, + 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, + 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79 +}; + +static u8 crc7_byte(u8 crc, u8 data) +{ + return crc7_syndrome_table[(crc << 1) ^ data]; +} + +static u8 crc7(u8 crc, const u8 *buffer, u32 len) +{ + while (len--) + crc = crc7_byte(crc, *buffer++); + return crc; +} + +static u8 wilc_get_crc7(u8 *buffer, u32 len) +{ + return crc7(0x7f, (const u8 *)buffer, len) << 1; +} + +/******************************************** + * + * Spi protocol Function + * + ********************************************/ + +#define CMD_DMA_WRITE 0xc1 +#define CMD_DMA_READ 0xc2 +#define CMD_INTERNAL_WRITE 0xc3 +#define CMD_INTERNAL_READ 0xc4 +#define CMD_TERMINATE 0xc5 +#define CMD_REPEAT 0xc6 +#define CMD_DMA_EXT_WRITE 0xc7 +#define CMD_DMA_EXT_READ 0xc8 +#define CMD_SINGLE_WRITE 0xc9 +#define CMD_SINGLE_READ 0xca +#define CMD_RESET 0xcf + +#define DATA_PKT_SZ_256 256 +#define DATA_PKT_SZ_512 512 +#define DATA_PKT_SZ_1K 1024 +#define DATA_PKT_SZ_4K (4 * 1024) +#define DATA_PKT_SZ_8K (8 * 1024) +#define DATA_PKT_SZ DATA_PKT_SZ_8K + +#define USE_SPI_DMA 0 + +#define WILC_SPI_COMMAND_STAT_SUCCESS 0 +#define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) + +struct wilc_spi_cmd { + u8 cmd_type; + union { + struct { + u8 addr[3]; + u8 crc[]; + } __packed simple_cmd; + struct { + u8 addr[3]; + u8 size[2]; + u8 crc[]; + } __packed dma_cmd; + struct { + u8 addr[3]; + u8 size[3]; + u8 crc[]; + } __packed dma_cmd_ext; + struct { + u8 addr[2]; + __be32 data; + u8 crc[]; + } __packed internal_w_cmd; + struct { + u8 addr[3]; + __be32 data; + u8 crc[]; + } __packed w_cmd; + } u; +} __packed; + +struct wilc_spi_read_rsp_data { + u8 rsp_cmd_type; + u8 status; + u8 resp_header; + u8 resp_data[4]; + u8 crc[]; +} __packed; + +struct wilc_spi_rsp_data { + u8 rsp_cmd_type; + u8 status; +} __packed; + +static int wilc_bus_probe(struct spi_device *spi) +{ + int ret; + struct wilc *wilc; + struct wilc_spi *spi_priv; + + spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); + if (!spi_priv) + return -ENOMEM; + + ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); + if (ret) { + kfree(spi_priv); + return ret; + } + + spi_set_drvdata(spi, wilc); + wilc->dev = &spi->dev; + wilc->bus_data = spi_priv; + wilc->dev_irq_num = spi->irq; + + wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk"); + if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + else if (!IS_ERR(wilc->rtc_clk)) + clk_prepare_enable(wilc->rtc_clk); + + return 0; +} + +static int wilc_bus_remove(struct spi_device *spi) +{ + struct wilc *wilc = spi_get_drvdata(spi); + + if (!IS_ERR(wilc->rtc_clk)) + clk_disable_unprepare(wilc->rtc_clk); + + wilc_netdev_cleanup(wilc); + return 0; +} + +static const struct of_device_id wilc_of_match[] = { + { .compatible = "microchip,wilc1000", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, wilc_of_match); + +static struct spi_driver wilc_spi_driver = { + .driver = { + .name = MODALIAS, + .of_match_table = wilc_of_match, + }, + .probe = wilc_bus_probe, + .remove = wilc_bus_remove, +}; +module_spi_driver(wilc_spi_driver); +MODULE_LICENSE("GPL"); + +static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int ret; + struct spi_message msg; + + if (len > 0 && b) { + struct spi_transfer tr = { + .tx_buf = b, + .len = len, + .delay_usecs = 0, + }; + char *r_buffer = kzalloc(len, GFP_KERNEL); + + if (!r_buffer) + return -ENOMEM; + + tr.rx_buf = r_buffer; + dev_dbg(&spi->dev, "Request writing %d bytes\n", len); + + memset(&msg, 0, sizeof(msg)); + spi_message_init(&msg); + msg.spi = spi; + msg.is_dma_mapped = USE_SPI_DMA; + spi_message_add_tail(&tr, &msg); + + ret = spi_sync(spi, &msg); + if (ret < 0) + dev_err(&spi->dev, "SPI transaction failed\n"); + + kfree(r_buffer); + } else { + dev_err(&spi->dev, + "can't write data with the following length: %d\n", + len); + ret = -EINVAL; + } + + return ret; +} + +static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int ret; + + if (rlen > 0) { + struct spi_message msg; + struct spi_transfer tr = { + .rx_buf = rb, + .len = rlen, + .delay_usecs = 0, + + }; + char *t_buffer = kzalloc(rlen, GFP_KERNEL); + + if (!t_buffer) + return -ENOMEM; + + tr.tx_buf = t_buffer; + + memset(&msg, 0, sizeof(msg)); + spi_message_init(&msg); + msg.spi = spi; + msg.is_dma_mapped = USE_SPI_DMA; + spi_message_add_tail(&tr, &msg); + + ret = spi_sync(spi, &msg); + if (ret < 0) + dev_err(&spi->dev, "SPI transaction failed\n"); + kfree(t_buffer); + } else { + dev_err(&spi->dev, + "can't read data with the following length: %u\n", + rlen); + ret = -EINVAL; + } + + return ret; +} + +static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int ret; + + if (rlen > 0) { + struct spi_message msg; + struct spi_transfer tr = { + .rx_buf = rb, + .tx_buf = wb, + .len = rlen, + .bits_per_word = 8, + .delay_usecs = 0, + + }; + + memset(&msg, 0, sizeof(msg)); + spi_message_init(&msg); + msg.spi = spi; + msg.is_dma_mapped = USE_SPI_DMA; + + spi_message_add_tail(&tr, &msg); + ret = spi_sync(spi, &msg); + if (ret < 0) + dev_err(&spi->dev, "SPI transaction failed\n"); + } else { + dev_err(&spi->dev, + "can't read data with the following length: %u\n", + rlen); + ret = -EINVAL; + } + + return ret; +} + +static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + struct wilc_spi *spi_priv = wilc->bus_data; + int ix, nbytes; + int result = 0; + u8 cmd, order, crc[2] = {0}; + + /* + * Data + */ + ix = 0; + do { + if (sz <= DATA_PKT_SZ) { + nbytes = sz; + order = 0x3; + } else { + nbytes = DATA_PKT_SZ; + if (ix == 0) + order = 0x1; + else + order = 0x02; + } + + /* + * Write command + */ + cmd = 0xf0; + cmd |= order; + + if (wilc_spi_tx(wilc, &cmd, 1)) { + dev_err(&spi->dev, + "Failed data block cmd write, bus error...\n"); + result = -EINVAL; + break; + } + + /* + * Write data + */ + if (wilc_spi_tx(wilc, &b[ix], nbytes)) { + dev_err(&spi->dev, + "Failed data block write, bus error...\n"); + result = -EINVAL; + break; + } + + /* + * Write Crc + */ + if (!spi_priv->crc_off) { + if (wilc_spi_tx(wilc, crc, 2)) { + dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); + result = -EINVAL; + break; + } + } + + /* + * No need to wait for response + */ + ix += nbytes; + sz -= nbytes; + } while (sz); + + return result; +} + +/******************************************** + * + * Spi Internal Read/Write Function + * + ********************************************/ +static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, + u8 clockless) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + struct wilc_spi *spi_priv = wilc->bus_data; + u8 wb[32], rb[32]; + int cmd_len, resp_len; + u8 crc[2]; + struct wilc_spi_cmd *c; + struct wilc_spi_read_rsp_data *r; + + memset(wb, 0x0, sizeof(wb)); + memset(rb, 0x0, sizeof(rb)); + c = (struct wilc_spi_cmd *)wb; + c->cmd_type = cmd; + if (cmd == CMD_SINGLE_READ) { + c->u.simple_cmd.addr[0] = adr >> 16; + c->u.simple_cmd.addr[1] = adr >> 8; + c->u.simple_cmd.addr[2] = adr; + } else if (cmd == CMD_INTERNAL_READ) { + c->u.simple_cmd.addr[0] = adr >> 8; + if (clockless == 1) + c->u.simple_cmd.addr[0] |= BIT(7); + c->u.simple_cmd.addr[1] = adr; + c->u.simple_cmd.addr[2] = 0x0; + } else { + dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); + return -EINVAL; + } + + cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); + resp_len = sizeof(*r); + if (!spi_priv->crc_off) { + c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); + cmd_len += 1; + resp_len += 2; + } + + if (cmd_len + resp_len > ARRAY_SIZE(wb)) { + dev_err(&spi->dev, + "spi buffer size too small (%d) (%d) (%zu)\n", + cmd_len, resp_len, ARRAY_SIZE(wb)); + return -EINVAL; + } + + if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { + dev_err(&spi->dev, "Failed cmd write, bus error...\n"); + return -EINVAL; + } + + r = (struct wilc_spi_read_rsp_data *)&rb[cmd_len]; + if (r->rsp_cmd_type != cmd) { + dev_err(&spi->dev, + "Failed cmd response, cmd (%02x), resp (%02x)\n", + cmd, r->rsp_cmd_type); + return -EINVAL; + } + + if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { + dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", + r->status); + return -EINVAL; + } + + if (WILC_GET_RESP_HDR_START(r->resp_header) != 0xf) { + dev_err(&spi->dev, "Error, data read response (%02x)\n", + r->resp_header); + return -EINVAL; + } + + if (b) + memcpy(b, r->resp_data, 4); + + if (!spi_priv->crc_off) + memcpy(crc, r->crc, 2); + + return 0; +} + +static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, + u8 clockless) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + struct wilc_spi *spi_priv = wilc->bus_data; + u8 wb[32], rb[32]; + int cmd_len, resp_len; + struct wilc_spi_cmd *c; + struct wilc_spi_rsp_data *r; + + memset(wb, 0x0, sizeof(wb)); + memset(rb, 0x0, sizeof(rb)); + c = (struct wilc_spi_cmd *)wb; + c->cmd_type = cmd; + if (cmd == CMD_INTERNAL_WRITE) { + c->u.internal_w_cmd.addr[0] = adr >> 8; + if (clockless == 1) + c->u.internal_w_cmd.addr[0] |= BIT(7); + + c->u.internal_w_cmd.addr[1] = adr; + c->u.internal_w_cmd.data = cpu_to_be32(data); + cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); + if (!spi_priv->crc_off) + c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); + } else if (cmd == CMD_SINGLE_WRITE) { + c->u.w_cmd.addr[0] = adr >> 16; + c->u.w_cmd.addr[1] = adr >> 8; + c->u.w_cmd.addr[2] = adr; + c->u.w_cmd.data = cpu_to_be32(data); + cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); + if (!spi_priv->crc_off) + c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); + } else { + dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); + return -EINVAL; + } + + if (!spi_priv->crc_off) + cmd_len += 1; + + resp_len = sizeof(*r); + + if (cmd_len + resp_len > ARRAY_SIZE(wb)) { + dev_err(&spi->dev, + "spi buffer size too small (%d) (%d) (%zu)\n", + cmd_len, resp_len, ARRAY_SIZE(wb)); + return -EINVAL; + } + + if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { + dev_err(&spi->dev, "Failed cmd write, bus error...\n"); + return -EINVAL; + } + + r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; + if (r->rsp_cmd_type != cmd) { + dev_err(&spi->dev, + "Failed cmd response, cmd (%02x), resp (%02x)\n", + cmd, r->rsp_cmd_type); + return -EINVAL; + } + + if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { + dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", + r->status); + return -EINVAL; + } + + return 0; +} + +static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + struct wilc_spi *spi_priv = wilc->bus_data; + u8 wb[32], rb[32]; + int cmd_len, resp_len; + int retry, ix = 0; + u8 crc[2]; + struct wilc_spi_cmd *c; + struct wilc_spi_rsp_data *r; + + memset(wb, 0x0, sizeof(wb)); + memset(rb, 0x0, sizeof(rb)); + c = (struct wilc_spi_cmd *)wb; + c->cmd_type = cmd; + if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { + c->u.dma_cmd.addr[0] = adr >> 16; + c->u.dma_cmd.addr[1] = adr >> 8; + c->u.dma_cmd.addr[2] = adr; + c->u.dma_cmd.size[0] = sz >> 8; + c->u.dma_cmd.size[1] = sz; + cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); + if (!spi_priv->crc_off) + c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); + } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { + c->u.dma_cmd_ext.addr[0] = adr >> 16; + c->u.dma_cmd_ext.addr[1] = adr >> 8; + c->u.dma_cmd_ext.addr[2] = adr; + c->u.dma_cmd_ext.size[0] = sz >> 16; + c->u.dma_cmd_ext.size[1] = sz >> 8; + c->u.dma_cmd_ext.size[2] = sz; + cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); + if (!spi_priv->crc_off) + c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); + } else { + dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", + cmd); + return -EINVAL; + } + if (!spi_priv->crc_off) + cmd_len += 1; + + resp_len = sizeof(*r); + + if (cmd_len + resp_len > ARRAY_SIZE(wb)) { + dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", + cmd_len, resp_len, ARRAY_SIZE(wb)); + return -EINVAL; + } + + if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { + dev_err(&spi->dev, "Failed cmd write, bus error...\n"); + return -EINVAL; + } + + r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; + if (r->rsp_cmd_type != cmd) { + dev_err(&spi->dev, + "Failed cmd response, cmd (%02x), resp (%02x)\n", + cmd, r->rsp_cmd_type); + return -EINVAL; + } + + if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { + dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", + r->status); + return -EINVAL; + } + + if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) + return 0; + + while (sz > 0) { + int nbytes; + u8 rsp; + + if (sz <= DATA_PKT_SZ) + nbytes = sz; + else + nbytes = DATA_PKT_SZ; + + /* + * Data Response header + */ + retry = 100; + do { + if (wilc_spi_rx(wilc, &rsp, 1)) { + dev_err(&spi->dev, + "Failed resp read, bus err\n"); + return -EINVAL; + } + if (WILC_GET_RESP_HDR_START(rsp) == 0xf) + break; + } while (retry--); + + /* + * Read bytes + */ + if (wilc_spi_rx(wilc, &b[ix], nbytes)) { + dev_err(&spi->dev, + "Failed block read, bus err\n"); + return -EINVAL; + } + + /* + * Read Crc + */ + if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) { + dev_err(&spi->dev, + "Failed block crc read, bus err\n"); + return -EINVAL; + } + + ix += nbytes; + sz -= nbytes; + } + return 0; +} + +static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + u8 cmd = CMD_SINGLE_READ; + u8 clockless = 0; + + if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { + /* Clockless register */ + cmd = CMD_INTERNAL_READ; + clockless = 1; + } + + result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); + if (result) { + dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); + return result; + } + + le32_to_cpus(data); + + return 0; +} + +static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + + if (size <= 4) + return -EINVAL; + + result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size); + if (result) { + dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); + return result; + } + + return 0; +} + +static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + + result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0); + if (result) { + dev_err(&spi->dev, "Failed internal write cmd...\n"); + return result; + } + + return 0; +} + +static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + + result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0); + if (result) { + dev_err(&spi->dev, "Failed internal read cmd...\n"); + return result; + } + + le32_to_cpus(data); + + return 0; +} + +/******************************************** + * + * Spi interfaces + * + ********************************************/ + +static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + u8 cmd = CMD_SINGLE_WRITE; + u8 clockless = 0; + + if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { + /* Clockless register */ + cmd = CMD_INTERNAL_WRITE; + clockless = 1; + } + + result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); + if (result) { + dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); + return result; + } + + return 0; +} + +static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + int result; + + /* + * has to be greated than 4 + */ + if (size <= 4) + return -EINVAL; + + result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size); + if (result) { + dev_err(&spi->dev, + "Failed cmd, write block (%08x)...\n", addr); + return result; + } + + /* + * Data + */ + result = spi_data_write(wilc, buf, size); + if (result) { + dev_err(&spi->dev, "Failed block data write...\n"); + return result; + } + + return 0; +} + +/******************************************** + * + * Bus interfaces + * + ********************************************/ + +static int wilc_spi_deinit(struct wilc *wilc) +{ + /* + * TODO: + */ + return 0; +} + +static int wilc_spi_init(struct wilc *wilc, bool resume) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + struct wilc_spi *spi_priv = wilc->bus_data; + u32 reg; + u32 chipid; + static int isinit; + int ret; + + if (isinit) { + ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); + if (ret) + dev_err(&spi->dev, "Fail cmd read chip id...\n"); + + return ret; + } + + /* + * configure protocol + */ + + /* + * TODO: We can remove the CRC trials if there is a definite + * way to reset + */ + /* the SPI to it's initial value. */ + ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); + if (ret) { + /* + * Read failed. Try with CRC off. This might happen when module + * is removed but chip isn't reset + */ + spi_priv->crc_off = 1; + dev_err(&spi->dev, + "Failed read with CRC on, retrying with CRC off\n"); + ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); + if (ret) { + /* + * Read failed with both CRC on and off, + * something went bad + */ + dev_err(&spi->dev, "Failed internal read protocol\n"); + return ret; + } + } + if (spi_priv->crc_off == 0) { + reg &= ~0xc; /* disable crc checking */ + reg &= ~0x70; + reg |= (0x5 << 4); + ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); + if (ret) { + dev_err(&spi->dev, + "[wilc spi %d]: Failed internal write reg\n", + __LINE__); + return ret; + } + spi_priv->crc_off = 1; + } + + /* + * make sure can read back chip id correctly + */ + ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); + if (ret) { + dev_err(&spi->dev, "Fail cmd read chip id...\n"); + return ret; + } + + isinit = 1; + + return 0; +} + +static int wilc_spi_read_size(struct wilc *wilc, u32 *size) +{ + int ret; + + ret = spi_internal_read(wilc, + WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); + *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); + + return ret; +} + +static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) +{ + return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, + int_status); +} + +static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) +{ + return spi_internal_write(wilc, WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, + val); +} + +static int wilc_spi_sync_ext(struct wilc *wilc, int nint) +{ + struct spi_device *spi = to_spi_device(wilc->dev); + u32 reg; + int ret, i; + + if (nint > MAX_NUM_INT) { + dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); + return -EINVAL; + } + + /* + * interrupt pin mux select + */ + ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); + if (ret) { + dev_err(&spi->dev, "Failed read reg (%08x)...\n", + WILC_PIN_MUX_0); + return ret; + } + reg |= BIT(8); + ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); + if (ret) { + dev_err(&spi->dev, "Failed write reg (%08x)...\n", + WILC_PIN_MUX_0); + return ret; + } + + /* + * interrupt enable + */ + ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); + if (ret) { + dev_err(&spi->dev, "Failed read reg (%08x)...\n", + WILC_INTR_ENABLE); + return ret; + } + + for (i = 0; (i < 5) && (nint > 0); i++, nint--) + reg |= (BIT((27 + i))); + + ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); + if (ret) { + dev_err(&spi->dev, "Failed write reg (%08x)...\n", + WILC_INTR_ENABLE); + return ret; + } + if (nint) { + ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); + if (ret) { + dev_err(&spi->dev, "Failed read reg (%08x)...\n", + WILC_INTR2_ENABLE); + return ret; + } + + for (i = 0; (i < 3) && (nint > 0); i++, nint--) + reg |= BIT(i); + + ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); + if (ret) { + dev_err(&spi->dev, "Failed write reg (%08x)...\n", + WILC_INTR2_ENABLE); + return ret; + } + } + + return 0; +} + +/* Global spi HIF function table */ +static const struct wilc_hif_func wilc_hif_spi = { + .hif_init = wilc_spi_init, + .hif_deinit = wilc_spi_deinit, + .hif_read_reg = wilc_spi_read_reg, + .hif_write_reg = wilc_spi_write_reg, + .hif_block_rx = wilc_spi_read, + .hif_block_tx = wilc_spi_write, + .hif_read_int = wilc_spi_read_int, + .hif_clear_int_ext = wilc_spi_clear_int_ext, + .hif_read_size = wilc_spi_read_size, + .hif_block_tx_ext = wilc_spi_write, + .hif_block_rx_ext = wilc_spi_read, + .hif_sync_ext = wilc_spi_sync_ext, +}; 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Wed, 11 Mar 2020 12:19:25 +0000 From: To: CC: , , , , , , , , Subject: [PATCH v5 13/17] wilc1000: add wlan.c Thread-Topic: [PATCH v5 13/17] wilc1000: add wlan.c Thread-Index: AQHV95842cWP9H0JDUOoDaFgJZs0Ng== Date: Wed, 11 Mar 2020 12:18:49 +0000 Message-ID: <20200311121809.5610-14-ajay.kathat@microchip.com> References: <20200311121809.5610-1-ajay.kathat@microchip.com> In-Reply-To: <20200311121809.5610-1-ajay.kathat@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [121.244.27.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 38dd4b81-8467-4925-1e62-08d7c5b67038 x-ms-traffictypediagnostic: BYAPR11MB2805: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:15; x-forefront-prvs: 0339F89554 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(376002)(136003)(346002)(396003)(366004)(199004)(478600001)(2906002)(71200400001)(8936002)(81166006)(81156014)(6666004)(316002)(5660300002)(54906003)(6506007)(1076003)(8676002)(6512007)(86362001)(36756003)(107886003)(4326008)(6486002)(76116006)(91956017)(66476007)(64756008)(66446008)(66946007)(66556008)(6916009)(2616005)(186003)(30864003)(26005)(579004)(559001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR11MB2805; H:BYAPR11MB3125.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: v9TBkRIz+DJ2hYQgiz0ejQScOYQoY3d2csLy/GKj4FPUfUo+z03vk3iVle9wrBtp6ztsP6zceJafLZFAVrFHtD7/tkGEW8Eoia4YETTOrVtiCYDKtblbQxEqEGU3ln+5jODSSygutA+M9QKYqhjm9h6kTaTFAEQzYhuBaTKN/xP20K1EUIb6DT819mIqJqwhULJKJFz7/6QS5U2G78DDzvXGZEDmqRJLZjNY0hQU9t0wxh6sr5skG2szJEGKc2+r8vgaqgBxP7Q0RkNqR3nKWRst3pjNYrBGI2whRo5VMeYfPDhsPvQ+jmhEOCiuh/b8lG2vq0AUw4ROaQH8LSI6f2mZYst4SjtkOU15++2t+2S8ohI4yGjEC3DYsW2UDJx7He14Bd8Z1PoJ2eK3JfQ/EstbEGkqtxxrBmuqkkF9e4rAqJGcQzIrBAHSTe638n2h x-ms-exchange-antispam-messagedata: zitc4UgfzfYMjKAokOc7yU6z87hA73bj92EIt7e+hVfpy2nZ7O2A7hxC5zSa75hEfnTjchpgBePuDcGgP3/mWpP7nX2PcXgah0WllnLr+q8A6y9lai8TEniSzrpt8C5F6h/pRPPn2+hTMYXDhnmKkQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 38dd4b81-8467-4925-1e62-08d7c5b67038 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2020 12:18:49.0187 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /kmcqano7wnnsKSjC9e4f78+QSC5jKVbOKDL1imwNrWDhUE6gOvhhRYlBxA6oMSiUnDqxy8qdr0O62hJdOAUsfCQU2IgB0g5nfw+K2pYMWY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2805 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ajay Singh Moved 'drivers/staging/wilc1000/wlan.c' to 'drivers/net/wireless/microchip/wilc1000/wlan.c'. Signed-off-by: Ajay Singh --- .../net/wireless/microchip/wilc1000/wlan.c | 1238 +++++++++++++++++ 1 file changed, 1238 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/wlan.c diff --git a/drivers/net/wireless/microchip/wilc1000/wlan.c b/drivers/net/wireless/microchip/wilc1000/wlan.c new file mode 100644 index 000000000000..6a82fb2f283e --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/wlan.c @@ -0,0 +1,1238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#include +#include +#include "cfg80211.h" +#include "wlan_cfg.h" + +static inline bool is_wilc1000(u32 id) +{ + return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID; +} + +static inline void acquire_bus(struct wilc *wilc, enum bus_acquire acquire) +{ + mutex_lock(&wilc->hif_cs); + if (acquire == WILC_BUS_ACQUIRE_AND_WAKEUP) + chip_wakeup(wilc); +} + +static inline void release_bus(struct wilc *wilc, enum bus_release release) +{ + if (release == WILC_BUS_RELEASE_ALLOW_SLEEP) + chip_allow_sleep(wilc); + mutex_unlock(&wilc->hif_cs); +} + +static void wilc_wlan_txq_remove(struct wilc *wilc, struct txq_entry_t *tqe) +{ + list_del(&tqe->list); + wilc->txq_entries -= 1; +} + +static struct txq_entry_t * +wilc_wlan_txq_remove_from_head(struct net_device *dev) +{ + struct txq_entry_t *tqe = NULL; + unsigned long flags; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + if (!list_empty(&wilc->txq_head.list)) { + tqe = list_first_entry(&wilc->txq_head.list, struct txq_entry_t, + list); + list_del(&tqe->list); + wilc->txq_entries -= 1; + } + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + return tqe; +} + +static void wilc_wlan_txq_add_to_tail(struct net_device *dev, + struct txq_entry_t *tqe) +{ + unsigned long flags; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + list_add_tail(&tqe->list, &wilc->txq_head.list); + wilc->txq_entries += 1; + + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + + complete(&wilc->txq_event); +} + +static void wilc_wlan_txq_add_to_head(struct wilc_vif *vif, + struct txq_entry_t *tqe) +{ + unsigned long flags; + struct wilc *wilc = vif->wilc; + + mutex_lock(&wilc->txq_add_to_head_cs); + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + list_add(&tqe->list, &wilc->txq_head.list); + wilc->txq_entries += 1; + + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + mutex_unlock(&wilc->txq_add_to_head_cs); + complete(&wilc->txq_event); +} + +#define NOT_TCP_ACK (-1) + +static inline void add_tcp_session(struct wilc_vif *vif, u32 src_prt, + u32 dst_prt, u32 seq) +{ + struct tcp_ack_filter *f = &vif->ack_filter; + + if (f->tcp_session < 2 * MAX_TCP_SESSION) { + f->ack_session_info[f->tcp_session].seq_num = seq; + f->ack_session_info[f->tcp_session].bigger_ack_num = 0; + f->ack_session_info[f->tcp_session].src_port = src_prt; + f->ack_session_info[f->tcp_session].dst_port = dst_prt; + f->tcp_session++; + } +} + +static inline void update_tcp_session(struct wilc_vif *vif, u32 index, u32 ack) +{ + struct tcp_ack_filter *f = &vif->ack_filter; + + if (index < 2 * MAX_TCP_SESSION && + ack > f->ack_session_info[index].bigger_ack_num) + f->ack_session_info[index].bigger_ack_num = ack; +} + +static inline void add_tcp_pending_ack(struct wilc_vif *vif, u32 ack, + u32 session_index, + struct txq_entry_t *txqe) +{ + struct tcp_ack_filter *f = &vif->ack_filter; + u32 i = f->pending_base + f->pending_acks_idx; + + if (i < MAX_PENDING_ACKS) { + f->pending_acks[i].ack_num = ack; + f->pending_acks[i].txqe = txqe; + f->pending_acks[i].session_index = session_index; + txqe->ack_idx = i; + f->pending_acks_idx++; + } +} + +static inline void tcp_process(struct net_device *dev, struct txq_entry_t *tqe) +{ + void *buffer = tqe->buffer; + const struct ethhdr *eth_hdr_ptr = buffer; + int i; + unsigned long flags; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + struct tcp_ack_filter *f = &vif->ack_filter; + const struct iphdr *ip_hdr_ptr; + const struct tcphdr *tcp_hdr_ptr; + u32 ihl, total_length, data_offset; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + if (eth_hdr_ptr->h_proto != htons(ETH_P_IP)) + goto out; + + ip_hdr_ptr = buffer + ETH_HLEN; + + if (ip_hdr_ptr->protocol != IPPROTO_TCP) + goto out; + + ihl = ip_hdr_ptr->ihl << 2; + tcp_hdr_ptr = buffer + ETH_HLEN + ihl; + total_length = ntohs(ip_hdr_ptr->tot_len); + + data_offset = tcp_hdr_ptr->doff << 2; + if (total_length == (ihl + data_offset)) { + u32 seq_no, ack_no; + + seq_no = ntohl(tcp_hdr_ptr->seq); + ack_no = ntohl(tcp_hdr_ptr->ack_seq); + for (i = 0; i < f->tcp_session; i++) { + u32 j = f->ack_session_info[i].seq_num; + + if (i < 2 * MAX_TCP_SESSION && + j == seq_no) { + update_tcp_session(vif, i, ack_no); + break; + } + } + if (i == f->tcp_session) + add_tcp_session(vif, 0, 0, seq_no); + + add_tcp_pending_ack(vif, ack_no, i, tqe); + } + +out: + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); +} + +static void wilc_wlan_txq_filter_dup_tcp_ack(struct net_device *dev) +{ + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + struct tcp_ack_filter *f = &vif->ack_filter; + u32 i = 0; + u32 dropped = 0; + unsigned long flags; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + for (i = f->pending_base; + i < (f->pending_base + f->pending_acks_idx); i++) { + u32 index; + u32 bigger_ack_num; + + if (i >= MAX_PENDING_ACKS) + break; + + index = f->pending_acks[i].session_index; + + if (index >= 2 * MAX_TCP_SESSION) + break; + + bigger_ack_num = f->ack_session_info[index].bigger_ack_num; + + if (f->pending_acks[i].ack_num < bigger_ack_num) { + struct txq_entry_t *tqe; + + tqe = f->pending_acks[i].txqe; + if (tqe) { + wilc_wlan_txq_remove(wilc, tqe); + tqe->status = 1; + if (tqe->tx_complete_func) + tqe->tx_complete_func(tqe->priv, + tqe->status); + kfree(tqe); + dropped++; + } + } + } + f->pending_acks_idx = 0; + f->tcp_session = 0; + + if (f->pending_base == 0) + f->pending_base = MAX_TCP_SESSION; + else + f->pending_base = 0; + + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + + while (dropped > 0) { + wait_for_completion_timeout(&wilc->txq_event, + msecs_to_jiffies(1)); + dropped--; + } +} + +void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value) +{ + vif->ack_filter.enabled = value; +} + +static int wilc_wlan_txq_add_cfg_pkt(struct wilc_vif *vif, u8 *buffer, + u32 buffer_size) +{ + struct txq_entry_t *tqe; + struct wilc *wilc = vif->wilc; + + netdev_dbg(vif->ndev, "Adding config packet ...\n"); + if (wilc->quit) { + netdev_dbg(vif->ndev, "Return due to clear function\n"); + complete(&wilc->cfg_event); + return 0; + } + + tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); + if (!tqe) + return 0; + + tqe->type = WILC_CFG_PKT; + tqe->buffer = buffer; + tqe->buffer_size = buffer_size; + tqe->tx_complete_func = NULL; + tqe->priv = NULL; + tqe->ack_idx = NOT_TCP_ACK; + tqe->vif = vif; + + wilc_wlan_txq_add_to_head(vif, tqe); + + return 1; +} + +int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer, + u32 buffer_size, + void (*tx_complete_fn)(void *, int)) +{ + struct txq_entry_t *tqe; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc; + + wilc = vif->wilc; + + if (wilc->quit) + return 0; + + tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); + + if (!tqe) + return 0; + tqe->type = WILC_NET_PKT; + tqe->buffer = buffer; + tqe->buffer_size = buffer_size; + tqe->tx_complete_func = tx_complete_fn; + tqe->priv = priv; + tqe->vif = vif; + + tqe->ack_idx = NOT_TCP_ACK; + if (vif->ack_filter.enabled) + tcp_process(dev, tqe); + wilc_wlan_txq_add_to_tail(dev, tqe); + return wilc->txq_entries; +} + +int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer, + u32 buffer_size, + void (*tx_complete_fn)(void *, int)) +{ + struct txq_entry_t *tqe; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc; + + wilc = vif->wilc; + + if (wilc->quit) + return 0; + + tqe = kmalloc(sizeof(*tqe), GFP_ATOMIC); + + if (!tqe) + return 0; + tqe->type = WILC_MGMT_PKT; + tqe->buffer = buffer; + tqe->buffer_size = buffer_size; + tqe->tx_complete_func = tx_complete_fn; + tqe->priv = priv; + tqe->ack_idx = NOT_TCP_ACK; + tqe->vif = vif; + wilc_wlan_txq_add_to_tail(dev, tqe); + return 1; +} + +static struct txq_entry_t *wilc_wlan_txq_get_first(struct wilc *wilc) +{ + struct txq_entry_t *tqe = NULL; + unsigned long flags; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + if (!list_empty(&wilc->txq_head.list)) + tqe = list_first_entry(&wilc->txq_head.list, struct txq_entry_t, + list); + + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + + return tqe; +} + +static struct txq_entry_t *wilc_wlan_txq_get_next(struct wilc *wilc, + struct txq_entry_t *tqe) +{ + unsigned long flags; + + spin_lock_irqsave(&wilc->txq_spinlock, flags); + + if (!list_is_last(&tqe->list, &wilc->txq_head.list)) + tqe = list_next_entry(tqe, list); + else + tqe = NULL; + spin_unlock_irqrestore(&wilc->txq_spinlock, flags); + + return tqe; +} + +static void wilc_wlan_rxq_add(struct wilc *wilc, struct rxq_entry_t *rqe) +{ + if (wilc->quit) + return; + + mutex_lock(&wilc->rxq_cs); + list_add_tail(&rqe->list, &wilc->rxq_head.list); + mutex_unlock(&wilc->rxq_cs); +} + +static struct rxq_entry_t *wilc_wlan_rxq_remove(struct wilc *wilc) +{ + struct rxq_entry_t *rqe = NULL; + + mutex_lock(&wilc->rxq_cs); + if (!list_empty(&wilc->rxq_head.list)) { + rqe = list_first_entry(&wilc->rxq_head.list, struct rxq_entry_t, + list); + list_del(&rqe->list); + } + mutex_unlock(&wilc->rxq_cs); + return rqe; +} + +void chip_allow_sleep(struct wilc *wilc) +{ + u32 reg = 0; + + wilc->hif_func->hif_read_reg(wilc, WILC_SDIO_WAKEUP_REG, ®); + + wilc->hif_func->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg & ~WILC_SDIO_WAKEUP_BIT); + wilc->hif_func->hif_write_reg(wilc, WILC_SDIO_HOST_TO_FW_REG, 0); +} +EXPORT_SYMBOL_GPL(chip_allow_sleep); + +void chip_wakeup(struct wilc *wilc) +{ + u32 reg, clk_status_reg; + const struct wilc_hif_func *h = wilc->hif_func; + + if (wilc->io_type == WILC_HIF_SPI) { + do { + h->hif_read_reg(wilc, WILC_SPI_WAKEUP_REG, ®); + h->hif_write_reg(wilc, WILC_SPI_WAKEUP_REG, + reg | WILC_SPI_WAKEUP_BIT); + h->hif_write_reg(wilc, WILC_SPI_WAKEUP_REG, + reg & ~WILC_SPI_WAKEUP_BIT); + + do { + usleep_range(2000, 2500); + wilc_get_chipid(wilc, true); + } while (wilc_get_chipid(wilc, true) == 0); + } while (wilc_get_chipid(wilc, true) == 0); + } else if (wilc->io_type == WILC_HIF_SDIO) { + h->hif_write_reg(wilc, WILC_SDIO_HOST_TO_FW_REG, + WILC_SDIO_HOST_TO_FW_BIT); + usleep_range(200, 400); + h->hif_read_reg(wilc, WILC_SDIO_WAKEUP_REG, ®); + do { + h->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg | WILC_SDIO_WAKEUP_BIT); + h->hif_read_reg(wilc, WILC_SDIO_CLK_STATUS_REG, + &clk_status_reg); + + while (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)) { + usleep_range(2000, 2500); + + h->hif_read_reg(wilc, WILC_SDIO_CLK_STATUS_REG, + &clk_status_reg); + } + if (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)) { + h->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg & ~WILC_SDIO_WAKEUP_BIT); + } + } while (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)); + } + + if (wilc->chip_ps_state == WILC_CHIP_SLEEPING_MANUAL) { + if (wilc_get_chipid(wilc, false) < WILC_1000_BASE_ID_2B) { + u32 val32; + + h->hif_read_reg(wilc, WILC_REG_4_TO_1_RX, &val32); + val32 |= BIT(6); + h->hif_write_reg(wilc, WILC_REG_4_TO_1_RX, val32); + + h->hif_read_reg(wilc, WILC_REG_4_TO_1_TX_BANK0, &val32); + val32 |= BIT(6); + h->hif_write_reg(wilc, WILC_REG_4_TO_1_TX_BANK0, val32); + } + } + wilc->chip_ps_state = WILC_CHIP_WAKEDUP; +} +EXPORT_SYMBOL_GPL(chip_wakeup); + +void host_wakeup_notify(struct wilc *wilc) +{ + acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); + wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_2, 1); + release_bus(wilc, WILC_BUS_RELEASE_ONLY); +} +EXPORT_SYMBOL_GPL(host_wakeup_notify); + +void host_sleep_notify(struct wilc *wilc) +{ + acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); + wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_1, 1); + release_bus(wilc, WILC_BUS_RELEASE_ONLY); +} +EXPORT_SYMBOL_GPL(host_sleep_notify); + +int wilc_wlan_handle_txq(struct wilc *wilc, u32 *txq_count) +{ + int i, entries = 0; + u32 sum; + u32 reg; + u32 offset = 0; + int vmm_sz = 0; + struct txq_entry_t *tqe; + int ret = 0; + int counter; + int timeout; + u32 vmm_table[WILC_VMM_TBL_SIZE]; + const struct wilc_hif_func *func; + u8 *txb = wilc->tx_buffer; + struct net_device *dev; + struct wilc_vif *vif; + + if (wilc->quit) + goto out_update_cnt; + + mutex_lock(&wilc->txq_add_to_head_cs); + tqe = wilc_wlan_txq_get_first(wilc); + if (!tqe) + goto out_unlock; + dev = tqe->vif->ndev; + wilc_wlan_txq_filter_dup_tcp_ack(dev); + i = 0; + sum = 0; + while (tqe && (i < (WILC_VMM_TBL_SIZE - 1))) { + if (tqe->type == WILC_CFG_PKT) + vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET; + else if (tqe->type == WILC_NET_PKT) + vmm_sz = ETH_ETHERNET_HDR_OFFSET; + else + vmm_sz = HOST_HDR_OFFSET; + + vmm_sz += tqe->buffer_size; + vmm_sz = ALIGN(vmm_sz, 4); + + if ((sum + vmm_sz) > WILC_TX_BUFF_SIZE) + break; + + vmm_table[i] = vmm_sz / 4; + if (tqe->type == WILC_CFG_PKT) + vmm_table[i] |= BIT(10); + cpu_to_le32s(&vmm_table[i]); + + i++; + sum += vmm_sz; + tqe = wilc_wlan_txq_get_next(wilc, tqe); + } + + if (i == 0) + goto out_unlock; + vmm_table[i] = 0x0; + + acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); + counter = 0; + func = wilc->hif_func; + do { + ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); + if (ret) + break; + + if ((reg & 0x1) == 0) + break; + + counter++; + if (counter > 200) { + counter = 0; + ret = func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, 0); + break; + } + } while (!wilc->quit); + + if (ret) + goto out_release_bus; + + timeout = 200; + do { + ret = func->hif_block_tx(wilc, + WILC_VMM_TBL_RX_SHADOW_BASE, + (u8 *)vmm_table, + ((i + 1) * 4)); + if (ret) + break; + + ret = func->hif_write_reg(wilc, WILC_HOST_VMM_CTL, 0x2); + if (ret) + break; + + do { + ret = func->hif_read_reg(wilc, WILC_HOST_VMM_CTL, ®); + if (ret) + break; + if (FIELD_GET(WILC_VMM_ENTRY_AVAILABLE, reg)) { + entries = FIELD_GET(WILC_VMM_ENTRY_COUNT, reg); + break; + } + } while (--timeout); + if (timeout <= 0) { + ret = func->hif_write_reg(wilc, WILC_HOST_VMM_CTL, 0x0); + break; + } + + if (ret) + break; + + if (entries == 0) { + ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); + if (ret) + break; + reg &= ~BIT(0); + ret = func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, reg); + } + } while (0); + + if (ret) + goto out_release_bus; + + if (entries == 0) { + /* + * No VMM space available in firmware so retry to transmit + * the packet from tx queue. + */ + ret = WILC_VMM_ENTRY_FULL_RETRY; + goto out_release_bus; + } + + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + + offset = 0; + i = 0; + do { + u32 header, buffer_offset; + char *bssid; + u8 mgmt_ptk = 0; + + tqe = wilc_wlan_txq_remove_from_head(dev); + if (!tqe) + break; + + vif = tqe->vif; + if (vmm_table[i] == 0) + break; + + le32_to_cpus(&vmm_table[i]); + vmm_sz = FIELD_GET(WILC_VMM_BUFFER_SIZE, vmm_table[i]); + vmm_sz *= 4; + + if (tqe->type == WILC_MGMT_PKT) + mgmt_ptk = 1; + + header = (FIELD_PREP(WILC_VMM_HDR_TYPE, tqe->type) | + FIELD_PREP(WILC_VMM_HDR_MGMT_FIELD, mgmt_ptk) | + FIELD_PREP(WILC_VMM_HDR_PKT_SIZE, tqe->buffer_size) | + FIELD_PREP(WILC_VMM_HDR_BUFF_SIZE, vmm_sz)); + + cpu_to_le32s(&header); + memcpy(&txb[offset], &header, 4); + if (tqe->type == WILC_CFG_PKT) { + buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET; + } else if (tqe->type == WILC_NET_PKT) { + bssid = tqe->vif->bssid; + buffer_offset = ETH_ETHERNET_HDR_OFFSET; + memcpy(&txb[offset + 8], bssid, 6); + } else { + buffer_offset = HOST_HDR_OFFSET; + } + + memcpy(&txb[offset + buffer_offset], + tqe->buffer, tqe->buffer_size); + offset += vmm_sz; + i++; + tqe->status = 1; + if (tqe->tx_complete_func) + tqe->tx_complete_func(tqe->priv, tqe->status); + if (tqe->ack_idx != NOT_TCP_ACK && + tqe->ack_idx < MAX_PENDING_ACKS) + vif->ack_filter.pending_acks[tqe->ack_idx].txqe = NULL; + kfree(tqe); + } while (--entries); + + acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); + + ret = func->hif_clear_int_ext(wilc, ENABLE_TX_VMM); + if (ret) + goto out_release_bus; + + ret = func->hif_block_tx_ext(wilc, 0, txb, offset); + +out_release_bus: + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + +out_unlock: + mutex_unlock(&wilc->txq_add_to_head_cs); + +out_update_cnt: + *txq_count = wilc->txq_entries; + return ret; +} + +static void wilc_wlan_handle_rx_buff(struct wilc *wilc, u8 *buffer, int size) +{ + int offset = 0; + u32 header; + u32 pkt_len, pkt_offset, tp_len; + int is_cfg_packet; + u8 *buff_ptr; + + do { + buff_ptr = buffer + offset; + header = get_unaligned_le32(buff_ptr); + + is_cfg_packet = FIELD_GET(WILC_PKT_HDR_CONFIG_FIELD, header); + pkt_offset = FIELD_GET(WILC_PKT_HDR_OFFSET_FIELD, header); + tp_len = FIELD_GET(WILC_PKT_HDR_TOTAL_LEN_FIELD, header); + pkt_len = FIELD_GET(WILC_PKT_HDR_LEN_FIELD, header); + + if (pkt_len == 0 || tp_len == 0) + break; + + if (pkt_offset & IS_MANAGMEMENT) { + buff_ptr += HOST_HDR_OFFSET; + wilc_wfi_mgmt_rx(wilc, buff_ptr, pkt_len); + } else { + if (!is_cfg_packet) { + wilc_frmw_to_host(wilc, buff_ptr, pkt_len, + pkt_offset); + } else { + struct wilc_cfg_rsp rsp; + + buff_ptr += pkt_offset; + + wilc_wlan_cfg_indicate_rx(wilc, buff_ptr, + pkt_len, + &rsp); + if (rsp.type == WILC_CFG_RSP) { + if (wilc->cfg_seq_no == rsp.seq_no) + complete(&wilc->cfg_event); + } else if (rsp.type == WILC_CFG_RSP_STATUS) { + wilc_mac_indicate(wilc); + } + } + } + offset += tp_len; + } while (offset < size); +} + +static void wilc_wlan_handle_rxq(struct wilc *wilc) +{ + int size; + u8 *buffer; + struct rxq_entry_t *rqe; + + while (!wilc->quit) { + rqe = wilc_wlan_rxq_remove(wilc); + if (!rqe) + break; + + buffer = rqe->buffer; + size = rqe->buffer_size; + wilc_wlan_handle_rx_buff(wilc, buffer, size); + + kfree(rqe); + } + if (wilc->quit) + complete(&wilc->cfg_event); +} + +static void wilc_unknown_isr_ext(struct wilc *wilc) +{ + wilc->hif_func->hif_clear_int_ext(wilc, 0); +} + +static void wilc_wlan_handle_isr_ext(struct wilc *wilc, u32 int_status) +{ + u32 offset = wilc->rx_buffer_offset; + u8 *buffer = NULL; + u32 size; + u32 retries = 0; + int ret = 0; + struct rxq_entry_t *rqe; + + size = FIELD_GET(WILC_INTERRUPT_DATA_SIZE, int_status) << 2; + + while (!size && retries < 10) { + wilc->hif_func->hif_read_size(wilc, &size); + size = FIELD_GET(WILC_INTERRUPT_DATA_SIZE, size) << 2; + retries++; + } + + if (size <= 0) + return; + + if (WILC_RX_BUFF_SIZE - offset < size) + offset = 0; + + buffer = &wilc->rx_buffer[offset]; + + wilc->hif_func->hif_clear_int_ext(wilc, DATA_INT_CLR | ENABLE_RX_VMM); + ret = wilc->hif_func->hif_block_rx_ext(wilc, 0, buffer, size); + if (ret) + return; + + offset += size; + wilc->rx_buffer_offset = offset; + rqe = kmalloc(sizeof(*rqe), GFP_KERNEL); + if (!rqe) + return; + + rqe->buffer = buffer; + rqe->buffer_size = size; + wilc_wlan_rxq_add(wilc, rqe); + wilc_wlan_handle_rxq(wilc); +} + +void wilc_handle_isr(struct wilc *wilc) +{ + u32 int_status; + + acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); + wilc->hif_func->hif_read_int(wilc, &int_status); + + if (int_status & DATA_INT_EXT) + wilc_wlan_handle_isr_ext(wilc, int_status); + + if (!(int_status & (ALL_INT_EXT))) + wilc_unknown_isr_ext(wilc); + + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); +} +EXPORT_SYMBOL_GPL(wilc_handle_isr); + +int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer, + u32 buffer_size) +{ + u32 offset; + u32 addr, size, size2, blksz; + u8 *dma_buffer; + int ret = 0; + + blksz = BIT(12); + + dma_buffer = kmalloc(blksz, GFP_KERNEL); + if (!dma_buffer) + return -EIO; + + offset = 0; + do { + addr = get_unaligned_le32(&buffer[offset]); + size = get_unaligned_le32(&buffer[offset + 4]); + acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); + offset += 8; + while (((int)size) && (offset < buffer_size)) { + if (size <= blksz) + size2 = size; + else + size2 = blksz; + + memcpy(dma_buffer, &buffer[offset], size2); + ret = wilc->hif_func->hif_block_tx(wilc, addr, + dma_buffer, size2); + if (ret) + break; + + addr += size2; + offset += size2; + size -= size2; + } + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + + if (ret) + goto fail; + } while (offset < buffer_size); + +fail: + + kfree(dma_buffer); + + return ret; +} + +int wilc_wlan_start(struct wilc *wilc) +{ + u32 reg = 0; + int ret; + u32 chipid; + + if (wilc->io_type == WILC_HIF_SDIO) { + reg = 0; + reg |= BIT(3); + } else if (wilc->io_type == WILC_HIF_SPI) { + reg = 1; + } + acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); + ret = wilc->hif_func->hif_write_reg(wilc, WILC_VMM_CORE_CFG, reg); + if (ret) { + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + return ret; + } + reg = 0; + if (wilc->io_type == WILC_HIF_SDIO && wilc->dev_irq_num) + reg |= WILC_HAVE_SDIO_IRQ_GPIO; + + ret = wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_1, reg); + if (ret) { + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + return ret; + } + + wilc->hif_func->hif_sync_ext(wilc, NUM_INT_EXT); + + ret = wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &chipid); + if (ret) { + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + return ret; + } + + wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); + if ((reg & BIT(10)) == BIT(10)) { + reg &= ~BIT(10); + wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); + wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); + } + + reg |= BIT(10); + ret = wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); + wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + + return ret; +} + +int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif) +{ + u32 reg = 0; + int ret; + + acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); + + ret = wilc->hif_func->hif_read_reg(wilc, WILC_GP_REG_0, ®); + if (ret) { + netdev_err(vif->ndev, "Error while reading reg\n"); + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + return ret; + } + + ret = wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_0, + (reg | WILC_ABORT_REQ_BIT)); + if (ret) { + netdev_err(vif->ndev, "Error while writing reg\n"); + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + return ret; + } + + ret = wilc->hif_func->hif_read_reg(wilc, WILC_FW_HOST_COMM, ®); + if (ret) { + netdev_err(vif->ndev, "Error while reading reg\n"); + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + return ret; + } + reg = BIT(0); + + ret = wilc->hif_func->hif_write_reg(wilc, WILC_FW_HOST_COMM, reg); + if (ret) { + netdev_err(vif->ndev, "Error while writing reg\n"); + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + return ret; + } + + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + + return 0; +} + +void wilc_wlan_cleanup(struct net_device *dev) +{ + struct txq_entry_t *tqe; + struct rxq_entry_t *rqe; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + + wilc->quit = 1; + while ((tqe = wilc_wlan_txq_remove_from_head(dev))) { + if (tqe->tx_complete_func) + tqe->tx_complete_func(tqe->priv, 0); + kfree(tqe); + } + + while ((rqe = wilc_wlan_rxq_remove(wilc))) + kfree(rqe); + + kfree(wilc->rx_buffer); + wilc->rx_buffer = NULL; + kfree(wilc->tx_buffer); + wilc->tx_buffer = NULL; + wilc->hif_func->hif_deinit(NULL); +} + +static int wilc_wlan_cfg_commit(struct wilc_vif *vif, int type, + u32 drv_handler) +{ + struct wilc *wilc = vif->wilc; + struct wilc_cfg_frame *cfg = &wilc->cfg_frame; + int t_len = wilc->cfg_frame_offset + sizeof(struct wilc_cfg_cmd_hdr); + + if (type == WILC_CFG_SET) + cfg->hdr.cmd_type = 'W'; + else + cfg->hdr.cmd_type = 'Q'; + + cfg->hdr.seq_no = wilc->cfg_seq_no % 256; + cfg->hdr.total_len = cpu_to_le16(t_len); + cfg->hdr.driver_handler = cpu_to_le32(drv_handler); + wilc->cfg_seq_no = cfg->hdr.seq_no; + + if (!wilc_wlan_txq_add_cfg_pkt(vif, (u8 *)&cfg->hdr, t_len)) + return -1; + + return 0; +} + +int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer, + u32 buffer_size, int commit, u32 drv_handler) +{ + u32 offset; + int ret_size; + struct wilc *wilc = vif->wilc; + + mutex_lock(&wilc->cfg_cmd_lock); + + if (start) + wilc->cfg_frame_offset = 0; + + offset = wilc->cfg_frame_offset; + ret_size = wilc_wlan_cfg_set_wid(wilc->cfg_frame.frame, offset, + wid, buffer, buffer_size); + offset += ret_size; + wilc->cfg_frame_offset = offset; + + if (!commit) { + mutex_unlock(&wilc->cfg_cmd_lock); + return ret_size; + } + + netdev_dbg(vif->ndev, "%s: seqno[%d]\n", __func__, wilc->cfg_seq_no); + + if (wilc_wlan_cfg_commit(vif, WILC_CFG_SET, drv_handler)) + ret_size = 0; + + if (!wait_for_completion_timeout(&wilc->cfg_event, + WILC_CFG_PKTS_TIMEOUT)) { + netdev_dbg(vif->ndev, "%s: Timed Out\n", __func__); + ret_size = 0; + } + + wilc->cfg_frame_offset = 0; + wilc->cfg_seq_no += 1; + mutex_unlock(&wilc->cfg_cmd_lock); + + return ret_size; +} + +int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit, + u32 drv_handler) +{ + u32 offset; + int ret_size; + struct wilc *wilc = vif->wilc; + + mutex_lock(&wilc->cfg_cmd_lock); + + if (start) + wilc->cfg_frame_offset = 0; + + offset = wilc->cfg_frame_offset; + ret_size = wilc_wlan_cfg_get_wid(wilc->cfg_frame.frame, offset, wid); + offset += ret_size; + wilc->cfg_frame_offset = offset; + + if (!commit) { + mutex_unlock(&wilc->cfg_cmd_lock); + return ret_size; + } + + if (wilc_wlan_cfg_commit(vif, WILC_CFG_QUERY, drv_handler)) + ret_size = 0; + + if (!wait_for_completion_timeout(&wilc->cfg_event, + WILC_CFG_PKTS_TIMEOUT)) { + netdev_dbg(vif->ndev, "%s: Timed Out\n", __func__); + ret_size = 0; + } + wilc->cfg_frame_offset = 0; + wilc->cfg_seq_no += 1; + mutex_unlock(&wilc->cfg_cmd_lock); + + return ret_size; +} + +int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids, + u32 count) +{ + int i; + int ret = 0; + u32 drv = wilc_get_vif_idx(vif); + + if (mode == WILC_GET_CFG) { + for (i = 0; i < count; i++) { + if (!wilc_wlan_cfg_get(vif, !i, + wids[i].id, + (i == count - 1), + drv)) { + ret = -ETIMEDOUT; + break; + } + } + for (i = 0; i < count; i++) { + wids[i].size = wilc_wlan_cfg_get_val(vif->wilc, + wids[i].id, + wids[i].val, + wids[i].size); + } + } else if (mode == WILC_SET_CFG) { + for (i = 0; i < count; i++) { + if (!wilc_wlan_cfg_set(vif, !i, + wids[i].id, + wids[i].val, + wids[i].size, + (i == count - 1), + drv)) { + ret = -ETIMEDOUT; + break; + } + } + } + + return ret; +} + +static int init_chip(struct net_device *dev) +{ + u32 chipid; + u32 reg; + int ret = 0; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc = vif->wilc; + + acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); + + chipid = wilc_get_chipid(wilc, true); + + if ((chipid & 0xfff) != 0xa0) { + ret = wilc->hif_func->hif_read_reg(wilc, + WILC_CORTUS_RESET_MUX_SEL, + ®); + if (ret) { + netdev_err(dev, "fail read reg 0x1118\n"); + goto release; + } + reg |= BIT(0); + ret = wilc->hif_func->hif_write_reg(wilc, + WILC_CORTUS_RESET_MUX_SEL, + reg); + if (ret) { + netdev_err(dev, "fail write reg 0x1118\n"); + goto release; + } + ret = wilc->hif_func->hif_write_reg(wilc, + WILC_CORTUS_BOOT_REGISTER, + WILC_CORTUS_BOOT_FROM_IRAM); + if (ret) { + netdev_err(dev, "fail write reg 0xc0000\n"); + goto release; + } + } + +release: + release_bus(wilc, WILC_BUS_RELEASE_ONLY); + + return ret; +} + +u32 wilc_get_chipid(struct wilc *wilc, bool update) +{ + static u32 chipid; + u32 tempchipid = 0; + u32 rfrevid = 0; + + if (chipid == 0 || update) { + wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &tempchipid); + wilc->hif_func->hif_read_reg(wilc, WILC_RF_REVISION_ID, + &rfrevid); + if (!is_wilc1000(tempchipid)) { + chipid = 0; + return chipid; + } + if (tempchipid == WILC_1000_BASE_ID_2A) { /* 0x1002A0 */ + if (rfrevid != 0x1) + tempchipid = WILC_1000_BASE_ID_2A_REV1; + } else if (tempchipid == WILC_1000_BASE_ID_2B) { /* 0x1002B0 */ + if (rfrevid == 0x4) + tempchipid = WILC_1000_BASE_ID_2B_REV1; + else if (rfrevid != 0x3) + tempchipid = WILC_1000_BASE_ID_2B_REV2; + } + + chipid = tempchipid; + } + return chipid; +} + +int wilc_wlan_init(struct net_device *dev) +{ + int ret = 0; + struct wilc_vif *vif = netdev_priv(dev); + struct wilc *wilc; + + wilc = vif->wilc; + + wilc->quit = 0; + + if (wilc->hif_func->hif_init(wilc, false)) { + ret = -EIO; + goto fail; + } + + if (!wilc->tx_buffer) + wilc->tx_buffer = kmalloc(WILC_TX_BUFF_SIZE, GFP_KERNEL); + + if (!wilc->tx_buffer) { + ret = -ENOBUFS; + goto fail; + } + + if (!wilc->rx_buffer) + wilc->rx_buffer = kmalloc(WILC_RX_BUFF_SIZE, GFP_KERNEL); + + if (!wilc->rx_buffer) { + ret = -ENOBUFS; + goto fail; + } + + if (init_chip(dev)) { + ret = -EIO; + goto fail; + } + + return 0; + +fail: + + kfree(wilc->rx_buffer); + wilc->rx_buffer = NULL; + kfree(wilc->tx_buffer); + wilc->tx_buffer = NULL; + + return ret; +} From patchwork Wed Mar 11 12:18:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04FFFC3F2C6 for ; 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Signed-off-by: Ajay Singh --- .../net/wireless/microchip/wilc1000/sdio.c | 1023 +++++++++++++++++ 1 file changed, 1023 insertions(+) create mode 100644 drivers/net/wireless/microchip/wilc1000/sdio.c diff --git a/drivers/net/wireless/microchip/wilc1000/sdio.c b/drivers/net/wireless/microchip/wilc1000/sdio.c new file mode 100644 index 000000000000..36eb589263bf --- /dev/null +++ b/drivers/net/wireless/microchip/wilc1000/sdio.c @@ -0,0 +1,1023 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. + * All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "netdev.h" +#include "cfg80211.h" + +#define SDIO_MODALIAS "wilc1000_sdio" + +#define SDIO_VENDOR_ID_WILC 0x0296 +#define SDIO_DEVICE_ID_WILC 0x5347 + +static const struct sdio_device_id wilc_sdio_ids[] = { + { SDIO_DEVICE(SDIO_VENDOR_ID_WILC, SDIO_DEVICE_ID_WILC) }, + { }, +}; + +#define WILC_SDIO_BLOCK_SIZE 512 + +struct wilc_sdio { + bool irq_gpio; + u32 block_size; + int has_thrpt_enh3; +}; + +struct sdio_cmd52 { + u32 read_write: 1; + u32 function: 3; + u32 raw: 1; + u32 address: 17; + u32 data: 8; +}; + +struct sdio_cmd53 { + u32 read_write: 1; + u32 function: 3; + u32 block_mode: 1; + u32 increment: 1; + u32 address: 17; + u32 count: 9; + u8 *buffer; + u32 block_size; +}; + +static const struct wilc_hif_func wilc_hif_sdio; + +static void wilc_sdio_interrupt(struct sdio_func *func) +{ + sdio_release_host(func); + wilc_handle_isr(sdio_get_drvdata(func)); + sdio_claim_host(func); +} + +static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd) +{ + struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); + int ret; + u8 data; + + sdio_claim_host(func); + + func->num = cmd->function; + if (cmd->read_write) { /* write */ + if (cmd->raw) { + sdio_writeb(func, cmd->data, cmd->address, &ret); + data = sdio_readb(func, cmd->address, &ret); + cmd->data = data; + } else { + sdio_writeb(func, cmd->data, cmd->address, &ret); + } + } else { /* read */ + data = sdio_readb(func, cmd->address, &ret); + cmd->data = data; + } + + sdio_release_host(func); + + if (ret) + dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); + return ret; +} + +static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd) +{ + struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev); + int size, ret; + + sdio_claim_host(func); + + func->num = cmd->function; + func->cur_blksize = cmd->block_size; + if (cmd->block_mode) + size = cmd->count * cmd->block_size; + else + size = cmd->count; + + if (cmd->read_write) { /* write */ + ret = sdio_memcpy_toio(func, cmd->address, + (void *)cmd->buffer, size); + } else { /* read */ + ret = sdio_memcpy_fromio(func, (void *)cmd->buffer, + cmd->address, size); + } + + sdio_release_host(func); + + if (ret) + dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret); + + return ret; +} + +static int wilc_sdio_probe(struct sdio_func *func, + const struct sdio_device_id *id) +{ + struct wilc *wilc; + int ret; + struct wilc_sdio *sdio_priv; + + sdio_priv = kzalloc(sizeof(*sdio_priv), GFP_KERNEL); + if (!sdio_priv) + return -ENOMEM; + + ret = wilc_cfg80211_init(&wilc, &func->dev, WILC_HIF_SDIO, + &wilc_hif_sdio); + if (ret) { + kfree(sdio_priv); + return ret; + } + + if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) { + struct device_node *np = func->card->dev.of_node; + int irq_num = of_irq_get(np, 0); + + if (irq_num > 0) { + wilc->dev_irq_num = irq_num; + sdio_priv->irq_gpio = true; + } + } + + sdio_set_drvdata(func, wilc); + wilc->bus_data = sdio_priv; + wilc->dev = &func->dev; + + wilc->rtc_clk = devm_clk_get(&func->card->dev, "rtc"); + if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + else if (!IS_ERR(wilc->rtc_clk)) + clk_prepare_enable(wilc->rtc_clk); + + dev_info(&func->dev, "Driver Initializing success\n"); + return 0; +} + +static void wilc_sdio_remove(struct sdio_func *func) +{ + struct wilc *wilc = sdio_get_drvdata(func); + + if (!IS_ERR(wilc->rtc_clk)) + clk_disable_unprepare(wilc->rtc_clk); + + wilc_netdev_cleanup(wilc); +} + +static int wilc_sdio_reset(struct wilc *wilc) +{ + struct sdio_cmd52 cmd; + int ret; + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = SDIO_CCCR_ABORT; + cmd.data = WILC_SDIO_CCCR_ABORT_RESET; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n"); + return ret; + } + return 0; +} + +static int wilc_sdio_suspend(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + struct wilc *wilc = sdio_get_drvdata(func); + int ret; + + dev_info(dev, "sdio suspend\n"); + chip_wakeup(wilc); + + if (!IS_ERR(wilc->rtc_clk)) + clk_disable_unprepare(wilc->rtc_clk); + + if (wilc->suspend_event) { + host_sleep_notify(wilc); + chip_allow_sleep(wilc); + } + + ret = wilc_sdio_reset(wilc); + if (ret) { + dev_err(&func->dev, "Fail reset sdio\n"); + return ret; + } + sdio_claim_host(func); + + return 0; +} + +static int wilc_sdio_enable_interrupt(struct wilc *dev) +{ + struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); + int ret = 0; + + sdio_claim_host(func); + ret = sdio_claim_irq(func, wilc_sdio_interrupt); + sdio_release_host(func); + + if (ret < 0) { + dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret); + ret = -EIO; + } + return ret; +} + +static void wilc_sdio_disable_interrupt(struct wilc *dev) +{ + struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev); + int ret; + + sdio_claim_host(func); + ret = sdio_release_irq(func); + if (ret < 0) + dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret); + sdio_release_host(func); +} + +/******************************************** + * + * Function 0 + * + ********************************************/ + +static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct sdio_cmd52 cmd; + int ret; + + /** + * Review: BIG ENDIAN + **/ + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = WILC_SDIO_FBR_CSA_REG; + cmd.data = (u8)adr; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Failed cmd52, set %04x data...\n", + cmd.address); + return ret; + } + + cmd.address = WILC_SDIO_FBR_CSA_REG + 1; + cmd.data = (u8)(adr >> 8); + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Failed cmd52, set %04x data...\n", + cmd.address); + return ret; + } + + cmd.address = WILC_SDIO_FBR_CSA_REG + 2; + cmd.data = (u8)(adr >> 16); + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Failed cmd52, set %04x data...\n", + cmd.address); + return ret; + } + + return 0; +} + +static int wilc_sdio_set_block_size(struct wilc *wilc, u8 func_num, + u32 block_size) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct sdio_cmd52 cmd; + int ret; + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE; + cmd.data = (u8)block_size; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Failed cmd52, set %04x data...\n", + cmd.address); + return ret; + } + + cmd.address = SDIO_FBR_BASE(func_num) + SDIO_CCCR_BLKSIZE + 1; + cmd.data = (u8)(block_size >> 8); + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Failed cmd52, set %04x data...\n", + cmd.address); + return ret; + } + + return 0; +} + +/******************************************** + * + * Sdio interfaces + * + ********************************************/ +static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + int ret; + + cpu_to_le32s(&data); + + if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ + struct sdio_cmd52 cmd; + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = addr; + cmd.data = data; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) + dev_err(&func->dev, + "Failed cmd 52, read reg (%08x) ...\n", addr); + } else { + struct sdio_cmd53 cmd; + + /** + * set the AHB address + **/ + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + + cmd.read_write = 1; + cmd.function = 0; + cmd.address = WILC_SDIO_FBR_DATA_REG; + cmd.block_mode = 0; + cmd.increment = 1; + cmd.count = 4; + cmd.buffer = (u8 *)&data; + cmd.block_size = sdio_priv->block_size; + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) + dev_err(&func->dev, + "Failed cmd53, write reg (%08x)...\n", addr); + } + + return ret; +} + +static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + u32 block_size = sdio_priv->block_size; + struct sdio_cmd53 cmd; + int nblk, nleft, ret; + + cmd.read_write = 1; + if (addr > 0) { + /** + * func 0 access + **/ + cmd.function = 0; + cmd.address = WILC_SDIO_FBR_DATA_REG; + } else { + /** + * func 1 access + **/ + cmd.function = 1; + cmd.address = WILC_SDIO_F1_DATA_REG; + } + + size = ALIGN(size, 4); + nblk = size / block_size; + nleft = size % block_size; + + if (nblk > 0) { + cmd.block_mode = 1; + cmd.increment = 1; + cmd.count = nblk; + cmd.buffer = buf; + cmd.block_size = block_size; + if (addr > 0) { + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + } + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd53 [%x], block send...\n", addr); + return ret; + } + if (addr > 0) + addr += nblk * block_size; + buf += nblk * block_size; + } + + if (nleft > 0) { + cmd.block_mode = 0; + cmd.increment = 1; + cmd.count = nleft; + cmd.buffer = buf; + + cmd.block_size = block_size; + + if (addr > 0) { + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + } + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd53 [%x], bytes send...\n", addr); + return ret; + } + } + + return 0; +} + +static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + int ret; + + if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */ + struct sdio_cmd52 cmd; + + cmd.read_write = 0; + cmd.function = 0; + cmd.raw = 0; + cmd.address = addr; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd 52, read reg (%08x) ...\n", addr); + return ret; + } + *data = cmd.data; + } else { + struct sdio_cmd53 cmd; + + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + + cmd.read_write = 0; + cmd.function = 0; + cmd.address = WILC_SDIO_FBR_DATA_REG; + cmd.block_mode = 0; + cmd.increment = 1; + cmd.count = 4; + cmd.buffer = (u8 *)data; + + cmd.block_size = sdio_priv->block_size; + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd53, read reg (%08x)...\n", addr); + return ret; + } + } + + le32_to_cpus(data); + return 0; +} + +static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + u32 block_size = sdio_priv->block_size; + struct sdio_cmd53 cmd; + int nblk, nleft, ret; + + cmd.read_write = 0; + if (addr > 0) { + /** + * func 0 access + **/ + cmd.function = 0; + cmd.address = WILC_SDIO_FBR_DATA_REG; + } else { + /** + * func 1 access + **/ + cmd.function = 1; + cmd.address = WILC_SDIO_F1_DATA_REG; + } + + size = ALIGN(size, 4); + nblk = size / block_size; + nleft = size % block_size; + + if (nblk > 0) { + cmd.block_mode = 1; + cmd.increment = 1; + cmd.count = nblk; + cmd.buffer = buf; + cmd.block_size = block_size; + if (addr > 0) { + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + } + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd53 [%x], block read...\n", addr); + return ret; + } + if (addr > 0) + addr += nblk * block_size; + buf += nblk * block_size; + } /* if (nblk > 0) */ + + if (nleft > 0) { + cmd.block_mode = 0; + cmd.increment = 1; + cmd.count = nleft; + cmd.buffer = buf; + + cmd.block_size = block_size; + + if (addr > 0) { + ret = wilc_sdio_set_func0_csa_address(wilc, addr); + if (ret) + return ret; + } + ret = wilc_sdio_cmd53(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd53 [%x], bytes read...\n", addr); + return ret; + } + } + + return 0; +} + +/******************************************** + * + * Bus interfaces + * + ********************************************/ + +static int wilc_sdio_deinit(struct wilc *wilc) +{ + return 0; +} + +static int wilc_sdio_init(struct wilc *wilc, bool resume) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + struct sdio_cmd52 cmd; + int loop, ret; + u32 chipid; + + /** + * function 0 csa enable + **/ + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 1; + cmd.address = SDIO_FBR_BASE(func->num); + cmd.data = SDIO_FBR_ENABLE_CSA; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Fail cmd 52, enable csa...\n"); + return ret; + } + + /** + * function 0 block size + **/ + ret = wilc_sdio_set_block_size(wilc, 0, WILC_SDIO_BLOCK_SIZE); + if (ret) { + dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n"); + return ret; + } + sdio_priv->block_size = WILC_SDIO_BLOCK_SIZE; + + /** + * enable func1 IO + **/ + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 1; + cmd.address = SDIO_CCCR_IOEx; + cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Fail cmd 52, set IOE register...\n"); + return ret; + } + + /** + * make sure func 1 is up + **/ + cmd.read_write = 0; + cmd.function = 0; + cmd.raw = 0; + cmd.address = SDIO_CCCR_IORx; + loop = 3; + do { + cmd.data = 0; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Fail cmd 52, get IOR register...\n"); + return ret; + } + if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1) + break; + } while (loop--); + + if (loop <= 0) { + dev_err(&func->dev, "Fail func 1 is not ready...\n"); + return -EINVAL; + } + + /** + * func 1 is ready, set func 1 block size + **/ + ret = wilc_sdio_set_block_size(wilc, 1, WILC_SDIO_BLOCK_SIZE); + if (ret) { + dev_err(&func->dev, "Fail set func 1 block size...\n"); + return ret; + } + + /** + * func 1 interrupt enable + **/ + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 1; + cmd.address = SDIO_CCCR_IENx; + cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, "Fail cmd 52, set IEN register...\n"); + return ret; + } + + /** + * make sure can read back chip id correctly + **/ + if (!resume) { + int rev; + + ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); + if (ret) { + dev_err(&func->dev, "Fail cmd read chip id...\n"); + return ret; + } + dev_err(&func->dev, "chipid (%08x)\n", chipid); + rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid); + if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A)) + sdio_priv->has_thrpt_enh3 = 1; + else + sdio_priv->has_thrpt_enh3 = 0; + dev_info(&func->dev, "has_thrpt_enh3 = %d...\n", + sdio_priv->has_thrpt_enh3); + } + + return 0; +} + +static int wilc_sdio_read_size(struct wilc *wilc, u32 *size) +{ + u32 tmp; + struct sdio_cmd52 cmd; + + /** + * Read DMA count in words + **/ + cmd.read_write = 0; + cmd.function = 0; + cmd.raw = 0; + cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG; + cmd.data = 0; + wilc_sdio_cmd52(wilc, &cmd); + tmp = cmd.data; + + cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1; + cmd.data = 0; + wilc_sdio_cmd52(wilc, &cmd); + tmp |= (cmd.data << 8); + + *size = tmp; + return 0; +} + +static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + u32 tmp; + u8 irq_flags; + struct sdio_cmd52 cmd; + + wilc_sdio_read_size(wilc, &tmp); + + /** + * Read IRQ flags + **/ + if (!sdio_priv->irq_gpio) { + cmd.function = 1; + cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG; + } else { + cmd.function = 0; + cmd.address = WILC_SDIO_IRQ_FLAG_REG; + } + cmd.raw = 0; + cmd.read_write = 0; + cmd.data = 0; + wilc_sdio_cmd52(wilc, &cmd); + irq_flags = cmd.data; + tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data); + + if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)) + dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n", + FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags)); + + *int_status = tmp; + + return 0; +} + +static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + int ret; + int vmm_ctl; + + if (sdio_priv->has_thrpt_enh3) { + u32 reg = 0; + + if (sdio_priv->irq_gpio) + reg = val & (BIT(MAX_NUM_INT) - 1); + + /* select VMM table 0 */ + if (val & SEL_VMM_TBL0) + reg |= BIT(5); + /* select VMM table 1 */ + if (val & SEL_VMM_TBL1) + reg |= BIT(6); + /* enable VMM */ + if (val & EN_VMM) + reg |= BIT(7); + if (reg) { + struct sdio_cmd52 cmd; + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; + cmd.data = reg; + + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd52, set (%02x) data (%d) ...\n", + cmd.address, __LINE__); + return ret; + } + } + return 0; + } + if (sdio_priv->irq_gpio) { + /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */ + /* + * Cannot clear multiple interrupts. + * Must clear each interrupt individually. + */ + u32 flags; + int i; + + flags = val & (BIT(MAX_NUM_INT) - 1); + for (i = 0; i < NUM_INT_EXT && flags; i++) { + if (flags & BIT(i)) { + struct sdio_cmd52 cmd; + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG; + cmd.data = BIT(i); + + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd52, set (%02x) data (%d) ...\n", + cmd.address, __LINE__); + return ret; + } + flags &= ~BIT(i); + } + } + + for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) { + if (flags & BIT(i)) { + dev_err(&func->dev, + "Unexpected interrupt cleared %d...\n", + i); + flags &= ~BIT(i); + } + } + } + + vmm_ctl = 0; + /* select VMM table 0 */ + if (val & SEL_VMM_TBL0) + vmm_ctl |= BIT(0); + /* select VMM table 1 */ + if (val & SEL_VMM_TBL1) + vmm_ctl |= BIT(1); + /* enable VMM */ + if (val & EN_VMM) + vmm_ctl |= BIT(2); + + if (vmm_ctl) { + struct sdio_cmd52 cmd; + + cmd.read_write = 1; + cmd.function = 0; + cmd.raw = 0; + cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG; + cmd.data = vmm_ctl; + ret = wilc_sdio_cmd52(wilc, &cmd); + if (ret) { + dev_err(&func->dev, + "Failed cmd52, set (%02x) data (%d) ...\n", + cmd.address, __LINE__); + return ret; + } + } + return 0; +} + +static int wilc_sdio_sync_ext(struct wilc *wilc, int nint) +{ + struct sdio_func *func = dev_to_sdio_func(wilc->dev); + struct wilc_sdio *sdio_priv = wilc->bus_data; + u32 reg; + + if (nint > MAX_NUM_INT) { + dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); + return -EINVAL; + } + + /** + * Disable power sequencer + **/ + if (wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { + dev_err(&func->dev, "Failed read misc reg...\n"); + return -EINVAL; + } + + reg &= ~BIT(8); + if (wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { + dev_err(&func->dev, "Failed write misc reg...\n"); + return -EINVAL; + } + + if (sdio_priv->irq_gpio) { + u32 reg; + int ret, i; + + /** + * interrupt pin mux select + **/ + ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); + if (ret) { + dev_err(&func->dev, "Failed read reg (%08x)...\n", + WILC_PIN_MUX_0); + return ret; + } + reg |= BIT(8); + ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); + if (ret) { + dev_err(&func->dev, "Failed write reg (%08x)...\n", + WILC_PIN_MUX_0); + return ret; + } + + /** + * interrupt enable + **/ + ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); + if (ret) { + dev_err(&func->dev, "Failed read reg (%08x)...\n", + WILC_INTR_ENABLE); + return ret; + } + + for (i = 0; (i < 5) && (nint > 0); i++, nint--) + reg |= BIT((27 + i)); + ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); + if (ret) { + dev_err(&func->dev, "Failed write reg (%08x)...\n", + WILC_INTR_ENABLE); + return ret; + } + if (nint) { + ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); + if (ret) { + dev_err(&func->dev, + "Failed read reg (%08x)...\n", + WILC_INTR2_ENABLE); + return ret; + } + + for (i = 0; (i < 3) && (nint > 0); i++, nint--) + reg |= BIT(i); + + ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); + if (ret) { + dev_err(&func->dev, + "Failed write reg (%08x)...\n", + WILC_INTR2_ENABLE); + return ret; + } + } + } + return 0; +} + +/* Global sdio HIF function table */ +static const struct wilc_hif_func wilc_hif_sdio = { + .hif_init = wilc_sdio_init, + .hif_deinit = wilc_sdio_deinit, + .hif_read_reg = wilc_sdio_read_reg, + .hif_write_reg = wilc_sdio_write_reg, + .hif_block_rx = wilc_sdio_read, + .hif_block_tx = wilc_sdio_write, + .hif_read_int = wilc_sdio_read_int, + .hif_clear_int_ext = wilc_sdio_clear_int_ext, + .hif_read_size = wilc_sdio_read_size, + .hif_block_tx_ext = wilc_sdio_write, + .hif_block_rx_ext = wilc_sdio_read, + .hif_sync_ext = wilc_sdio_sync_ext, + .enable_interrupt = wilc_sdio_enable_interrupt, + .disable_interrupt = wilc_sdio_disable_interrupt, +}; + +static int wilc_sdio_resume(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + struct wilc *wilc = sdio_get_drvdata(func); + + dev_info(dev, "sdio resume\n"); + sdio_release_host(func); + chip_wakeup(wilc); + wilc_sdio_init(wilc, true); + + if (wilc->suspend_event) + host_wakeup_notify(wilc); + + chip_allow_sleep(wilc); + + return 0; +} + +static const struct of_device_id wilc_of_match[] = { + { .compatible = "microchip,wilc1000", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, wilc_of_match); + +static const struct dev_pm_ops wilc_sdio_pm_ops = { + .suspend = wilc_sdio_suspend, + .resume = wilc_sdio_resume, +}; + +static struct sdio_driver wilc_sdio_driver = { + .name = SDIO_MODALIAS, + .id_table = wilc_sdio_ids, + .probe = wilc_sdio_probe, + .remove = wilc_sdio_remove, + .drv = { + .pm = &wilc_sdio_pm_ops, + .of_match_table = wilc_of_match, + } +}; +module_driver(wilc_sdio_driver, + sdio_register_driver, + sdio_unregister_driver); +MODULE_LICENSE("GPL"); From patchwork Wed Mar 11 12:18:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Singh X-Patchwork-Id: 216318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CACBDC18E5B for ; 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It's moved from staging to 'Documentation/devicetree/bindings/net/wireless' path. Signed-off-by: Ajay Singh --- .../net/wireless/microchip,wilc1000.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/wireless/microchip,wilc1000.yaml diff --git a/Documentation/devicetree/bindings/net/wireless/microchip,wilc1000.yaml b/Documentation/devicetree/bindings/net/wireless/microchip,wilc1000.yaml new file mode 100644 index 000000000000..bc6cc5d3f347 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/microchip,wilc1000.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/microchip,wilc1000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip WILC wireless devicetree bindings + +maintainers: + - Adham Abozaeid + - Ajay Singh + +description: + The wilc1000 chips can be connected via SPI or SDIO. This document + describes the binding to connect wilc devices. + +properties: + compatible: + const: microchip,wilc1000 + + spi-max-frequency: true + + interrupts: + maxItems: 1 + + clocks: + description: phandle to the clock connected on rtc clock line. + maxItems: 1 + + clock-names: + const: rtc + +required: + - compatible + - interrupts + +examples: + - | + spi1: spi@fc018000 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&pioB 21 0>; + wifi@0 { + compatible = "microchip,wilc1000"; + spi-max-frequency = <48000000>; + reg = <0>; + interrupt-parent = <&pioC>; + interrupts = <27 0>; + clocks = <&pck1>; + clock-names = "rtc"; + }; + }; + + - | + mmc1: mmc@fc000000 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + non-removable; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + bus-width = <4>; + wifi@0 { + compatible = "microchip,wilc1000"; + reg = <0>; + interrupt-parent = <&pioC>; + interrupts = <27 0>; + clocks = <&pck1>; + clock-names = "rtc"; + }; + };