From patchwork Fri May 29 07:36:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 214503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D71D3C433E2 for ; Fri, 29 May 2020 07:37:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BFF2D2074D for ; Fri, 29 May 2020 07:37:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726762AbgE2HhN (ORCPT ); Fri, 29 May 2020 03:37:13 -0400 Received: from twhmllg4.macronix.com ([211.75.127.132]:24793 "EHLO TWHMLLG4.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726771AbgE2HhN (ORCPT ); Fri, 29 May 2020 03:37:13 -0400 Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG4.macronix.com with ESMTP id 04T7aHpv067318; Fri, 29 May 2020 15:36:18 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, tudor.ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, boris.brezillon@collabora.com, matthias.bgg@gmail.com Cc: p.yadav@ti.com, juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang Subject: [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from BFPT Date: Fri, 29 May 2020 15:36:09 +0800 Message-Id: <1590737775-4798-2-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> References: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG4.macronix.com 04T7aHpv067318 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Get maximum operation speed of device in octal mode from BFPT 20th DWORD. Signed-off-by: Mason Yang --- drivers/mtd/spi-nor/core.h | 2 ++ drivers/mtd/spi-nor/sfdp.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/sfdp.h | 4 ++++ 3 files changed, 42 insertions(+) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 6f2f6b2..7a36b22 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -190,6 +190,7 @@ struct spi_nor_locking_ops { * * @size: the flash memory density in bytes. * @page_size: the page size of the SPI NOR flash memory. + * @octal_max_speed: maximum operation speed of device in octal mode. * @hwcaps: describes the read and page program hardware * capabilities. * @reads: read capabilities ordered by priority: the higher index @@ -212,6 +213,7 @@ struct spi_nor_locking_ops { struct spi_nor_flash_parameter { u64 size; u32 page_size; + u16 octal_max_speed; struct spi_nor_hwcaps hwcaps; struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index f6038d3..4d13f66 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ +#include #include #include #include @@ -26,6 +27,12 @@ #define SFDP_JESD216A_MINOR 5 #define SFDP_JESD216B_MINOR 6 +/* Basic Flash Parameter Table 20th DWORD, Max operation speed of device */ +struct octal_max_speed { + u8 idx; /* Bits value */ + u16 hz; /* MHz */ +}; + struct sfdp_header { u32 signature; /* Ox50444653U <=> "SFDP" */ u8 minor; @@ -440,6 +447,22 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, u32 addr; u16 half; u8 erase_mask; + static const struct octal_max_speed max_hz[] = { + /* Bits value, MHz */ + { 0x0c, 400 }, + { 0x0b, 333 }, + { 0x0a, 266 }, + { 0x09, 250 }, + { 0x08, 200 }, + { 0x07, 166 }, + { 0x06, 133 }, + { 0x05, 100 }, + { 0x04, 80 }, + { 0x03, 66 }, + { 0x02, 50 }, + { 0x01, 33 }, + }; + u8 idx; /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) @@ -604,6 +627,19 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EINVAL; } + /* Octal mode max speed */ + idx = max(FIELD_GET(BFPT_DWORD20_OCTAL_DTR_MAX_SPEED, + bfpt.dwords[BFPT_DWORD(20)]), + FIELD_GET(BFPT_DWORD20_OCTAL_STR_MAX_SPEED, + bfpt.dwords[BFPT_DWORD(20)])); + + for (i = 0; i < ARRAY_SIZE(max_hz); i++) { + if (max_hz[i].idx == idx) { + params->octal_max_speed = max_hz[i].hz; + break; + } + } + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); } diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index e0a8ded..8ae6d9a 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -83,6 +83,10 @@ struct sfdp_bfpt { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ +#define BFPT_DWORD20_OCTAL_MAX_SPEED_MASK GENMASK(31, 16) +#define BFPT_DWORD20_OCTAL_DTR_MAX_SPEED GENMASK(31, 28) +#define BFPT_DWORD20_OCTAL_STR_MAX_SPEED GENMASK(19, 16) + struct sfdp_parameter_header { u8 id_lsb; u8 minor; From patchwork Fri May 29 07:36:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 214504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BFD8C433E1 for ; Fri, 29 May 2020 07:37:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E3D4120897 for ; Fri, 29 May 2020 07:37:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726771AbgE2HhN (ORCPT ); Fri, 29 May 2020 03:37:13 -0400 Received: from twhmllg4.macronix.com ([211.75.127.132]:24791 "EHLO TWHMLLG4.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726767AbgE2HhN (ORCPT ); Fri, 29 May 2020 03:37:13 -0400 Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG4.macronix.com with ESMTP id 04T7aHpw067318; Fri, 29 May 2020 15:36:19 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, tudor.ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, boris.brezillon@collabora.com, matthias.bgg@gmail.com Cc: p.yadav@ti.com, juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang Subject: [PATCH v4 2/7] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Date: Fri, 29 May 2020 15:36:10 +0800 Message-Id: <1590737775-4798-3-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> References: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG4.macronix.com 04T7aHpw067318 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org JESD251, xSPI profile 1.0 table supports octal DTR mode. Extract information like the fast read opcode, dummy cycles for various frequencies, the number of dummy cycles needed for a Read Status Register command, the number of address bytes needed for a Read Status Register command, read volatile register command and write volatile register command. According to BFPT 20th DWORD of octal maximum speed, driver get it's specific dummy cycles from profile 1.0 table and then could update it to device by their fixup hooks. Since driver get octal DTR read opcode and then set read settings, expose spi_nor_set_read_settings() in core.h. Signed-off-by: Mason Yang --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 16 +++++++ drivers/mtd/spi-nor/sfdp.c | 106 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1ab4386..3799417 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2204,7 +2204,7 @@ static int spi_nor_check(struct spi_nor *nor) return 0; } -static void +void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7a36b22..a33f807 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -191,6 +191,12 @@ struct spi_nor_locking_ops { * @size: the flash memory density in bytes. * @page_size: the page size of the SPI NOR flash memory. * @octal_max_speed: maximum operation speed of device in octal mode. + * @rdsr_dummy: dummy cycles needed for Read Status Register command. + * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register + * command. + * @rd_reg_cmd: read volatile register command for xSPI device. + * @wr_reg_cmd: write volatile register command for xSPI device. + * @dummy_cycles: dummy cycles used for various frequencies * @hwcaps: describes the read and page program hardware * capabilities. * @reads: read capabilities ordered by priority: the higher index @@ -214,6 +220,11 @@ struct spi_nor_flash_parameter { u64 size; u32 page_size; u16 octal_max_speed; + u8 rdsr_dummy; + u8 rdsr_addr_nbytes; + u8 rd_reg_cmd; + u8 wr_reg_cmd; + u8 dummy_cycles; struct spi_nor_hwcaps hwcaps; struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; @@ -420,6 +431,11 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, int spi_nor_hwcaps_read2cmd(u32 hwcaps); u8 spi_nor_convert_3to4_read(u8 opcode); +void spi_nor_set_read_settings(struct spi_nor_read_command *read, + u8 num_mode_clocks, + u8 num_wait_states, + u8 opcode, + enum spi_nor_protocol proto); void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, enum spi_nor_protocol proto); diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 4d13f66..27a4de4 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -20,6 +20,7 @@ #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */ +#define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 table. */ #define SFDP_SIGNATURE 0x50444653U #define SFDP_JESD216_MAJOR 1 @@ -27,6 +28,27 @@ #define SFDP_JESD216A_MINOR 5 #define SFDP_JESD216B_MINOR 6 +/* xSPI Profile 1.0 table (from JESD216D.01). */ +#define XSPI_PF1_DWORD1_RD_CMD GENMASK(15, 8) +#define XSPI_PF1_DWORD1_RDSR_ADDR_BYTES BIT(29) +#define XSPI_PF1_DWORD1_RDSR_DUMMY_CYCLES BIT(28) +#define XSPI_PF1_DWORD2_RD_REG_CMD GENMASK(31, 24) +#define XSPI_PF1_DWORD2_WR_REG_CMD GENMASK(15, 8) +#define XSPI_PF1_DUMMY_CYCLES_DEFAULT 20 +#define XSPI_DWORD(x) ((x) - 1) +#define XSPI_DWORD_MAX 5 + +struct sfdp_xspi { + u32 dwords[XSPI_DWORD_MAX]; +}; + +struct xspi_dummy_cycles { + u16 speed_hz; /* Speed MHz */ + u8 dwords; /* Dwords index */ + u32 mask; /* Mask */ + u8 shift; /* Bit shift */ +}; + /* Basic Flash Parameter Table 20th DWORD, Max operation speed of device */ struct octal_max_speed { u8 idx; /* Bits value */ @@ -1117,6 +1139,86 @@ static int spi_nor_parse_4bait(struct spi_nor *nor, } /** + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table + * @nor: pointer to a 'struct spi_nor' + * @param_header: xspi profile 1 parameter table header + * @params: pointer to the 'struct spi_nor_flash_parameter' to be. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_parse_profile1(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + struct spi_nor_flash_parameter *params) +{ + struct sfdp_xspi pfile1; + u8 opcode; + u32 i, addr; + size_t len; + int ret; + static const struct xspi_dummy_cycles dummy[] = { + /* {MHz, Dwords index, Mask, Bit shift} */ + { 200, 4, GENMASK(11, 7), 7}, + { 166, 5, GENMASK(31, 27), 27}, + { 133, 5, GENMASK(21, 17), 17}, + { 100, 5, GENMASK(11, 7), 7}, + }; + + if (header->major != SFDP_JESD216_MAJOR || + header->length < XSPI_DWORD_MAX) + return -EINVAL; + + len = min_t(size_t, sizeof(pfile1), + header->length * sizeof(u32)); + + memset(&pfile1, 0, sizeof(pfile1)); + + addr = SFDP_PARAM_HEADER_PTP(header); + ret = spi_nor_read_sfdp(nor, addr, len, &pfile1); + if (ret) + goto out; + + /* Fix endianness of the xSPI 1.0 DWORDs. */ + le32_to_cpu_array(pfile1.dwords, XSPI_DWORD_MAX); + + /* Get 8D-8D-8D fast read opcode and dummy cycles. */ + opcode = FIELD_GET(XSPI_PF1_DWORD1_RD_CMD, + pfile1.dwords[XSPI_DWORD(1)]); + + if (pfile1.dwords[XSPI_DWORD(1)] & XSPI_PF1_DWORD1_RDSR_ADDR_BYTES) + params->rdsr_addr_nbytes = 4; + else + params->rdsr_addr_nbytes = 0; + + if (pfile1.dwords[XSPI_DWORD(1)] & XSPI_PF1_DWORD1_RDSR_DUMMY_CYCLES) + params->rdsr_dummy = 8; + else + params->rdsr_dummy = 4; + + params->rd_reg_cmd = FIELD_GET(XSPI_PF1_DWORD2_RD_REG_CMD, + pfile1.dwords[XSPI_DWORD(2)]); + params->wr_reg_cmd = FIELD_GET(XSPI_PF1_DWORD2_WR_REG_CMD, + pfile1.dwords[XSPI_DWORD(2)]); + + /* according to BFPT 20th DOWRD to get devices dummy cycles */ + for (i = 0; i < ARRAY_SIZE(dummy); i++) { + if (params->octal_max_speed == dummy[i].speed_hz) { + params->dummy_cycles = (dummy[i].mask & + pfile1.dwords[XSPI_DWORD(dummy[i].dwords)]) >> + dummy[i].shift; + break; + } + } + if (i == ARRAY_SIZE(dummy)) + params->dummy_cycles = XSPI_PF1_DUMMY_CYCLES_DEFAULT; + + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, params->dummy_cycles, + opcode, SNOR_PROTO_8_8_8_DTR); +out: + return ret; +} + +/** * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. * @nor: pointer to a 'struct spi_nor' * @params: pointer to the 'struct spi_nor_flash_parameter' to be @@ -1217,6 +1319,10 @@ int spi_nor_parse_sfdp(struct spi_nor *nor, err = spi_nor_parse_4bait(nor, param_header, params); break; + case SFDP_PROFILE1_ID: + err = spi_nor_parse_profile1(nor, param_header, params); + break; + default: break; } From patchwork Fri May 29 07:36:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 214502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACBD8C433DF for ; Fri, 29 May 2020 07:37:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 960442074D for ; Fri, 29 May 2020 07:37:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726788AbgE2HhT (ORCPT ); Fri, 29 May 2020 03:37:19 -0400 Received: from twhmllg4.macronix.com ([211.75.127.132]:24828 "EHLO TWHMLLG4.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726774AbgE2HhT (ORCPT ); Fri, 29 May 2020 03:37:19 -0400 Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG4.macronix.com with ESMTP id 04T7aHq2067318; Fri, 29 May 2020 15:36:22 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, tudor.ambarus@microchip.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, boris.brezillon@collabora.com, matthias.bgg@gmail.com Cc: p.yadav@ti.com, juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang Subject: [PATCH v4 6/7] spi: mxic: patch for octal DTR mode support Date: Fri, 29 May 2020 15:36:14 +0800 Message-Id: <1590737775-4798-7-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> References: <1590737775-4798-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG4.macronix.com 04T7aHq2067318 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Driver patch for octal 8D-8D-8D mode support. Signed-off-by: Mason Yang --- drivers/spi/spi-mxic.c | 98 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 32 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 69491f3..a9b3817 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -280,10 +280,55 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op) +{ + u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | + OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | + (op->cmd.dtr ? OP_CMD_DDR : 0); + + if (op->addr.nbytes) + cfg |= OP_ADDR_BYTES(op->addr.nbytes) | + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | + (op->addr.dtr ? OP_ADDR_DDR : 0); + + if (op->dummy.nbytes) + cfg |= OP_DUMMY_CYC(op->dummy.nbytes); + + if (op->data.nbytes) { + cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | + (op->data.dtr ? OP_DATA_DDR : 0); + if (op->data.dir == SPI_MEM_DATA_IN) + cfg |= OP_READ; + } + + return cfg; +} + +static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags) +{ + struct mxic_spi *mxic = spi_master_get_devdata(spi->master); + int nio = 1; + + if (spi->mode & (SPI_RX_OCTAL | SPI_TX_OCTAL)) + nio = 8; + else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) + nio = 4; + else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) + nio = 2; + + writel(flags | HC_CFG_NIO(nio) | + HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1), + mxic->regs + HC_CFG); +} + static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, void *rxbuf, unsigned int len) { unsigned int pos = 0; + bool dtr_enabled; + + dtr_enabled = (readl(mxic->regs + SS_CTRL(0)) & OP_DATA_DDR); while (pos < len) { unsigned int nbytes = len - pos; @@ -302,6 +347,9 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, if (ret) return ret; + if (dtr_enabled && len & 0x1) + nbytes++; + writel(data, mxic->regs + TXD(nbytes % 4)); if (rxbuf) { @@ -319,6 +367,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, data = readl(mxic->regs + RXD); data >>= (8 * (4 - nbytes)); + if (dtr_enabled && len & 0x1) + nbytes++; memcpy(rxbuf + pos, &data, nbytes); WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); } else { @@ -335,8 +385,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->data.buswidth > 4 || op->addr.buswidth > 4 || - op->dummy.buswidth > 4 || op->cmd.buswidth > 4) + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) return false; if (op->data.nbytes && op->dummy.nbytes && @@ -346,6 +396,9 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem, if (op->addr.nbytes > 7) return false; + if (op->cmd.buswidth == 8 && op->cmd.nbytes == 2) + return true; + return spi_mem_default_supports_op(mem, op); } @@ -353,47 +406,27 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); - int nio = 1, i, ret; - u32 ss_ctrl; - u8 addr[8]; + int i, ret; + u8 addr[8], cmd[2]; ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); if (ret) return ret; - if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) - nio = 4; - else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) - nio = 2; + mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN); - writel(HC_CFG_NIO(nio) | - HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) | - HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) | - HC_CFG_MAN_CS_EN, - mxic->regs + HC_CFG); writel(HC_EN_BIT, mxic->regs + HC_EN); - ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1); - - if (op->addr.nbytes) - ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) | - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1); - - if (op->dummy.nbytes) - ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes); - - if (op->data.nbytes) { - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1); - if (op->data.dir == SPI_MEM_DATA_IN) - ss_ctrl |= OP_READ; - } - - writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select)); + writel(mxic_spi_mem_prep_op_cfg(op), + mxic->regs + SS_CTRL(mem->spi->chip_select)); writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, mxic->regs + HC_CFG); - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1); + for (i = 0; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1)); + + ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); if (ret) goto out; @@ -566,7 +599,8 @@ static int mxic_spi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_MASK(8); master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_TX_DUAL | - SPI_RX_QUAD | SPI_TX_QUAD; + SPI_RX_QUAD | SPI_TX_QUAD | + SPI_RX_OCTAL | SPI_TX_OCTAL; mxic_spi_hw_init(mxic);