From patchwork Fri Mar 6 20:57:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 214214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F481C10F26 for ; Fri, 6 Mar 2020 20:57:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 530C820709 for ; Fri, 6 Mar 2020 20:57:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=walle.cc header.i=@walle.cc header.b="U6Vuut1g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726185AbgCFU5P (ORCPT ); Fri, 6 Mar 2020 15:57:15 -0500 Received: from ssl.serverraum.org ([176.9.125.105]:39199 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbgCFU5P (ORCPT ); Fri, 6 Mar 2020 15:57:15 -0500 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id B4FAE23E5A; Fri, 6 Mar 2020 21:57:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1583528233; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=q71VaiFL5GD6eAxeUMfKSm1S1jRZh0ImWHYLWUEuk7M=; b=U6Vuut1gkukNxqHcH3uDUmvg/44I6feqkj5Vzwckf3+eWRtxjpPeW0Y4EDCm1yNRI/htNf 7xBkb+CYeGTnMrzwVyPU8dzck8TulnOhsNpKVA+M5cMBba05stpsvvQr5a/RBsCoub8YoZ 6lmXyyBTqMWmEW1tg+hbgbR0rZdjqv8= From: Michael Walle To: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Shawn Guo , Li Yang , Michael Walle , Rob Herring Subject: [PATCH 1/2] dt-bindings: serial: lpuart: add ls1028a compatibility Date: Fri, 6 Mar 2020 21:57:02 +0100 Message-Id: <20200306205703.30634-1-michael@walle.cc> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Spamd-Bar: ++++++ X-Rspamd-Server: web X-Rspamd-Queue-Id: B4FAE23E5A X-Spamd-Result: default: False [6.40 / 15.00]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TAGGED_RCPT(0.00)[dt]; MIME_GOOD(-0.10)[text/plain]; BROKEN_CONTENT_TYPE(1.50)[]; NEURAL_SPAM(0.00)[0.535]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DKIM_SIGNED(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; MID_CONTAINS_FROM(1.00)[]; RCVD_COUNT_ZERO(0.00)[0]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:31334, ipnet:2a02:810c:8000::/33, country:DE]; SUSPICIOUS_RECIPS(1.50)[] X-Spam: Yes Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Signed-off-by: Michael Walle Reviewed-by: Rob Herring --- .../devicetree/bindings/serial/fsl-lpuart.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c904e2e68332..e7448b92dd9d 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,ls1028a-lpuart" for lpuart compatible with the one integrated + on LS1028A SoC with 32-bit little-endian register organization - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated on i.MX7ULP SoC with 32-bit little-endian register organization - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated @@ -15,10 +17,10 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names -- clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud - clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access - lpuart controller registers, it also requires "baud" clock for module to - receive/transmit data. +- clock-names : For vf610/ls1021a/ls1028a/imx7ulp, "ipg" clock is for uart + bus/baud clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used + to access lpuart controller registers, it also requires "baud" clock for + module to receive/transmit data. Optional properties: - dmas: A list of two dma specifiers, one for each entry in dma-names.