From patchwork Thu Jun 4 10:13:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 213940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33E35C433DF for ; Thu, 4 Jun 2020 10:13:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13BA62074B for ; Thu, 4 Jun 2020 10:13:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="UIQtNB2N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728019AbgFDKNW (ORCPT ); Thu, 4 Jun 2020 06:13:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728005AbgFDKNV (ORCPT ); Thu, 4 Jun 2020 06:13:21 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F73BC08C5C0 for ; Thu, 4 Jun 2020 03:13:20 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id c11so6571877ljn.2 for ; Thu, 04 Jun 2020 03:13:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=WUmyTqxSfskM62xuisvKT7kgxPPBRtPkhWKMRB3p5tM=; b=UIQtNB2NQwTL6Nr699IX6cXcWtvFF+bvXPkCRURE8M7j5xtFCr28b919++lOSss6nv Ygr3gRXgzyrYHxJHZPj3/WoWgmX1q4o4Tu6QzsaQwPFVwJ4ejgZyef+t1l2Z6QiGBosq 9JfINGMU9pztizvzzANuZLkn/n3jRZxIVpQh0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WUmyTqxSfskM62xuisvKT7kgxPPBRtPkhWKMRB3p5tM=; b=uYQRYpKNbKPcSy16CUh7T/xSdTOI1Ant97IB7THKMc4XQHHRhBAL4TIb7UYSOpjAPC HqHQE2ZVk/otZEnQKJ2OwjPrcPk8NWd2n7SBNnjJKommpH/DwGJ3rNXd43PZYHf4OH7h Do4FaUMPYlrSVRSozVdV7dI7accvpEUQF9Wv+vfhkR2kUoQEcT/cd3Nn075pAjUeQDwC ptE521nkzdtK+E6MF8OIPQTEOPL21KpSjqwJiGpqaXn9QVNo82rLeX7VUhV4La/F8p6X DMCMuHwkGskfTHV/lYLw4dJQFMosLtjQI0yKXwss8Clk5Hsng+91A2cCt1BhyFnDEDzQ dtRw== X-Gm-Message-State: AOAM533GmZsmRAhO2k0P+C4h9EWb7/6b+nFnpVytLG2lo61NLEdSeSvh h1o6RJbiLv8+EC8xFaJ6bjujJg== X-Google-Smtp-Source: ABdhPJzhna3WAOIKLBaalRS3fGtym65ULihde2dV23JDTe/SV7Hmo1UgLnQB16v5MguATD5wzDVwRQ== X-Received: by 2002:a2e:b4e7:: with SMTP id s7mr1689284ljm.336.1591265598323; Thu, 04 Jun 2020 03:13:18 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id w144sm1363613lff.67.2020.06.04.03.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 03:13:17 -0700 (PDT) Date: Thu, 4 Jun 2020 12:13:12 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v7 1/5] dt-bindings: vendor: add vendor prefix for LiteX Message-ID: <20200604121142.2964437-1-mholenko@antmicro.com> References: <20200604121142.2964437-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200604121142.2964437-0-mholenko@antmicro.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski Add vendor prefix for LiteX SoC builder. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko Acked-by: Rob Herring --- Notes: No changes in v7. No changes in v6. No changes in v5. No changes in v4. Changes in v3: - added Acked-by tag No changes in v2. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 997934c58f9a..d2eaddc473ac 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -575,6 +575,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^litex,.*": + description: LiteX SoC builder "^lltc,.*": description: Linear Technology Corporation "^logicpd,.*": From patchwork Thu Jun 4 10:13:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 213939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 373B9C433E1 for ; Thu, 4 Jun 2020 10:13:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0DFE72075B for ; Thu, 4 Jun 2020 10:13:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="iMT/qgf3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728156AbgFDKN6 (ORCPT ); Thu, 4 Jun 2020 06:13:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727082AbgFDKN6 (ORCPT ); Thu, 4 Jun 2020 06:13:58 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0528DC03E96D for ; Thu, 4 Jun 2020 03:13:57 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id c11so6573796ljn.2 for ; Thu, 04 Jun 2020 03:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=biGaeORybU3iINe4rEXJqVRTixR9WDvwkNhPfWmjX4M=; b=iMT/qgf3EDzw8ORndXdQzAxpu3k8eykyqF42UOv4eC/DNY7Z+I3VPUkLBc5vooEe/U Sw9pt1SJWW5/h6RTCeiNNZC9O0/ZGOJy/yGuC2b4WIkL8GKT+GUCMm0vOh9iUvZbDJ1p PrSXOw2gZ4mkZbClK8lLpfgfiRYcZFK3As4rc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=biGaeORybU3iINe4rEXJqVRTixR9WDvwkNhPfWmjX4M=; b=eNeDSWwF04oVJRsZHUrjCFSgW7GkD/hQF3C6X76a29JAt8/0PNhVyOiwrnbgcaqr2H ipQj5kRM4gayluvtMyRrS9HjfTAWG2pLwYncDQRhsdxVPXfaGQlR6WcWE2TSuwrXyR3t NwOb4ji5geRLXd+E+IjpMC/1cWhwewtz9dFKhsnNmoB0XDbaJoHUdAKz0hIHcag6n3P7 kSiP7PHMjKM+Y2C5CJPAt5UBB1hvSUUwtaMnFf4kebrw7nJeESKmxGN/SJv8Yc28nYEG urf2ul1RiGhcPkRrjyh4Ag2Ab8qmCL2ceUEsLnDqYmFBX4ppMVoEb6iK44GNq+iNM4kt f9zw== X-Gm-Message-State: AOAM530CsKeatw7eG1tYwL2UEXlMAtfhGIaYPugQVl5PQYLEc2xZdPCh pleEx07ztUnWNnoeOoxyk/l7oQ== X-Google-Smtp-Source: ABdhPJyvrnpDO5h0qw1XwgvIURHMrKD08Wb3AYrR0F5X6YLTrGUEMygGuaDDuS+QtACzt3LZrjXENw== X-Received: by 2002:a05:651c:3d0:: with SMTP id f16mr1746118ljp.7.1591265635209; Thu, 04 Jun 2020 03:13:55 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id a1sm1647667lfi.36.2020.06.04.03.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 03:13:54 -0700 (PDT) Date: Thu, 4 Jun 2020 12:13:49 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v7 3/5] drivers/soc/litex: add LiteX SoC Controller driver Message-ID: <20200604121142.2964437-3-mholenko@antmicro.com> References: <20200604121142.2964437-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200604121142.2964437-0-mholenko@antmicro.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Pawel Czarnecki This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder. Co-developed-by: Mateusz Holenko Signed-off-by: Mateusz Holenko Signed-off-by: Pawel Czarnecki --- Notes: No changes in v7. Changes in v6: - added dependency on OF || COMPILE_TEST - used le32_to_cpu(readl(addr)) instead of __raw_readl and writel(cpu_to_le32(value), addr) instead of __raw_writel to take advantage of memory barriers provided by readl/writel Changes in v5: - removed helper accessors and used __raw_readl/__raw_writel instead - fixed checking for errors in litex_soc_ctrl_probe Changes in v4: - fixed indent in Kconfig's help section - fixed copyright header - changed compatible to "litex,soc-controller" - simplified litex_soc_ctrl_probe - removed unnecessary litex_soc_ctrl_remove This commit has been introduced in v3 of the patchset. It includes a simplified version of common 'litex.h' header introduced in v2 of the patchset. MAINTAINERS | 2 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/litex/Kconfig | 15 +++ drivers/soc/litex/Makefile | 3 + drivers/soc/litex/litex_soc_ctrl.c | 197 +++++++++++++++++++++++++++++ include/linux/litex.h | 45 +++++++ 7 files changed, 264 insertions(+) create mode 100644 drivers/soc/litex/Kconfig create mode 100644 drivers/soc/litex/Makefile create mode 100644 drivers/soc/litex/litex_soc_ctrl.c create mode 100644 include/linux/litex.h diff --git a/MAINTAINERS b/MAINTAINERS index e3f8804c08d7..b6d926a6ed04 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9923,6 +9923,8 @@ M: Karol Gugala M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml +F: drivers/soc/litex/litex_soc_ctrl.c +F: include/linux/litex.h LIVE PATCHING M: Josh Poimboeuf diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..d097d070f579 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..0b16108823ef 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_GEMINI) += gemini/ obj-y += imx/ obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/litex/Kconfig b/drivers/soc/litex/Kconfig new file mode 100644 index 000000000000..c974ec3846bc --- /dev/null +++ b/drivers/soc/litex/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License_Identifier: GPL-2.0 + +menu "Enable LiteX SoC Builder specific drivers" + +config LITEX_SOC_CONTROLLER + tristate "Enable LiteX SoC Controller driver" + depends on OF || COMPILE_TEST + help + This option enables the SoC Controller Driver which verifies + LiteX CSR access and provides common litex_get_reg/litex_set_reg + accessors. + All drivers that use functions from litex.h must depend on + LITEX_SOC_CONTROLLER. + +endmenu diff --git a/drivers/soc/litex/Makefile b/drivers/soc/litex/Makefile new file mode 100644 index 000000000000..98ff7325b1c0 --- /dev/null +++ b/drivers/soc/litex/Makefile @@ -0,0 +1,3 @@ +# SPDX-License_Identifier: GPL-2.0 + +obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex_soc_ctrl.o diff --git a/drivers/soc/litex/litex_soc_ctrl.c b/drivers/soc/litex/litex_soc_ctrl.c new file mode 100644 index 000000000000..319be92fc63f --- /dev/null +++ b/drivers/soc/litex/litex_soc_ctrl.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteX SoC Controller Driver + * + * Copyright (C) 2020 Antmicro + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The parameters below are true for LiteX SoC + * configured for 8-bit CSR Bus, 32-bit aligned. + * + * Supporting other configurations will require + * extending the logic in this header. + */ +#define LITEX_REG_SIZE 0x4 +#define LITEX_SUBREG_SIZE 0x1 +#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8) + +static DEFINE_SPINLOCK(csr_lock); + +/* + * LiteX SoC Generator, depending on the configuration, + * can split a single logical CSR (Control & Status Register) + * into a series of consecutive physical registers. + * + * For example, in the configuration with 8-bit CSR Bus, + * 32-bit aligned (the default one for 32-bit CPUs) a 32-bit + * logical CSR will be generated as four 32-bit physical registers, + * each one containing one byte of meaningful data. + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + * + * The purpose of `litex_set_reg`/`litex_get_reg` is to implement + * the logic of writing to/reading from the LiteX CSR in a single + * place that can be then reused by all LiteX drivers. + */ +void litex_set_reg(void __iomem *reg, unsigned long reg_size, + unsigned long val) +{ + unsigned long shifted_data, shift, i; + unsigned long flags; + + spin_lock_irqsave(&csr_lock, flags); + + for (i = 0; i < reg_size; ++i) { + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + shifted_data = val >> shift; + + writel(cpu_to_le32(shifted_data), reg + (LITEX_REG_SIZE * i)); + } + + spin_unlock_irqrestore(&csr_lock, flags); +} + +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_size) +{ + unsigned long shifted_data, shift, i; + unsigned long result = 0; + unsigned long flags; + + spin_lock_irqsave(&csr_lock, flags); + + for (i = 0; i < reg_size; ++i) { + shifted_data = le32_to_cpu(readl(reg + (LITEX_REG_SIZE * i))); + + shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); + result |= (shifted_data << shift); + } + + spin_unlock_irqrestore(&csr_lock, flags); + + return result; +} + +static int accessors_ok; + +/* + * Check if accessors are safe to be used by other drivers + * returns true if yes - false if not + */ +int litex_check_accessors(void) +{ + return accessors_ok; +} + +#define SCRATCH_REG_OFF 0x04 +#define SCRATCH_REG_SIZE 4 +#define SCRATCH_REG_VALUE 0x12345678 +#define SCRATCH_TEST_VALUE 0xdeadbeef + +/* + * Check LiteX CSR read/write access + * + * This function reads and writes a scratch register in order + * to verify if CSR access works. + * + * In case any problems are detected, the driver should panic + * and not set `accessors_ok` flag. As a result no other + * LiteX driver should access CSR bus. + * + * Access to the LiteX CSR is, by design, done in CPU native + * endianness. The driver should not dynamically configure + * access functions when the endianness mismatch is detected. + * Such situation indicates problems in the soft SoC design + * and should be solved at the LiteX generator level, + * not in the software. + */ +static int litex_check_csr_access(void __iomem *reg_addr) +{ + unsigned long reg; + + reg = litex_get_reg(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_SIZE); + + if (reg != SCRATCH_REG_VALUE) { + panic("Scratch register read error! Expected: 0x%x but got: 0x%lx", + SCRATCH_REG_VALUE, reg); + return -EINVAL; + } + + litex_set_reg(reg_addr + SCRATCH_REG_OFF, + SCRATCH_REG_SIZE, SCRATCH_TEST_VALUE); + reg = litex_get_reg(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_SIZE); + + if (reg != SCRATCH_TEST_VALUE) { + panic("Scratch register write error! Expected: 0x%x but got: 0x%lx", + SCRATCH_TEST_VALUE, reg); + return -EINVAL; + } + + /* restore original value of the SCRATCH register */ + litex_set_reg(reg_addr + SCRATCH_REG_OFF, + SCRATCH_REG_SIZE, SCRATCH_REG_VALUE); + + /* Set flag for other drivers */ + accessors_ok = 1; + pr_info("LiteX SoC Controller driver initialized"); + + return 0; +} + +struct litex_soc_ctrl_device { + void __iomem *base; +}; + +static const struct of_device_id litex_soc_ctrl_of_match[] = { + {.compatible = "litex,soc-controller"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, litex_soc_ctrl_of_match); + +static int litex_soc_ctrl_probe(struct platform_device *pdev) +{ + struct device *dev; + struct device_node *node; + struct litex_soc_ctrl_device *soc_ctrl_dev; + + dev = &pdev->dev; + node = dev->of_node; + if (!node) + return -ENODEV; + + soc_ctrl_dev = devm_kzalloc(dev, sizeof(*soc_ctrl_dev), GFP_KERNEL); + if (!soc_ctrl_dev) + return -ENOMEM; + + soc_ctrl_dev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(soc_ctrl_dev->base)) + return PTR_ERR(soc_ctrl_dev->base); + + return litex_check_csr_access(soc_ctrl_dev->base); +} + +static struct platform_driver litex_soc_ctrl_driver = { + .driver = { + .name = "litex-soc-controller", + .of_match_table = of_match_ptr(litex_soc_ctrl_of_match) + }, + .probe = litex_soc_ctrl_probe, +}; + +module_platform_driver(litex_soc_ctrl_driver); +MODULE_DESCRIPTION("LiteX SoC Controller driver"); +MODULE_AUTHOR("Antmicro "); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..f31062436273 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Implementation of the functions is provided by + * the LiteX SoC Controller driver. + * + * Copyright (C) 2019-2020 Antmicro + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include +#include +#include + +/* + * litex_check_accessors is a function implemented in + * drivers/soc/litex/litex_soc_controller.c + * checking if the common LiteX CSR accessors + * are safe to be used by the drivers; + * returns true (1) if yes - false (0) if not + * + * Important: All drivers that use litex_set_reg/litex_get_reg + * functions should make sure that LiteX SoC Controller driver + * has verified LiteX CSRs read and write operations before + * issuing any read/writes to the LiteX peripherals. + * + * Exemplary snippet that can be used at the beginning + * of the driver's probe() function to ensure that LiteX + * SoC Controller driver is properely initialized: + * + * if (!litex_check_accessors()) + * return -EPROBE_DEFER; + */ +int litex_check_accessors(void); + +void litex_set_reg(void __iomem *reg, unsigned long reg_sz, unsigned long val); + +unsigned long litex_get_reg(void __iomem *reg, unsigned long reg_sz); + + +#endif /* _LINUX_LITEX_H */ From patchwork Thu Jun 4 10:14:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateusz Holenko X-Patchwork-Id: 213938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6D6FC433DF for ; Thu, 4 Jun 2020 10:14:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 756E92075B for ; Thu, 4 Jun 2020 10:14:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=antmicro.com header.i=@antmicro.com header.b="GjHIHMft" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728274AbgFDKO2 (ORCPT ); Thu, 4 Jun 2020 06:14:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728054AbgFDKO1 (ORCPT ); Thu, 4 Jun 2020 06:14:27 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 333F4C03E96D for ; Thu, 4 Jun 2020 03:14:27 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id r125so3202749lff.13 for ; Thu, 04 Jun 2020 03:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antmicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=gcrlC09cVVVdVMUgxMwZkpjIi0SrTSHpVlDwpATjvhM=; b=GjHIHMft32ZEHR38oB87tpvBnBF1/cr/pZfATqYNZGoaSfc6t/sDcI0SildMIk6xtX dxuwPy9OuTQ+XioPAXxrdISR5DmI+SO95SoKSCvfgpDx2KM5VtT90GE+deCXfz4FsITp fGvVGZ+UVHU3Fn9HcGn3MNeYZub3Gmgo+2M8Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=gcrlC09cVVVdVMUgxMwZkpjIi0SrTSHpVlDwpATjvhM=; b=a0v6mHr8q7rHPwHLbu9K2q1BBFzQD9sPFcKVSI2CnbTDYtJcnw99vOAZxKdbM9xtXW Z/A265aNayR9d9kZncn9LKEtFblQSRjWgYzJkYtIdo+XxJwPCaPwD5+DBAPWqE6KJ8mC XxK6q4SX0jMfQosvxPPVSgC/Fmvt49QxF2MCa51bCibv6ul+8AlJPm8dV4dvup1Og1vQ WnINks43LPJ0PwMhsE1TtXftyZkoP8zLUxsad9l7hMlyYuDK/EEdmnk3KxduQNoMwb9n Br1uL9ht2YvFMBQ1OwEep0GuBS+meLVoUBEEgQxuNOkvLxnZ7csqF65Ldmmq5nn2+/7P RrPg== X-Gm-Message-State: AOAM532J2psprgfCfdmCMshkQXJWkmX4NeI33WhqjmLDje5tt5iy1+nD o+orkbGUCZ6Aacebe2ZB5OSZgg== X-Google-Smtp-Source: ABdhPJxcHo2Cd7GkKhdfJLbX4foVCHLjKklr1S49J6SfrXZTmZqIIht6UhBw1NgXnEmSFbbDAkZnyw== X-Received: by 2002:a05:6512:488:: with SMTP id v8mr2144423lfq.205.1591265665545; Thu, 04 Jun 2020 03:14:25 -0700 (PDT) Received: from localhost.localdomain (d79-196.icpnet.pl. [77.65.79.196]) by smtp.gmail.com with ESMTPSA id s28sm1357348lfs.3.2020.06.04.03.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jun 2020 03:14:24 -0700 (PDT) Date: Thu, 4 Jun 2020 12:14:19 +0200 From: Mateusz Holenko To: Rob Herring , Mark Rutland , Greg Kroah-Hartman , Jiri Slaby , devicetree@vger.kernel.org, linux-serial@vger.kernel.org Cc: Stafford Horne , Karol Gugala , Mateusz Holenko , Mauro Carvalho Chehab , "David S. Miller" , "Paul E. McKenney" , Filip Kokosinski , Pawel Czarnecki , Joel Stanley , Jonathan Cameron , Maxime Ripard , Shawn Guo , Heiko Stuebner , Sam Ravnborg , Icenowy Zheng , Laurent Pinchart , linux-kernel@vger.kernel.org, "Gabriel L. Somlo" Subject: [PATCH v7 5/5] drivers/tty/serial: add LiteUART driver Message-ID: <20200604121142.2964437-5-mholenko@antmicro.com> References: <20200604121142.2964437-0-mholenko@antmicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200604121142.2964437-0-mholenko@antmicro.com> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Filip Kokosinski This commit adds driver for the FPGA-based LiteUART serial controller from LiteX SoC builder. The current implementation supports LiteUART configured for 32 bit data width and 8 bit CSR bus width. It does not support IRQ. Signed-off-by: Filip Kokosinski Signed-off-by: Mateusz Holenko --- Notes: Changed in v7: - added missing include directive Changes in v6: - LiteUART ports now stored in xArray - removed PORT_LITEUART - fixed formatting - removed some unnecessary defines No changes in v5. Changes in v4: - fixed copyright header - removed a wrong dependency on UARTLITE from Kconfig - added a dependency on LITEX_SOC_CONTROLLER to LITEUART in Kconfig Changes in v3: - aliases made optional - used litex_get_reg/litex_set_reg functions instead of macros - SERIAL_LITEUART_NR_PORTS renamed to SERIAL_LITEUART_MAX_PORTS - PORT_LITEUART changed from 122 to 123 - added dependency on LITEX_SOC_CONTROLLER - patch number changed from 4 to 5 No changes in v2. MAINTAINERS | 1 + drivers/tty/serial/Kconfig | 31 +++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/liteuart.c | 405 ++++++++++++++++++++++++++++++++++ 4 files changed, 438 insertions(+) create mode 100644 drivers/tty/serial/liteuart.c diff --git a/MAINTAINERS b/MAINTAINERS index b6d926a6ed04..d06d099aa56f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9924,6 +9924,7 @@ M: Mateusz Holenko S: Maintained F: Documentation/devicetree/bindings/*/litex,*.yaml F: drivers/soc/litex/litex_soc_ctrl.c +F: drivers/tty/serial/liteuart.c F: include/linux/litex.h LIVE PATCHING diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index adf9e80e7dc9..17aaf0afb27a 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1562,6 +1562,37 @@ config SERIAL_MILBEAUT_USIO_CONSOLE receives all kernel messages and warnings and which allows logins in single user mode). +config SERIAL_LITEUART + tristate "LiteUART serial port support" + depends on HAS_IOMEM + depends on OF || COMPILE_TEST + depends on LITEX_SOC_CONTROLLER + select SERIAL_CORE + help + This driver is for the FPGA-based LiteUART serial controller from LiteX + SoC builder. + + Say 'Y' here if you wish to use the LiteUART serial controller. + Otherwise, say 'N'. + +config SERIAL_LITEUART_MAX_PORTS + int "Maximum number of LiteUART ports" + depends on SERIAL_LITEUART + default "1" + help + Set this to the maximum number of serial ports you want the driver + to support. + +config SERIAL_LITEUART_CONSOLE + bool "LiteUART serial port console support" + depends on SERIAL_LITEUART=y + select SERIAL_CORE_CONSOLE + help + Say 'Y' here if you wish to use the FPGA-based LiteUART serial controller + from LiteX SoC builder as the system console (the system console is the + device which receives all kernel messages and warnings and which allows + logins in single user mode). Otherwise, say 'N'. + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index d056ee6cca33..9f8ba419ff3b 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o +obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/liteuart.c b/drivers/tty/serial/liteuart.c new file mode 100644 index 000000000000..b90e51fad281 --- /dev/null +++ b/drivers/tty/serial/liteuart.c @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LiteUART serial controller (LiteX) Driver + * + * Copyright (C) 2019-2020 Antmicro + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * CSRs definitions (base address offsets + width) + * + * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus, + * 32-bit aligned. + * + * Supporting other configurations might require new definitions or a more + * generic way of indexing the LiteX CSRs. + * + * For more details on how CSRs are defined and handled in LiteX, see comments + * in the LiteX SoC Driver: drivers/soc/litex/litex_soc_ctrl.c + */ +#define OFF_RXTX 0x00 +#define OFF_TXFULL 0x04 +#define OFF_RXEMPTY 0x08 +#define OFF_EV_STATUS 0x0c +#define OFF_EV_PENDING 0x10 +#define OFF_EV_ENABLE 0x14 + +/* events */ +#define EV_TX 0x1 +#define EV_RX 0x2 + +struct liteuart_port { + struct uart_port port; + struct timer_list timer; +}; + +#define to_liteuart_port(port) container_of(port, struct liteuart_port, port) + +static DEFINE_XARRAY_FLAGS(liteuart_array, XA_FLAGS_ALLOC); + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE +static struct console liteuart_console; +#endif + +static struct uart_driver liteuart_driver = { + .owner = THIS_MODULE, + .driver_name = "liteuart", + .dev_name = "ttyLXU", + .major = 0, + .minor = 0, + .nr = CONFIG_SERIAL_LITEUART_MAX_PORTS, +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + .cons = &liteuart_console, +#endif +}; + +static void liteuart_timer(struct timer_list *t) +{ + struct liteuart_port *uart = from_timer(uart, t, timer); + struct uart_port *port = &uart->port; + unsigned char __iomem *membase = port->membase; + unsigned int flg = TTY_NORMAL; + int ch; + unsigned long status; + + while ((status = !litex_get_reg(membase + OFF_RXEMPTY, 1)) == 1) { + ch = litex_get_reg(membase + OFF_RXTX, 1); + port->icount.rx++; + + /* necessary for RXEMPTY to refresh its value */ + litex_set_reg(membase + OFF_EV_PENDING, 1, EV_TX | EV_RX); + + /* no overflow bits in status */ + if (!(uart_handle_sysrq_char(port, ch))) + uart_insert_char(port, status, 0, ch, flg); + + tty_flip_buffer_push(&port->state->port); + } + + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); +} + +static void liteuart_putchar(struct uart_port *port, int ch) +{ + while (litex_get_reg(port->membase + OFF_TXFULL, 1)) + cpu_relax(); + + litex_set_reg(port->membase + OFF_RXTX, 1, ch); +} + +static unsigned int liteuart_tx_empty(struct uart_port *port) +{ + /* not really tx empty, just checking if tx is not full */ + if (!litex_get_reg(port->membase + OFF_TXFULL, 1)) + return TIOCSER_TEMT; + + return 0; +} + +static void liteuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* modem control register is not present in LiteUART */ +} + +static unsigned int liteuart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; +} + +static void liteuart_stop_tx(struct uart_port *port) +{ +} + +static void liteuart_start_tx(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + unsigned char ch; + + if (unlikely(port->x_char)) { + litex_set_reg(port->membase + OFF_RXTX, 1, port->x_char); + port->icount.tx++; + port->x_char = 0; + } else if (!uart_circ_empty(xmit)) { + while (xmit->head != xmit->tail) { + ch = xmit->buf[xmit->tail]; + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + liteuart_putchar(port, ch); + } + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static void liteuart_stop_rx(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* just delete timer */ + del_timer(&uart->timer); +} + +static void liteuart_break_ctl(struct uart_port *port, int break_state) +{ + /* LiteUART doesn't support sending break signal */ +} + +static int liteuart_startup(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* disable events */ + litex_set_reg(port->membase + OFF_EV_ENABLE, 1, 0); + + /* prepare timer for polling */ + timer_setup(&uart->timer, liteuart_timer, 0); + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + + return 0; +} + +static void liteuart_shutdown(struct uart_port *port) +{ +} + +static void liteuart_set_termios(struct uart_port *port, struct ktermios *new, + struct ktermios *old) +{ + unsigned int baud; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + /* update baudrate */ + baud = uart_get_baud_rate(port, new, old, 0, 460800); + uart_update_timeout(port, new->c_cflag, baud); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *liteuart_type(struct uart_port *port) +{ + return "liteuart"; +} + +static void liteuart_release_port(struct uart_port *port) +{ +} + +static int liteuart_request_port(struct uart_port *port) +{ + return 0; +} + +static void liteuart_config_port(struct uart_port *port, int flags) +{ + /* + * Driver core for serial ports forces a non-zero value for port type. + * Write an arbitrary value here to accommodate the serial core driver, + * as ID part of UAPI is redundant. + */ + port->type = 1; +} + +static int liteuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (port->type != PORT_UNKNOWN && ser->type != 1) + return -EINVAL; + + return 0; +} + +static const struct uart_ops liteuart_ops = { + .tx_empty = liteuart_tx_empty, + .set_mctrl = liteuart_set_mctrl, + .get_mctrl = liteuart_get_mctrl, + .stop_tx = liteuart_stop_tx, + .start_tx = liteuart_start_tx, + .stop_rx = liteuart_stop_rx, + .break_ctl = liteuart_break_ctl, + .startup = liteuart_startup, + .shutdown = liteuart_shutdown, + .set_termios = liteuart_set_termios, + .type = liteuart_type, + .release_port = liteuart_release_port, + .request_port = liteuart_request_port, + .config_port = liteuart_config_port, + .verify_port = liteuart_verify_port, +}; + +static int liteuart_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct liteuart_port *uart; + struct uart_port *port; + struct xa_limit limit; + int dev_id, ret; + + /* no device tree */ + if (!np) + return -ENODEV; + + if (!litex_check_accessors()) + return -EPROBE_DEFER; + + /* look for aliases; auto-enumerate for free index if not found */ + dev_id = of_alias_get_id(np, "serial"); + if (dev_id < 0) + limit = XA_LIMIT(0, CONFIG_SERIAL_LITEUART_MAX_PORTS); + else + limit = XA_LIMIT(dev_id, dev_id); + + uart = kzalloc(sizeof(struct liteuart_port), GFP_KERNEL); + if (!uart) + return -ENOMEM; + + ret = xa_alloc(&liteuart_array, &dev_id, uart, limit, GFP_KERNEL); + if (ret) + return ret; + + port = &uart->port; + + /* get membase */ + port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (!port->membase) + return -ENXIO; + + /* values not from device tree */ + port->dev = &pdev->dev; + port->iotype = UPIO_MEM; + port->flags = UPF_BOOT_AUTOCONF; + port->ops = &liteuart_ops; + port->regshift = 2; + port->fifosize = 16; + port->iobase = 1; + port->type = PORT_UNKNOWN; + port->line = dev_id; + spin_lock_init(&port->lock); + + return uart_add_one_port(&liteuart_driver, &uart->port); +} + +static int liteuart_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id liteuart_of_match[] = { + { .compatible = "litex,liteuart" }, + {} +}; +MODULE_DEVICE_TABLE(of, liteuart_of_match); + +static struct platform_driver liteuart_platform_driver = { + .probe = liteuart_probe, + .remove = liteuart_remove, + .driver = { + .name = "liteuart", + .of_match_table = liteuart_of_match, + }, +}; + +#ifdef CONFIG_SERIAL_LITEUART_CONSOLE + +static void liteuart_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct liteuart_port *uart; + struct uart_port *port; + unsigned long flags; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + port = &uart->port; + + spin_lock_irqsave(&port->lock, flags); + uart_console_write(port, s, count, liteuart_putchar); + spin_unlock_irqrestore(&port->lock, flags); +} + +static int liteuart_console_setup(struct console *co, char *options) +{ + struct liteuart_port *uart; + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); + if (!uart) + return -ENODEV; + + port = &uart->port; + if (!port->membase) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console liteuart_console = { + .name = "liteuart", + .write = liteuart_console_write, + .device = uart_console_device, + .setup = liteuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &liteuart_driver, +}; + +static int __init liteuart_console_init(void) +{ + register_console(&liteuart_console); + + return 0; +} +console_initcall(liteuart_console_init); +#endif /* CONFIG_SERIAL_LITEUART_CONSOLE */ + +static int __init liteuart_init(void) +{ + int res; + + res = uart_register_driver(&liteuart_driver); + if (res) + return res; + + res = platform_driver_register(&liteuart_platform_driver); + if (res) { + uart_unregister_driver(&liteuart_driver); + return res; + } + + return 0; +} + +static void __exit liteuart_exit(void) +{ + platform_driver_unregister(&liteuart_platform_driver); + uart_unregister_driver(&liteuart_driver); +} + +module_init(liteuart_init); +module_exit(liteuart_exit); + +MODULE_AUTHOR("Antmicro "); +MODULE_DESCRIPTION("LiteUART serial driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform: liteuart");