From patchwork Tue Mar 10 19:48:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 213535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BD67C10DCE for ; Tue, 10 Mar 2020 19:49:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3561D208E4 for ; Tue, 10 Mar 2020 19:49:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TMgpPbxw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727112AbgCJTta (ORCPT ); Tue, 10 Mar 2020 15:49:30 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43033 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTt3 (ORCPT ); Tue, 10 Mar 2020 15:49:29 -0400 Received: by mail-pf1-f194.google.com with SMTP id c144so6973584pfb.10; Tue, 10 Mar 2020 12:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x7SlQ0bsHgZszwUhHBadIYsQ2+v9rQS255Bp3qcZsTY=; b=TMgpPbxw0ko1PC3JxLulVtx+EOtLWWSi8eXOYfPX2GTCpCdg/2lBdl98IKRRz0wAl9 IoedTvSKkzCXBvqx5h1q3KndXz802MaIrSE9GolGUs+oSaC9vCe1dRkMUzq2axRyiJnX j+oXEAIEvIAKugR+isAITSQIptoiGEUUg3W7bjQJrqoHScpWtGRl/f2HSEN3u3/eWRDx ZkbrwCYemc7nuKSphAFtpDszAPf9sjlfhfRnnS1VNTNb/B4WuuxClKLMVnf96/w2CBFU Y2XKEeI/nwSLzWsq0Otj1JC28ETShWQNQuHb/V6u9uAmFkZASm/IaXpqIKYzDrPqqAY5 SzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x7SlQ0bsHgZszwUhHBadIYsQ2+v9rQS255Bp3qcZsTY=; b=symvPdsC2NFHNooUAwKkVT1Lzlj9kIXuCatfudc3eymBQJtfz7MAQlkDfZh4CaS2B+ co5FThAzOfWBElZQOd4ZKpMeYMjLqsfpK0csCmoHzhxxSXO3sCJUkgKyyI5gkURIcGZn XrxGMSmRV3XGxo/oUDsXNTU1GftUw4/2pd52HE+TQJtV1ImDUOvlRsqMmJP/whue+CFW MXqdTV88Qh7RvdTnoO2bT09fYiGSUeX79zZ5MUY6WMqIgZ5L0NsFT795/IkQNQKFTf8j 2E9A2EKB2w8DSxgPCyhaECeqriliQVppucmx11ZN8JrMBrNrL/2SlPn0c2RmyNyY42yp d8YA== X-Gm-Message-State: ANhLgQ2VJ1t6GUtMUXJIxaDzYWrS7cy3JEExgXVVuxBJ3IkbbHSgEgqU oao9HAZf0rgDRggPddzAvlMNrnjE X-Google-Smtp-Source: ADFU+vsX0s58xHBrZiNWhQNZ4+BYI9nXUKflY0WKkor13fnLHK+tPp5d03Uw5SXrCIjLbznhdB/0EA== X-Received: by 2002:a62:880f:: with SMTP id l15mr3796070pfd.218.1583869768082; Tue, 10 Mar 2020 12:49:28 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:27 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Rob Herring Subject: [PATCHv3 1/5] devicetree: bindings: exynos: Add new compatible for Exynos5420 dwc3 clocks support Date: Tue, 10 Mar 2020 19:48:50 +0000 Message-Id: <20200310194854.831-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add the new compatible string for Exynos5422 DWC3 to support enable/disable of core and suspend clk by DWC3 driver. Also updated the clock names for compatible samsung,exynos5420-dwusb3. Acked-by: Rob Herring Signed-off-by: Anand Moon --- Documentation/devicetree/bindings/usb/exynos-usb.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index 6aae1544f240..220f729ac8eb 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -69,7 +69,9 @@ DWC3 Required properties: - compatible: should be one of the following - "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on - Exynos5250/5420. + Exynos5250. + "samsung,exynos5420-dwusb3": for USB 3.0 DWC3 controller on + Exynos5420. "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on Exynos5433. "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. @@ -82,6 +84,7 @@ Required properties: Following clock names shall be provided for different compatibles: - samsung,exynos5250-dwusb3: "usbdrd30", + - samsung,exynos5420-dwusb3: "usbdrd30", "usbdrd30_susp_clk", - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", "phyclk", - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", From patchwork Tue Mar 10 19:48:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 213534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FFC8C10DCE for ; Tue, 10 Mar 2020 19:49:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E3669222D9 for ; Tue, 10 Mar 2020 19:49:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EV6ESjvM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727558AbgCJTtl (ORCPT ); Tue, 10 Mar 2020 15:49:41 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42870 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTtl (ORCPT ); Tue, 10 Mar 2020 15:49:41 -0400 Received: by mail-pg1-f195.google.com with SMTP id h8so6775247pgs.9; Tue, 10 Mar 2020 12:49:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=emQ/yaW/q4/ovb1N6uLBO7edbmwlmGSYTgLz5DT87lA=; b=EV6ESjvMWVAvTDBujuWToM6fGI3hSCL2aCgcuSqMgAc8yycZzHOC7OHaPIsAiB713o O/Y0aZQJKvNIJjiF8siDeNtT636r09VfJU6Yd9CiAe5EJ170hoiWEXi/Z1DxnPZt4MGI L9me3kaVwfNRlFe6A8UuV3qHHJhTgGd3YObjOhAgOOu50a39FWrGcYTIZttalqZq8fmk OwXkGP/mgJVMvjpBc4asDsjBUXVyND9oa+PcwKfJpfYg+477WFUjU2uCAIGagz8wJuna YCy2P6DTgxZT6a6ZJ6/gMl5DTJniwhkupAh/Vu4DcgpjvcickHR23AVoJW9WbVGUWGRj BxYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=emQ/yaW/q4/ovb1N6uLBO7edbmwlmGSYTgLz5DT87lA=; b=HYAwhsUBdDfc3Mid7DuihZYq16FDU7JRQKj/Kce4i8X9xf7dw6R/Yw4thJ3m1KlNHx 1N5qaunKlWL5eHMb6/Ggav7VhYVqTROWPoDkE6lE8TWC87N5gu6O+6xcbn/Nd4lxtWUC l+ntN9josktTRRR4PbBOn/wLa8+MjDRQzn0uD4ZrNiG44SppldtAcQMnk8HKn8C7eqHI 2enSZykPbazimU/JhvmOLMhHT3Hu4bHvRs1VDzawG58oGs7LHW7CxX4AGch1xhc9h7VJ sT7xEQLF5HQj18cgLIS0yN9jb6i3f7vxp4JnWPs3RdmtavRhC0U9U/wZUrJGsyJ5bRN3 vlag== X-Gm-Message-State: ANhLgQ3YESKSlsjOxZ4MUIsaqSHwxeyepQR75gkogotWRsgOhyA4E3KD 2pOzJBcvT7MUT4l0qVpxpRCNuqZI X-Google-Smtp-Source: ADFU+vtDBYANFwpiHqzazrotjATDf0coh4Fl5OzSUKLN06VFFAld3h6QHUGXG0wvNEoqt2bc+hC5wg== X-Received: by 2002:a62:3086:: with SMTP id w128mr2539561pfw.63.1583869778145; Tue, 10 Mar 2020 12:49:38 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:37 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 3/5] ARM: dts: exynos: Add FSYS power domain to Exynos542x USB nodes Date: Tue, 10 Mar 2020 19:48:52 +0000 Message-Id: <20200310194854.831-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add a power domain FSYS for USB 3.0 and USB 2.0 and pdma nodes present on Exynos542x/5800 SoCs. Signed-off-by: Anand Moon --- New patch in this series. --- arch/arm/boot/dts/exynos5420.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index bd505256a223..4046b669b105 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -396,6 +396,13 @@ msc_pd: power-domain@10044120 { label = "MSC"; }; + fsys_pd: power-domain@10044140 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044140 0x20>; + #power-domain-cells = <0>; + label = "FSYS"; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -461,6 +468,7 @@ pdma0: pdma@121a0000 { #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&fsys_pd>; }; pdma1: pdma@121b0000 { @@ -472,6 +480,7 @@ pdma1: pdma@121b0000 { #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&fsys_pd>; }; mdma0: mdma@10800000 { @@ -1374,17 +1383,20 @@ &trng { &usbdrd3_0 { clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&fsys_pd>; }; &usbdrd_phy0 { clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &usbdrd3_1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&fsys_pd>; }; &usbdrd_dwc3_1 { @@ -1395,16 +1407,19 @@ &usbdrd_phy1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &usbhost1 { clocks = <&clock CLK_USBH20>; clock-names = "usbhost"; + power-domains = <&fsys_pd>; }; &usbhost2 { clocks = <&clock CLK_USBH20>; clock-names = "usbhost"; + power-domains = <&fsys_pd>; }; &usb2_phy { @@ -1412,6 +1427,7 @@ &usb2_phy { clock-names = "phy", "ref"; samsung,sysreg-phandle = <&sysreg_system_controller>; samsung,pmureg-phandle = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &watchdog { From patchwork Tue Mar 10 19:48:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 213533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9DF4C1975A for ; Tue, 10 Mar 2020 19:49:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6CC5D21655 for ; Tue, 10 Mar 2020 19:49:51 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 10 Mar 2020 12:49:47 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 5/5] clk: samsung: exynos542x: Move FSYS subsystem clocks to its sub-CMU Date: Tue, 10 Mar 2020 19:48:54 +0000 Message-Id: <20200310194854.831-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes. Signed-off-by: Anand Moon --- New patch in the series --- drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++------- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c9e5a1fb6653..6c4c47dfcdce 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), - /* USB3.0 */ - DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), - DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), - DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), - DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), - /* MMC */ DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { /* FSYS Block */ GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), - GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), - GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), GATE(CLK_SROMC, "sromc", "aclk200_fsys2", GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), - GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), - GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), - GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ }; +/* USB3.0 */ +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = { + DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), + DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), + DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), + DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), +}; + +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = { + GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), + GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), + GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), + GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), + GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = { + { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */ + { SRC_TOP3, 0, BIT(24) }, /* SW_MUX_PCLK_200_FSYS_SEL */ + { SRC_TOP3, 0, BIT(28) }, /* SW_MUX_ACLK_200_FSYS_SEL */ +}; + static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, CLK_SET_RATE_PARENT, 0), @@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { .pd_name = "MAU", }; +static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = { + .div_clks = exynos5x_fsys_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_fsys_div_clks), + .gate_clks = exynos5x_fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_fsys_gate_clks), + .suspend_regs = exynos5x_fsys_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs), + .pd_name = "FSYS", +}; + static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { &exynos5x_disp_subcmu, &exynos5x_gsc_subcmu, &exynos5x_g3d_subcmu, &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, + &exynos5x_fsys_subcmu, }; static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { @@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, &exynos5800_mau_subcmu, + &exynos5x_fsys_subcmu, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {