From patchwork Thu Sep 7 11:41:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111890 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp682263qge; Thu, 7 Sep 2017 04:45:35 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5nW0xngABhla6UWLTN9E3XRXsq4+DKcyYBt/m6RTjYmgHTkvuXB3D5k3JJjce+RZcQIu83 X-Received: by 10.84.129.193 with SMTP id b59mr2804449plb.108.1504784735445; Thu, 07 Sep 2017 04:45:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504784735; cv=none; d=google.com; s=arc-20160816; b=eKAp3Wt2gv3zbfYOu7xzc8rcpxXSJJHVq1ENpbcvrj+EV/BW29PO02dXNNoHJpXGkp aj9G4TH2T7GqUFd8Ws3O7MUMJQhQ8H7GgTvm6NLBJQ+yEAPJfkNvUQGd7z82kmFJE/S6 kLcgxH94dzlflAFQWKbgyxHxARmwBCg8j4rSJYhQ9nm3XrBrre321Hj8uC3kUIxrIWYD gnqUqxJvvJeAEDYhk3HyO8JRy7SCSsHnACEFFZGSE8k1NgXpMVx3UnG5y9hHeQ3U8ykN jc3umI2h6uOSJf9zYQ1PyAJHPRJ9eAafi5umjMdD7nE8tM81BUiPQs5zEBy+mLvStNfn 6pfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=IBfDz1kQGKy4HSf4gyTyv3RWhyF3TqSGq+5ofwdc88c=; b=X/uDm2zHkEk8GB/84JYhqAnJ8bFG4xlyZYau5JI8VSQm9an1rK2lK+PYMzA3nbigvn pa0YH384zz9MTIx40o/GTvGKuiL5IcJhLG1hSjAzrEZcpIOYhMaG0nRDqAD2edVzNXSU E/0B0t5NFvGBt/Lia9pkyfyPnyKeya6OmZ0+E5jMVBdrkw2eXcsomB+FKWxY0E8w6+Kg C0JLtQHw5zg6BKscy3lYruEJOPGPy/ooGJloHglawNglY/GhrxTpYg4NdIL7g/H45nw0 mti+2Z1bvcawC7nekYucwpV0Q8fvEgMHKiH5y7N7WM3ezt5b/l9SHrDRimuB9iP2er5e PTcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=hhdWwkFY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n7si1887336plk.806.2017.09.07.04.45.35; Thu, 07 Sep 2017 04:45:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=hhdWwkFY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755413AbdIGLpc (ORCPT + 26 others); Thu, 7 Sep 2017 07:45:32 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17249 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755222AbdIGLn7 (ORCPT ); Thu, 7 Sep 2017 07:43:59 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v87BgcP0021413; Thu, 7 Sep 2017 20:42:41 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v87BgcP0021413 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1504784562; bh=IBfDz1kQGKy4HSf4gyTyv3RWhyF3TqSGq+5ofwdc88c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hhdWwkFY2VVgmfK0BafD18nwODXyKoX6Unz5z44F79J+KOq4TZpRNYmtsTFhgr9P7 OddeSwrxCFitHaeJCk+MEOT93qOgBR7wif0IoMZ+ZumYdcaUnRSWJDNE5W2PZNv0sN 8uEf2IWrg6yoiZ/mn0/a81/wKvZac5i8XcNqVV3RxZ92kGtkJ2qgGTRvuSjjzNNZdR cdosmVRClAqChK2I/DBiZn842Ni9WM4PDOM9GjXy7h/wyG/+zMhYzEAW569+Ijzjmh 3PjVuPHBGwtilYnT3Bh+iALSdMZx5MqvhFtyCffma+REfxNaCChu8KBcFatdH1dxgl 0b8ybjMPLFDHQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , Thomas Gleixner , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring Cc: Jassi Brar , devicetree@vger.kernel.org, Jason Cooper , Masami Hiramatsu , David Daney , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] irqdomain: clear trigger type in irq_domain_push_irq() Date: Thu, 7 Sep 2017 20:41:58 +0900 Message-Id: <1504784522-26841-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> References: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Prior to the addition of irq_domain_push_irq(), the hierarchy IRQ domain always allocates IRQs from the outer-most domain. Each irqchip usually calls irq_domain_alloc_irqs_parent(), ascending the topology up to the root irqchip. The brand-new function irq_domain_push_irq() allows us to allocate IRQs for parent domain first, then add a child irq_data to the tail of the chain. For the new use-case, if the parent sets a temporary trigger type, it may differ from the type requested to the outer-most irqchip, then irq_create_fwspec_mapping() warns "type mismatch, failed to map..." Clear the trigger type when a new irq_data is connected to the chain. Signed-off-by: Masahiro Yamada --- Changes in v4: - Newly added kernel/irq/irqdomain.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index da3e0b6..18d11b9 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -1532,6 +1532,9 @@ int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg) tail_irq_data->chip = NULL; tail_irq_data->chip_data = NULL; + /* clear the trigger type to avoid "type mismatch" error */ + irqd_set_trigger_type(tail_irq_data, IRQ_TYPE_NONE); + /* May (probably does) set hwirq, chip, etc. */ rv = irq_domain_alloc_irqs_hierarchy(domain, virq, 1, arg); if (rv) { From patchwork Thu Sep 7 11:41:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111887 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp680711qge; Thu, 7 Sep 2017 04:44:04 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6qLYY40ciiuB2s19rnhy8HlM2V08uOChaT0vt5GEvwso7A2a6F3emr/VxWkUaNrpcO6gVP X-Received: by 10.84.210.107 with SMTP id z98mr2662153plh.248.1504784644278; Thu, 07 Sep 2017 04:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504784644; cv=none; d=google.com; s=arc-20160816; b=x88B15/DDOia3bWI0dEypC6+ohTe08bXAP3bWjeQ11Y6mev+KHT5HDb0rEi0+6DZWc xTiymbtY33xrfFnKu9qMWAIwDRUM35a0fUXfj6wRuIsrfFq372vRLGvQr5DKaAzNLm1M 0C4orBA29//LepIHdnKOtGRnIp9zeMasgjLbBLYYnP4l39bb77WuevquXXa6zIrcDlRV L/WhcS9ReloWks3S3zzPkpcxZhRI3EeaZxMawf2QVM05qjfrijHaa1hjACbyfM6F7iik E7ZNTpxQa+vw/hgb3OR1Vvt7+PfvQfZuN09w9JUQfWzufGA3pMjhquLlBEKdonOajMpn Su1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=OU4buTi5rdQ/c0WP7ZgP3dT5In+tuzYJfeV5iVj+UCo=; b=MTc30EK5O92H4qsfPlfRIJn9lNK6WIg/ibO2GlDudkmSbW+NIROuTD2pErbJpe2d3g as1f0DvMXLsUivJNqa2KGKDftBGfQYxG9ZC1StjqUQtIfuhUn14Xkd1somvPVsxx9QfP UPEjyfSW4brwJvLrgxdXL8STnYsr/oljP+gMO6rP6a3lbUR9nNkPSeIZVRHewOxdVaKz DUxSffQ6tcqvesIsLxzO5iENVCsvfnXusakq7GVNW05coABSA3cTx2rbOzwWLSRXNLPJ qkQs2hurYhWX3Cak/UuRsJPXs+ZR2qU8UpK5gGBy4hPb2XLd5qvj2s87j5e/fttVPcd5 yC3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=WhSokaQN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h3si1767510pld.23.2017.09.07.04.44.04; Thu, 07 Sep 2017 04:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=WhSokaQN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755298AbdIGLoB (ORCPT + 26 others); Thu, 7 Sep 2017 07:44:01 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17197 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755169AbdIGLn5 (ORCPT ); Thu, 7 Sep 2017 07:43:57 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v87BgcP1021413; Thu, 7 Sep 2017 20:42:42 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v87BgcP1021413 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1504784563; bh=OU4buTi5rdQ/c0WP7ZgP3dT5In+tuzYJfeV5iVj+UCo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WhSokaQNO3bIHWV1r6Sgh9C5jT3rlmNPtq732gJAI8lqECv3KEA2s+ez5IClPyqxU er1OAGMhr+zDJBSzuc8S6ANcl/IsHk/rzVoD3UiL90lnIZpDo5jVJ5MkJZIHf/1te2 rzAnUU5hrrSShEzCCN2A8/olXGewvxsGh233vWcl7d98uHbKfkyq8KogRGGly7qgeM Ap422685/tkXeYmWoH6sbKabhZfztdzKZicM3T/EdukG8+GWRYZfa1SPPlFAoqP2mt 4a6WHq4TSDjChuyPluaLQJuoerO+Ct5KzKb6ibTQ+pA9er2D+QZULyc38CEX+xhJCp UCzDn6Y7rXg0w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , Thomas Gleixner , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring Cc: Jassi Brar , devicetree@vger.kernel.org, Jason Cooper , Masami Hiramatsu , David Daney , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v4 3/6] irqdomain: move IRQ_DOMAIN_NAME_ALLOCATED define to the original position Date: Thu, 7 Sep 2017 20:41:59 +0900 Message-Id: <1504784522-26841-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> References: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 6a6544e520ab ("genirq/irqdomain: Remove auto-recursive hierarchy support") not only deleted IRQ_DOMAIN_FLAG_AUTO_RECURSIVE, but also moved IRQ_DOMAIN_NAME_ALLOCATED up. Get it back to the original position to sort the enum by the bit shift. Signed-off-by: Masahiro Yamada --- Changes in v4: - Newly added include/linux/irqdomain.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 81e4889..31be32d 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -180,9 +180,6 @@ enum { /* Irq domain is hierarchical */ IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0), - /* Irq domain name was allocated in __irq_domain_add() */ - IRQ_DOMAIN_NAME_ALLOCATED = (1 << 6), - /* Irq domain is an IPI domain with virq per cpu */ IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2), @@ -195,6 +192,9 @@ enum { /* Irq domain implements MSI remapping */ IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5), + /* Irq domain name was allocated in __irq_domain_add() */ + IRQ_DOMAIN_NAME_ALLOCATED = (1 << 6), + /* * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved * for implementation specific purposes and ignored by the From patchwork Thu Sep 7 11:42:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111891 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp682453qge; Thu, 7 Sep 2017 04:45:47 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4YePE04SfVkeL0T+o20rSlx80iJ8XQW3aQK1txVS03LSQCP/zi1HkJ0kHeFsp83fFG5XwF X-Received: by 10.98.144.210 with SMTP id q79mr2351452pfk.331.1504784747551; Thu, 07 Sep 2017 04:45:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504784747; cv=none; d=google.com; s=arc-20160816; b=yCXfxqh5Eun0KhWePWrfXBVUaoTj7DhC5WXWHNVhGD/k1TxFcjj2ZPnl+MVHdrRQCK tg8MRPlXehz2WvrhkapY/oxqrlSezm0rmzqrhB7TXZkrdEqGLjRX6qP7q3KHB7DP0ktD ImGwgzl6MTs/jtSg5WDpyRvTz3qliTU2CljVoew2puguZWNIaAiHsHgWt2NbtaUEL/b9 WMSLyWGqRykAe5MxnAc5JNRBcNdYbwfUa4KH00WpNWByeADnhKNRPU7/j2rx1JMYZrxc K3If81LXUNhw832nZGTf1+yNlWZ8OEN9844UdFQrh4Hva+myuiBmBYW6TyzTitt+OcQc AlLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=X/I1RnU3Gpzzhqg3pT6YB/0pqxY8xpqZMXsz/E2FYa4=; b=GUL4ng/2s+yNK2Xf0W8n1ocrxU9bgRdXcgk66sOUZiBgxrElhbk8EQxgOjIdFYS+mb dX5USnqCPTh2yOeqOfYL81OdRYe4+yHwRauovZW9n7+IT83zRXjg2fkNIl/usgj+7mZX uFmR3FJStULGPXCTiicv6x2hQ3sD4e5WtCQDcuxzLTOnzCoC6ixgdZ2MTnNMvDnXIvQI hpfakawDEC261vdblYUpQdcmV1LUeeH2Q5vBX7TRdyMCXT3o4IvX4hqeNntQ3/2HAgAV og8+lcjv2TDb06RcAno9B4hku4H3MbqfNSYBWOL4BE+Fkc8E1iTl5ybGOvk9MFpqtJ0V wIsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=v+mfaEEj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v26si1746596pgc.383.2017.09.07.04.45.47; Thu, 07 Sep 2017 04:45:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=v+mfaEEj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755394AbdIGLpa (ORCPT + 26 others); Thu, 7 Sep 2017 07:45:30 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:17251 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755223AbdIGLn7 (ORCPT ); Thu, 7 Sep 2017 07:43:59 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v87BgcP3021413; Thu, 7 Sep 2017 20:42:45 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v87BgcP3021413 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1504784566; bh=X/I1RnU3Gpzzhqg3pT6YB/0pqxY8xpqZMXsz/E2FYa4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=v+mfaEEjEDASsoAlytN+uZbu7QfE3gxL7g6ZMN8YCQN5qbiQ/l9HTLL51oQAdXLMT b/aPPOxpSFMGrFUAXVc4I6lLT+sKvrzLrtKDVoe2qZ6B4QBa9Y/xodLq7yQ1CWgW9v HuQciynbixVNGknv8KEKl4IWEFYX6LbzffiZNco/GZqurQBjk/CD7H6/ft/YoH8Oy8 Ndg9RLjzPXmjNAUb8yOX/8QQnrxiGY5hX5mtey3vFQfR8y7Qmkm5AaslQZ+TU1tjCW /dOJVS0TjS3Z84hJIwu327cqF2vNHZhVP3GSoCaQNBpSL+aCM+jpuO3KOCTa9TLZZi R8pM5/2iTLWDQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , Thomas Gleixner , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring Cc: Jassi Brar , devicetree@vger.kernel.org, Jason Cooper , Masami Hiramatsu , David Daney , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v4 5/6] irqdomain: add IRQ_DOMAIN_FLAG_NO_CREATE flag Date: Thu, 7 Sep 2017 20:42:01 +0900 Message-Id: <1504784522-26841-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> References: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When an irqchip driver uses irq_domain_push_irq(), all irqs should be statically created by the irqchip. If a device tries to allocate an irq on-the-fly, irq_domain_alloc_irqs() is called. It allocates struct irq_data and invokes .alloc() hook passing fwspec as its argument. This is probably not what the irqchip expects (unless .alloc can call it recursively). This issue could happen when a device tries to get irq after irq_domain_create_hierarchy(), but before irq_domain_push_irq(). To avoid the race, add IRQ_DOMAIN_FLAG_NO_CREATE flag. This flag prevents devices from creating irqs. Devices are only allowed to get already existing irqs. Signed-off-by: Masahiro Yamada --- Changes in v4: - Newly added include/linux/irqdomain.h | 3 +++ kernel/irq/irqdomain.c | 3 +++ 2 files changed, 6 insertions(+) -- 2.7.4 diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 7609807..525de32 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -195,6 +195,9 @@ enum { /* Irq domain name was allocated in __irq_domain_add() */ IRQ_DOMAIN_NAME_ALLOCATED = (1 << 6), + /* Do not allow irq consumers to create irq */ + IRQ_DOMAIN_FLAG_NO_CREATE = (1 << 7), + /* * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved * for implementation specific purposes and ignored by the diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index b317a64..ecf107ab 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -806,6 +806,9 @@ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) return 0; } + if (domain->flags & IRQ_DOMAIN_FLAG_NO_CREATE) + return -EPROBE_DEFER; + if (irq_domain_is_hierarchy(domain)) { virq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, fwspec); if (virq <= 0) From patchwork Thu Sep 7 11:42:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111889 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp681331qge; Thu, 7 Sep 2017 04:44:45 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5IfnLcVzZUTypT17RBuaTXjUUJbMm9q+lRYw1nKfsgXpV8/EJ9eIEzbn2BGUCjWGpPmo4p X-Received: by 10.99.95.204 with SMTP id t195mr2433922pgb.135.1504784685250; Thu, 07 Sep 2017 04:44:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504784685; cv=none; d=google.com; s=arc-20160816; b=k2VhWTKMWzQhuwKhau41bl0efmXeoVDOBdXmQHOALsB/ScuWTnmX1wkeal5krw5B93 99wqDx9AmxkBd95WsIBz2kBvPDet4TmuPDoGLS19iPgt/F2VHLEKkfUUc69r6j67/9fx uEc+r32FlzyOl0Mz7mclpafuMYOg4RRBanZCygl/vAvOf7VtA3LognoOVq7A1CTTaQAS 4sgl7BD36F+qZFrcGK5vcLsrp10ezPXWYLCJbDamudKEaHRpB3UH4Fe/H1U2/+NVOXU6 kNhIskaBHJis9tB6PtwminSjeaF4kbiziZKb164IxkMfHc6Ylyq/mHJvj1q38WuComNv qqcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=JsizReNWUbVQY7uPf6y0+xQvQIqKzrnRersMQEfLmxs=; b=yd2B8lQlGr39Aq8gJYQPTfymCgFRyUabDRrl+a/B4nK4V3MN4cOeXxucfAS/F5SYdz 5UivqBQp38kLNNxo7Zoa5V1lirNkbrsLpfrKrO8QgGw7XRq1V+pa6iJbsThTyrMcucpV ZMmk1SUdbNtpWHKpVvMHdZSPh8QTwcvTECmcu8kijnAzvU0M2QYpeaW3jAoLkcKeTwqB BsdH7UEbDmrPYs8cE8G1TS/7wY7wy7ZCaG1oRYcZu8gCDS7lAw4l1SDAO2kv2669c7qF grUFX+1Xhvizp0gLmo9EU295tbvFeowKn6X5toGJAVYL5oAvoselKjoMwebzyPQgXts4 tPHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=MGH4g3BA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p61si1798073plb.287.2017.09.07.04.44.39; Thu, 07 Sep 2017 04:44:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=MGH4g3BA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755369AbdIGLoi (ORCPT + 26 others); Thu, 7 Sep 2017 07:44:38 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:18230 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755352AbdIGLof (ORCPT ); Thu, 7 Sep 2017 07:44:35 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v87BgcP4021413; Thu, 7 Sep 2017 20:42:46 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v87BgcP4021413 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1504784567; bh=JsizReNWUbVQY7uPf6y0+xQvQIqKzrnRersMQEfLmxs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MGH4g3BAbL3hHYNp7lAoMGKqHVmJqKq/I3VB/UPpuFnqw4QeRyqOTV/IM0VLsJZMJ S0EYyi8u9a8A+syaPb7yWCxr60UPag1EOSh9NXHh0SMLSTqr/SSMdri+u3kyO0X42v 9QDL3Qx4jjZ5hbSOFY2c7nJRhtfFAVDmhfz3qLNmq2V0U4OcgYRuwDjvXIp8gUMxts M0aC1abu+hPkuwHLP6Ufkwp92A/0TQ66ev5bxcKaveuCfpggRqWPmf9tMJs0ZDEL54 NKMtQB8rutBc5X4uB2GQz2MBHU7KNFAhrx8RezTJjcqHs2nLveBvXzsX5zh0O3SVJb Iuz8pJvP0LRtw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , Thomas Gleixner , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring Cc: Jassi Brar , devicetree@vger.kernel.org, Jason Cooper , Masami Hiramatsu , David Daney , Masahiro Yamada , linux-kernel@vger.kernel.org, Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 6/6] gpio: uniphier: add UniPhier GPIO controller driver Date: Thu, 7 Sep 2017 20:42:02 +0900 Message-Id: <1504784522-26841-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> References: <1504784522-26841-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This GPIO controller device is used on UniPhier SoCs. It also serves as an interrupt controller, but interrupt signals are just delivered to the parent irqchip without any latching or OR'ing. This is implemented by using hierarchy IRQ domain. Implementation note: Unfortunately, the IRQ mapping from this controller to the parent is random. (48, 49, ..., 63, 154, 155, ...) If "interrupts" property is used, IRQ resources may be statically allocated when platform devices are populated from DT. This can be a problem for the hierarchy IRQ domain because IRQ allocation must happen from the outer-most domain up to the root domain in order to build up the stacked IRQ. (https://lkml.org/lkml/2017/7/6/758) Solutions to work around it could be to hard-code parent hwirqs or to invent a driver-specific DT property. Here, the new API irq_domain_push_irq() was merged by v4.14-rc1. It allows to add irq_data to the existing hierarchy. It will help to make this driver work whether the parent has already initialized the hierarchy or not. Signed-off-by: Masahiro Yamada --- Changes in v4: - Add COMPILE_TEST and select IRQ_DOMAIN_HIERARCHY - Reimplement irqchip part by using irq_domain_push_irq() Changes in v3: - Add .irq_set_affinity() hook - Use irq_domain_create_hierarchy() instead of legacy irq_domain_add_hierarchy() Changes in v2: - Remove +32 offset for parent interrupts to follow the GIC binding convention - Let uniphier_gpio_irq_alloc() fail if nr_irqs != 1 - Allocate gpio_chip statically because just one instance is supported - Fix suspend and resume hooks .../devicetree/bindings/gpio/gpio-uniphier.txt | 43 ++ MAINTAINERS | 1 + drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uniphier.c | 486 +++++++++++++++++++++ include/dt-bindings/gpio/uniphier-gpio.h | 18 + 6 files changed, 557 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-uniphier.txt create mode 100644 drivers/gpio/gpio-uniphier.c create mode 100644 include/dt-bindings/gpio/uniphier-gpio.h -- 2.7.4 diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt new file mode 100644 index 0000000..10326df --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt @@ -0,0 +1,43 @@ +UniPhier GPIO controller + +Required properties: +- compatible: Should be "socionext,uniphier-gpio". +- reg: Specifies offset and length of the register set for the device. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be 2. The first cell is the pin number and the second + cell is used to specify optional parameters. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies interrupts connected to the parent interrupt controller. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be 2. The first cell defines the interrupt number. + The second cell bits[3:0] is used to specify trigger type as follows: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. +- ngpios: Specifies the number of GPIO lines. +- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt) + +Optional properties: +- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt) + +Example: + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupts = <48 4>, <49 4>, <50 4>, <51 4>, + <52 4>, <53 4>, <54 4>, <55 4>, + <56 4>, <57 4>, <58 4>, <59 4>, + <60 4>, <61 4>, <62 4>, <63 4>, + <154 4>, <155 4>, <156 4>, <157 4>, + <158 4>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 11dde28..df67191 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2007,6 +2007,7 @@ F: arch/arm/mm/cache-uniphier.c F: arch/arm64/boot/dts/socionext/ F: drivers/bus/uniphier-system-bus.c F: drivers/clk/uniphier/ +F: drivers/gpio/gpio-uniphier.c F: drivers/i2c/busses/i2c-uniphier* F: drivers/irqchip/irq-uniphier-aidet.c F: drivers/pinctrl/uniphier/ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3f80f16..25c0f308 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -475,6 +475,14 @@ config GPIO_TZ1090_PDC help Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs. +config GPIO_UNIPHIER + tristate "UniPhier GPIO support" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on OF_GPIO + select IRQ_DOMAIN_HIERARCHY + help + Say yes here to support UniPhier GPIOs. + config GPIO_VF610 def_bool y depends on ARCH_MXC && SOC_VF610 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aeb70e9d..472f675 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o +obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c new file mode 100644 index 0000000..135c91a --- /dev/null +++ b/drivers/gpio/gpio-uniphier.c @@ -0,0 +1,486 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UNIPHIER_GPIO_BANK_MASK \ + GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) + +#define UNIPHIER_GPIO_IRQ_MAX_NUM 32 + +#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ +#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */ +#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */ +#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */ +#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */ +#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */ + +struct uniphier_gpio_priv { + struct gpio_chip chip; + struct irq_chip irq_chip; + struct irq_domain *domain; + void __iomem *regs; + spinlock_t lock; + unsigned int nirqs; + u32 saved_vals[0]; +}; + +static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) +{ + unsigned int reg; + + reg = (bank + 1) * 8; + + /* + * Unfortunately, the GPIO port registers are not contiguous because + * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. + */ + if (reg >= UNIPHIER_GPIO_IRQ_EN) + reg += 0x10; + + return reg; +} + +static void uniphier_gpio_get_bank_and_mask(unsigned int offset, + unsigned int *bank, u32 *mask) +{ + *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; + *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); +} + +static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv, + unsigned int reg, u32 mask, u32 val) +{ + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&priv->lock, flags); + tmp = readl(priv->regs + reg); + tmp &= ~mask; + tmp |= mask & val; + writel(tmp, priv->regs + reg); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, + unsigned int reg, u32 mask, u32 val) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); + + if (!mask) + return; + + uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, + mask, val); +} + +static void uniphier_gpio_offset_write(struct gpio_chip *chip, + unsigned int offset, unsigned int reg, + int val) +{ + unsigned int bank; + u32 mask; + + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + + uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); +} + +static int uniphier_gpio_offset_read(struct gpio_chip *chip, + unsigned int offset, unsigned int reg) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); + unsigned int bank, reg_offset; + u32 mask; + + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; + + return !!(readl(priv->regs + reg_offset) & mask); +} + +static int uniphier_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR); +} + +static int uniphier_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1); + + return 0; +} + +static int uniphier_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0); + + return 0; +} + +static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA); +} + +static void uniphier_gpio_set(struct gpio_chip *chip, + unsigned int offset, int val) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); +} + +static void uniphier_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + unsigned int bank, shift, bank_mask, bank_bits; + int i; + + for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { + bank = i / UNIPHIER_GPIO_LINES_PER_BANK; + shift = i % BITS_PER_LONG; + bank_mask = (mask[BIT_WORD(i)] >> shift) & + UNIPHIER_GPIO_BANK_MASK; + bank_bits = bits[BIT_WORD(i)] >> shift; + + uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, + bank_mask, bank_bits); + } +} + +static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); + + if (offset < UNIPHIER_GPIO_IRQ_OFFSET) + return -ENXIO; + + return irq_find_mapping(priv->domain, + offset - UNIPHIER_GPIO_IRQ_OFFSET); +} + +static void uniphier_gpio_irq_mask(struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); + + return irq_chip_mask_parent(data); +} + +static void uniphier_gpio_irq_unmask(struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); + + return irq_chip_unmask_parent(data); +} + +static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + u32 val = 0; + + if (type == IRQ_TYPE_EDGE_BOTH) { + val = mask; + type = IRQ_TYPE_EDGE_FALLING; + } + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); + /* To enable both edge detection, the noise filter must be enabled. */ + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); + + return irq_chip_set_type_parent(data, type); +} + +static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + irq_hw_number_t hwirq = (long)arg; + + if (WARN_ON(nr_irqs != 1)) + return -EINVAL; + + if (WARN_ON(hwirq >= priv->nirqs)) + return -EINVAL; + + return irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &priv->irq_chip, priv); +} + +static void uniphier_gpio_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + struct gpio_chip *chip = &priv->chip; + + gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); +} + +static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain, + struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + struct gpio_chip *chip = &priv->chip; + + gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); +} + +static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + + *out_hwirq = fwspec->param[0]; + *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = { + .alloc = uniphier_gpio_irq_domain_alloc, + .free = irq_domain_free_irqs_common, + .activate = uniphier_gpio_irq_domain_activate, + .deactivate = uniphier_gpio_irq_domain_deactivate, + .translate = uniphier_gpio_irq_domain_translate, +}; + +static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv) +{ + /* + * Due to the hardware design, the noise filter must be enabled to + * detect both edge interrupts. This filter is intended to remove the + * noise from the irq lines. It does not work for GPIO input, so GPIO + * debounce is not supported. Unfortunately, the filter period is + * shared among all irq lines. Just choose a sensible period here. + */ + writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC); +} + +static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio) +{ + return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK); +} + +static int uniphier_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *parent_np; + struct irq_domain *parent_domain; + struct uniphier_gpio_priv *priv; + struct gpio_chip *chip; + struct irq_chip *irq_chip; + struct resource *regs; + unsigned int nregs; + u32 ngpios; + int virq, ret, i; + + parent_np = of_irq_find_parent(dev->of_node); + if (!parent_np) + return -ENXIO; + + parent_domain = irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) + return -EPROBE_DEFER; + + ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios); + if (ret) + return ret; + + nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3; + priv = devm_kzalloc(dev, + sizeof(*priv) + sizeof(priv->saved_vals[0]) * nregs, + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->nirqs = of_irq_count(dev->of_node); + if (priv->nirqs > UNIPHIER_GPIO_IRQ_MAX_NUM) + return -EINVAL; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + spin_lock_init(&priv->lock); + + chip = &priv->chip; + chip->label = dev_name(dev); + chip->parent = dev; + chip->request = gpiochip_generic_request; + chip->free = gpiochip_generic_free; + chip->get_direction = uniphier_gpio_get_direction; + chip->direction_input = uniphier_gpio_direction_input; + chip->direction_output = uniphier_gpio_direction_output; + chip->get = uniphier_gpio_get; + chip->set = uniphier_gpio_set; + chip->set_multiple = uniphier_gpio_set_multiple; + chip->to_irq = uniphier_gpio_to_irq; + chip->base = -1; + chip->ngpio = ngpios; + + irq_chip = &priv->irq_chip; + irq_chip->name = dev_name(dev); + irq_chip->irq_mask = uniphier_gpio_irq_mask; + irq_chip->irq_unmask = uniphier_gpio_irq_unmask; + irq_chip->irq_eoi = irq_chip_eoi_parent; + irq_chip->irq_set_affinity = irq_chip_set_affinity_parent; + irq_chip->irq_set_type = uniphier_gpio_irq_set_type; + + uniphier_gpio_hw_init(priv); + + ret = devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + priv->domain = irq_domain_create_hierarchy( + parent_domain, + IRQ_DOMAIN_FLAG_NO_CREATE, priv->nirqs, + of_node_to_fwnode(dev->of_node), + &uniphier_gpio_irq_domain_ops, priv); + if (!priv->domain) + return -ENOMEM; + + for (i = 0; i < priv->nirqs; i++) { + virq = platform_get_irq(pdev, i); + if (virq < 0) + continue; + + ret = irq_domain_push_irq(priv->domain, virq, (void *)(long)i); + if (ret) + dev_warn(dev, + "failed to push to irq hierarchy. IRQ%d is not usable.", + i); + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int uniphier_gpio_remove(struct platform_device *pdev) +{ + struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); + unsigned int virq; + int ret, i; + + for (i = 0; i < priv->nirqs; i++) { + virq = irq_find_mapping(priv->domain, i); + if (!virq) + continue; + ret = irq_domain_pop_irq(priv->domain, virq); + if (ret) + return ret; + } + + irq_domain_remove(priv->domain); + + return 0; +} + +static int __maybe_unused uniphier_gpio_suspend(struct device *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); + unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); + u32 *val = priv->saved_vals; + unsigned int reg; + int i; + + for (i = 0; i < nbanks; i++) { + reg = uniphier_gpio_bank_to_reg(i); + + *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); + *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); + } + + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN); + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE); + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); + + return 0; +} + +static int __maybe_unused uniphier_gpio_resume(struct device *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); + unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); + const u32 *val = priv->saved_vals; + unsigned int reg; + int i; + + for (i = 0; i < nbanks; i++) { + reg = uniphier_gpio_bank_to_reg(i); + + writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); + writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); + } + + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN); + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE); + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); + + uniphier_gpio_hw_init(priv); + + return 0; +} + +static const struct dev_pm_ops uniphier_gpio_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend, + uniphier_gpio_resume) +}; + +static const struct of_device_id uniphier_gpio_match[] = { + { .compatible = "socionext,uniphier-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_gpio_match); + +static struct platform_driver uniphier_gpio_driver = { + .probe = uniphier_gpio_probe, + .remove = uniphier_gpio_remove, + .driver = { + .name = "uniphier-gpio", + .of_match_table = uniphier_gpio_match, + .pm = &uniphier_gpio_pm_ops, + }, +}; +module_platform_driver(uniphier_gpio_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h new file mode 100644 index 0000000..9f0ad17 --- /dev/null +++ b/include/dt-bindings/gpio/uniphier-gpio.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + */ + +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +#define _DT_BINDINGS_GPIO_UNIPHIER_H + +#define UNIPHIER_GPIO_LINES_PER_BANK 8 + +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) + +#define UNIPHIER_GPIO_PORT(bank, line) \ + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) + +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) + +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */