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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:11 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 03/17] ARM: tegra: Remove pen-locking from cpuidle-tegra20 Date: Thu, 13 Feb 2020 02:51:20 +0300 Message-Id: <20200212235134.12638-4-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Pen-locking is meant to block CPU0 if CPU1 wakes up during of entering into LP2 because of some interrupt firing up, preventing unnecessary LP2 enter that will be resumed immediately. Apparently this case doesn't happen often in practice, I checked how often it takes place and found that after ~20 hours of browsing web, managing email, watching videos and idling (15+ hours) there is only a dozen of early LP2 entering abortions and they all happened while device was idling. Thus let's remove the pen-locking and make LP2 entering uninterruptible, simplifying code quite a lot. This will also become very handy for the upcoming unified cpuidle driver, allowing to have a common LP2 code-path across of different hardware generations. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 46 +------ arch/arm/mach-tegra/pm.c | 7 -- arch/arm/mach-tegra/pm.h | 1 - arch/arm/mach-tegra/reset-handler.S | 11 -- arch/arm/mach-tegra/reset.h | 9 +- arch/arm/mach-tegra/sleep-tegra20.S | 170 -------------------------- arch/arm/mach-tegra/sleep.h | 12 -- 7 files changed, 5 insertions(+), 251 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 69f3fa270fbe..f7d5041e73cc 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -65,28 +66,8 @@ static struct cpuidle_driver tegra_idle_driver = { #ifdef CONFIG_PM_SLEEP #ifdef CONFIG_SMP -static int tegra20_reset_sleeping_cpu_1(void) -{ - int ret = 0; - - tegra_pen_lock(); - - if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE) - tegra20_cpu_shutdown(1); - else - ret = -EINVAL; - - tegra_pen_unlock(); - - return ret; -} - static void tegra20_wake_cpu1_from_reset(void) { - tegra_pen_lock(); - - tegra20_cpu_clear_resettable(); - /* enable cpu clock on cpu */ tegra_enable_cpu_clock(1); @@ -95,39 +76,20 @@ static void tegra20_wake_cpu1_from_reset(void) /* unhalt the cpu */ flowctrl_write_cpu_halt(1, 0); - - tegra_pen_unlock(); -} - -static int tegra20_reset_cpu_1(void) -{ - if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) - return 0; - - tegra20_wake_cpu1_from_reset(); - return -EBUSY; } #else static inline void tegra20_wake_cpu1_from_reset(void) { } - -static inline int tegra20_reset_cpu_1(void) -{ - return 0; -} #endif static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - while (tegra20_cpu_is_resettable_soon()) + while (!tegra_cpu_rail_off_ready()) cpu_relax(); - if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) - return false; - tegra_idle_lp2_last(); if (cpu_online(1)) @@ -141,9 +103,7 @@ static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); - - tegra20_cpu_clear_resettable(); + cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu); return true; } diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f5ff3dd1dd81..1ff499068bb1 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -137,18 +137,11 @@ bool tegra_set_cpu_in_lp2(void) if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) last_cpu = true; - else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1) - tegra20_cpu_set_resettable_soon(); spin_unlock(&tegra_lp2_lock); return last_cpu; } -int tegra_cpu_do_idle(void) -{ - return cpu_do_idle(); -} - static int tegra_sleep_cpu(unsigned long v2p) { /* diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 9a790f00237f..b9cc12222bb1 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,6 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); -int tegra_cpu_do_idle(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e3f34815c9da..53123ae4ac3b 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -183,17 +183,6 @@ after_errata: bleq __die @ CPU not present (to OS) #endif -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - cmp r6, #TEGRA20 - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov r0, #CPU_NOT_RESETTABLE - cmp r10, #0 - strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] -1: -#endif - /* Waking up from LP1? */ ldr r8, [r12, #RESET_DATA(MASK_LP1)] tst r8, r11 @ if in_lp1 diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index a4cfc08159f6..51265592cb1a 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -16,9 +16,8 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_RESETTABLE_STATUS 6 -#define TEGRA_RESET_TF_PRESENT 7 -#define TEGRA_RESET_DATA_SIZE 8 +#define TEGRA_RESET_TF_PRESENT 6 +#define TEGRA_RESET_DATA_SIZE 7 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -42,10 +41,6 @@ void __tegra_cpu_reset_handler_end(void); (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ (u32)__tegra_cpu_reset_handler_start))) -#define tegra20_cpu1_resettable_status \ - (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ - (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9a89f30d53ca..0e00ba8cf646 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,9 +43,6 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -#define __tegra20_cpu1_resettable_status_offset \ - (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) - .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) @@ -90,10 +87,6 @@ ENDPROC(tegra20_hotplug_shutdown) ENTRY(tegra20_cpu_shutdown) cmp r0, #0 reteq lr @ must not be called for CPU 0 - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE - strb r12, [r1, r2] cpu_to_halt_reg r1, r0 ldr r3, =TEGRA_FLOW_CTRL_VIRT @@ -116,107 +109,6 @@ ENDPROC(tegra20_cpu_shutdown) #endif #ifdef CONFIG_PM_SLEEP -/* - * tegra_pen_lock - * - * spinlock implementation with no atomic test-and-set and no coherence - * using Peterson's algorithm on strongly-ordered registers - * used to synchronize a cpu waking up from wfi with entering lp2 on idle - * - * The reference link of Peterson's algorithm: - * http://en.wikipedia.org/wiki/Peterson's_algorithm - * - * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) - * on cpu 0: - * r2 = flag[0] (in SCRATCH38) - * r3 = flag[1] (in SCRATCH39) - * on cpu1: - * r2 = flag[1] (in SCRATCH39) - * r3 = flag[0] (in SCRATCH38) - * - * must be called with MMU on - * corrupts r0-r3, r12 - */ -ENTRY(tegra_pen_lock) - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - add r1, r3, #PMC_SCRATCH37 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addeq r3, r3, #PMC_SCRATCH39 - addne r2, r3, #PMC_SCRATCH39 - addne r3, r3, #PMC_SCRATCH38 - - mov r12, #1 - str r12, [r2] @ flag[cpu] = 1 - dsb - str r12, [r1] @ !turn = cpu -1: dsb - ldr r12, [r3] - cmp r12, #1 @ flag[!cpu] == 1? - ldreq r12, [r1] - cmpeq r12, r0 @ !turn == cpu? - beq 1b @ while !turn == cpu && flag[!cpu] == 1 - - ret lr @ locked -ENDPROC(tegra_pen_lock) - -ENTRY(tegra_pen_unlock) - dsb - mov32 r3, TEGRA_PMC_VIRT - cpu_id r0 - cmp r0, #0 - addeq r2, r3, #PMC_SCRATCH38 - addne r2, r3, #PMC_SCRATCH39 - mov r12, #0 - str r12, [r2] - ret lr -ENDPROC(tegra_pen_unlock) - -/* - * tegra20_cpu_clear_resettable(void) - * - * Called to clear the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_clear_resettable) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_NOT_RESETTABLE - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_clear_resettable) - -/* - * tegra20_cpu_set_resettable_soon(void) - * - * Called to set the "resettable soon" flag in IRAM variable when - * it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_set_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - mov r12, #CPU_RESETTABLE_SOON - strb r12, [r1, r2] - ret lr -ENDPROC(tegra20_cpu_set_resettable_soon) - -/* - * tegra20_cpu_is_resettable_soon(void) - * - * Returns true if the "resettable soon" flag in IRAM variable has been - * set because it is expected that the secondary CPU will be idle soon. - */ -ENTRY(tegra20_cpu_is_resettable_soon) - mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT - ldr r2, =__tegra20_cpu1_resettable_status_offset - ldrb r12, [r1, r2] - cmp r12, #CPU_RESETTABLE_SOON - moveq r0, #1 - movne r0, #0 - ret lr -ENDPROC(tegra20_cpu_is_resettable_soon) - /* * tegra20_sleep_core_finish(unsigned long v2p) * @@ -242,68 +134,6 @@ ENTRY(tegra20_sleep_core_finish) ret r3 ENDPROC(tegra20_sleep_core_finish) -/* - * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) - * - * Enters WFI on secondary CPU by exiting coherency. - */ -ENTRY(tegra20_sleep_cpu_secondary_finish) - stmfd sp!, {r4-r11, lr} - - mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency - - /* Flush and disable the L1 data cache */ - mov r0, #TEGRA_FLUSH_CACHE_LOUIS - bl tegra_disable_clean_inv_dcache - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_RESETTABLE - strb r3, [r0, r4] - - bl tegra_cpu_do_idle - - /* - * cpu may be reset while in wfi, which will return through - * tegra_resume to cpu_resume - * or interrupt may wake wfi, which will return here - * cpu state is unchanged - MMU is on, cache is on, coherency - * is off, and the data cache is off - * - * r11 contains the original actlr - */ - - bl tegra_pen_lock - - mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT - ldr r4, =__tegra20_cpu1_resettable_status_offset - mov r3, #CPU_NOT_RESETTABLE - strb r3, [r0, r4] - - bl tegra_pen_unlock - - /* Re-enable the data cache */ - mrc p15, 0, r10, c1, c0, 0 - orr r10, r10, #CR_C - mcr p15, 0, r10, c1, c0, 0 - isb - - mcr p15, 0, r11, c1, c0, 1 @ reenable coherency - - /* Invalidate the TLBs & BTAC */ - mov r1, #0 - mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs - mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC - dsb - isb - - /* the cpu was running with coherency disabled, - * caches may be out of date */ - bl v7_flush_kern_cache_louis - - ldmfd sp!, {r4 - r11, pc} -ENDPROC(tegra20_sleep_cpu_secondary_finish) - /* * tegra20_tear_down_cpu * diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 63e2205cbc82..4978def9db46 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -114,8 +114,6 @@ .endm #else -void tegra_pen_lock(void); -void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); void tegra_disable_clean_inv_dcache(u32 flag); @@ -123,16 +121,6 @@ void tegra_disable_clean_inv_dcache(u32 flag); void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); -void tegra20_cpu_shutdown(int cpu); -int tegra20_cpu_is_resettable_soon(void); -void tegra20_cpu_clear_resettable(void); -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void tegra20_cpu_set_resettable_soon(void); -#else -static inline void tegra20_cpu_set_resettable_soon(void) {} -#endif - -int tegra20_sleep_cpu_secondary_finish(unsigned long); void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); From patchwork Wed Feb 12 23:51:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A94C352A4 for ; Wed, 12 Feb 2020 23:53:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 745DF2173E for ; Wed, 12 Feb 2020 23:53:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fsl+VrDn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729564AbgBLXxI (ORCPT ); Wed, 12 Feb 2020 18:53:08 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:45669 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729347AbgBLXwS (ORCPT ); Wed, 12 Feb 2020 18:52:18 -0500 Received: by mail-lj1-f194.google.com with SMTP id e18so4398186ljn.12; Wed, 12 Feb 2020 15:52:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KHrYqBDKYlz+lEpjkINyfV+xDsRET+kxSXkiOpMcGaI=; b=fsl+VrDnL7WiHbTcAd9P0ifXg0qE0zRu5C3CLwQ9sCU8JIgZi6xwcdiSN9rTEWzwb/ mh/RI764BLtOtQDE5a0JBW4DAodouHEC8ndP/tIvmcvKqnyRr+8lN8ANBDUvh7RPldik BBzkK0jj1wgH6FrG0hElA8XSYXplfse5gLpQ0FIcwR2HMc9HWIss6rlj+XzTfdMQhSXp FHFbI5L/OGP3pKt7YVskUtapD0GjxmNTfh2D5SQrB2zqSLfv0onbKLwxw0y4DVtELsE1 e6gD2LCoaTKN4G34YoyAQ9vlKTIRqqlM2yOYRI746SjF4qPTEwGH/HLjgBE/3t4Vu/4B xqrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KHrYqBDKYlz+lEpjkINyfV+xDsRET+kxSXkiOpMcGaI=; b=N+IewRma3E2U7H3zGq86Kd/MuPnsKIDupyU4WqIaQIbXj96Z2BZSdSgV2DjeRxceZq ZHmQMlw4Orz0jFRzZpDYx0x5H9A1RmSXTzoy/td5K50MCq9FW17ANLMtFnAJ+fAWKrFH /+fX2k7UTJGWCu3Mtbv9io+/JDbiCe0J8po4o7ZOWL+Xj564Ivzv0ccKh8l0jn4ZhvvX ZPzhetABFUMTzEHcUEUXTBK9hUO/K6eTdk7h1Ly7cFYmBgLCuc/BgG3hNZ4niOpzWxRZ KypQovstPLU2s2Qt8tIdZP+B+JBnieSRqSH2nck68lTZtafYRp6AuuY6sPoDSc0pte6a 2qdQ== X-Gm-Message-State: APjAAAUQ+AfvYO8Jlrz8JlA8IRNiyD2jf7sdtU2ZD1lRkubNSdFCdrg+ ueOMM3ND6vZ9Nwsq7Sl0BB8= X-Google-Smtp-Source: APXvYqzVk+PeVXZr6ke6FXgvT6ZBYF4v/LvqXXjYgZPEGiXy4XOapVBPuLj3DejgyYu3OqG74TjMzQ== X-Received: by 2002:a2e:a36a:: with SMTP id i10mr8988621ljn.107.1581551534332; Wed, 12 Feb 2020 15:52:14 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:13 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 05/17] ARM: tegra: Propagate error from tegra_idle_lp2_last() Date: Thu, 13 Feb 2020 02:51:22 +0300 Message-Id: <20200212235134.12638-6-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Technically cpu_suspend() may fail and it's never good to lose information about failure. For example things like cpuidle core could correctly sample idling time in the case of failure. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 6 ++++-- arch/arm/mach-tegra/cpuidle-tegra30.c | 4 +--- arch/arm/mach-tegra/pm.c | 8 ++++++-- arch/arm/mach-tegra/pm.h | 2 +- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index f7d5041e73cc..9789541adb7d 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -87,15 +87,17 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + bool ret; + while (!tegra_cpu_rail_off_ready()) cpu_relax(); - tegra_idle_lp2_last(); + ret = !tegra_idle_lp2_last(); if (cpu_online(1)) tegra20_wake_cpu1_from_reset(); - return true; + return ret; } #ifdef CONFIG_SMP diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index a3ce8dabfe18..17cbd118abee 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -68,9 +68,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, return false; } - tegra_idle_lp2_last(); - - return true; + return !tegra_idle_lp2_last(); } #ifdef CONFIG_SMP diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index a72f9a2d3cb7..a094acaca307 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -189,14 +189,16 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) tegra_pmc_enter_suspend_mode(mode); } -void tegra_idle_lp2_last(void) +int tegra_idle_lp2_last(void) { + int err; + tegra_pm_set(TEGRA_SUSPEND_LP2); cpu_cluster_pm_enter(); suspend_cpu_complex(); - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); /* * Resume L2 cache if it wasn't re-enabled early during resume, @@ -208,6 +210,8 @@ void tegra_idle_lp2_last(void) restore_cpu_complex(); cpu_cluster_pm_exit(); + + return err; } enum tegra_suspend_mode tegra_pm_validate_suspend_mode( diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 2c294f6365c0..7d72f31dee77 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,7 +25,7 @@ void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); void tegra_set_cpu_in_lp2(void); -void tegra_idle_lp2_last(void); +int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP From patchwork Wed Feb 12 23:51:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F4FFC352A4 for ; Wed, 12 Feb 2020 23:52:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0451221569 for ; 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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:15 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 06/17] ARM: tegra: Expose PM functions required for new cpuidle driver Date: Thu, 13 Feb 2020 02:51:23 +0300 Message-Id: <20200212235134.12638-7-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/ directory and it will require all these exposed Tegra PM-core functions. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra114.c | 3 +- arch/arm/mach-tegra/cpuidle-tegra20.c | 2 +- arch/arm/mach-tegra/cpuidle-tegra30.c | 3 +- arch/arm/mach-tegra/irq.c | 3 +- arch/arm/mach-tegra/pm.h | 8 ----- arch/arm/mach-tegra/sleep.h | 1 - arch/arm/mach-tegra/tegra.c | 1 - .../mach-tegra => include/soc/tegra}/irq.h | 8 +++-- include/soc/tegra/pm.h | 31 +++++++++++++++++++ 9 files changed, 43 insertions(+), 17 deletions(-) rename {arch/arm/mach-tegra => include/soc/tegra}/irq.h (59%) diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 5118f777fd66..2d8527837aeb 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -12,13 +12,14 @@ #include +#include + #include #include #include #include #include "cpuidle.h" -#include "pm.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 9789541adb7d..fdfe92068e38 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -27,7 +28,6 @@ #include "cpuidle.h" #include "iomap.h" #include "irq.h" -#include "pm.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 17cbd118abee..3e91c29891f7 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -17,12 +17,13 @@ #include #include +#include + #include #include #include #include "cpuidle.h" -#include "pm.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index ace7a390b5fe..4e1ee70b2a3f 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,9 +18,10 @@ #include #include +#include + #include "board.h" #include "iomap.h" -#include "irq.h" #define SGI_MASK 0xFFFF diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 7d72f31dee77..81525f5f4a44 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,20 +23,12 @@ void tegra20_sleep_core_init(void); void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); -void tegra_clear_cpu_in_lp2(void); -void tegra_set_cpu_in_lp2(void); -int tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); #ifdef CONFIG_PM_SLEEP void tegra_init_suspend(void); -int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline void tegra_init_suspend(void) {} -static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) -{ - return -ENOTSUPP; -} #endif #endif /* _MACH_TEGRA_PM_H_ */ diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4978def9db46..4718a3cb45a1 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -122,7 +122,6 @@ void tegra20_hotplug_shutdown(void); void tegra30_hotplug_shutdown(void); void tegra20_tear_down_cpu(void); -int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 1e3b85923ca3..79184a077c84 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -42,7 +42,6 @@ #include "common.h" #include "cpuidle.h" #include "iomap.h" -#include "irq.h" #include "pm.h" #include "reset.h" #include "sleep.h" diff --git a/arch/arm/mach-tegra/irq.h b/include/soc/tegra/irq.h similarity index 59% rename from arch/arm/mach-tegra/irq.h rename to include/soc/tegra/irq.h index 7a94cf121448..8eb11a7109e4 100644 --- a/arch/arm/mach-tegra/irq.h +++ b/include/soc/tegra/irq.h @@ -3,9 +3,11 @@ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. */ -#ifndef __TEGRA_IRQ_H -#define __TEGRA_IRQ_H +#ifndef __SOC_TEGRA_IRQ_H +#define __SOC_TEGRA_IRQ_H +#if defined(CONFIG_ARM) bool tegra_pending_sgi(void); - #endif + +#endif /* __SOC_TEGRA_IRQ_H */ diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 951fcd738d55..1974e8405098 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -6,6 +6,8 @@ #ifndef __SOC_TEGRA_PM_H__ #define __SOC_TEGRA_PM_H__ +#include + enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -20,6 +22,12 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); /* low-level resume entry point */ void tegra_resume(void); + +int tegra30_sleep_cpu_secondary_finish(unsigned long arg); +void tegra_clear_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); +int tegra_idle_lp2_last(void); +int tegra_pm_park_secondary_cpu(unsigned long cpu); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -30,6 +38,29 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) static inline void tegra_resume(void) { } + +static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg) +{ + return -ENOTSUPP; +} + +static inline void tegra_clear_cpu_in_lp2(void) +{ +} + +static inline void tegra_set_cpu_in_lp2(void) +{ +} + +static inline int tegra_idle_lp2_last(void) +{ + return -ENOTSUPP; +} + +static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) +{ + return -ENOTSUPP; +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ From patchwork Wed Feb 12 23:51:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E18CC3B187 for ; Wed, 12 Feb 2020 23:53:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 054DB206E5 for ; Wed, 12 Feb 2020 23:53:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lxqydUiP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729545AbgBLXw7 (ORCPT ); Wed, 12 Feb 2020 18:52:59 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:39140 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729370AbgBLXwT (ORCPT ); Wed, 12 Feb 2020 18:52:19 -0500 Received: by mail-lj1-f194.google.com with SMTP id o15so4437206ljg.6; Wed, 12 Feb 2020 15:52:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fS4gtNJrSYUjQQXOqqY/Oa93RASY09H9Tmcfh+YVDHY=; b=lxqydUiPnuXLChUwnee3i+KTHQwL+gubcerAHl5rh65Fzon23/BCEBKHAtoW2/clVR EwFx+n+eM0aj/UwPjhuj77J/gOwEn20HKTSwTUXvGApG8ciViGailWbVQAsmFSssToOz 8KcLhOuRpq3rxQQMxbHyjRBbVKdtBDtqWEREE8VqTXueKvp/d0imqQU35ZFdkP/ED+eF 7nL2WWoyICbj4b9PSQWDNnwEjY2wSh4810RgyfD/5OAvVC/x705DgTPCkKM5m9aqGvph FiJ6UcxSZ7FbgPi0rNOcUT6luSOwMVdPMLTcYlciTprqfIKjmugNP+UL/nGPLNiTHElt VseA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fS4gtNJrSYUjQQXOqqY/Oa93RASY09H9Tmcfh+YVDHY=; b=Odj0K6NJHxjS9G9BXI9FWSEdeny0lnMh4V11d+YLugVwCT2JdReVJbHFvpKQQn0neZ /gGonjwsG4JNU1wddLFxgJVF4pHCYZe/gZzpmzzJ9NhCDWghF3YZMlVHeUgoflVhQO6a zOiRIEV6X3gCN+Of2Pd8v0LDfV2j3Y1q8m+QC/c9PKISg+iwwzgC3QXfGti/kL9i2qWD QbTRVQi+UvdlPFemJMkjiQd5/Xntit3zzJxGYFvcg9buajgNyDCDDCzZj8VhepDkmOnj F1lTsbzrIOE0IJ3bOKTqcGNhTJmaH/mocmBDK1M8Orj9AciCSvRKb+UQ6tEyugdtPpSz IOgQ== X-Gm-Message-State: APjAAAUxEt3KuCfDMhOcf2IOvhB81s20Xd7FXFiQmq1rB5N7WGmrZzXD jsuHLNPSO5eLqf2y0c30iho= X-Google-Smtp-Source: APXvYqyrlY6DZo0Cd476tLwaHEZumaspt5hBJRv94qqezEburO4GEYyMUH4Ohjm0dZHpnq4qUwo7KQ== X-Received: by 2002:a2e:8015:: with SMTP id j21mr9099962ljg.172.1581551537702; Wed, 12 Feb 2020 15:52:17 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:17 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 08/17] ARM: tegra: Make outer_disable() open-coded Date: Thu, 13 Feb 2020 02:51:25 +0300 Message-Id: <20200212235134.12638-9-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The outer_disable() of Tegra's suspend code is open-coded now since that helper produces spurious warning message about secondary CPUs being online when CPU enters into LP2 from cpuidle. The secondaries are actually halted by the cpuidle driver on entering into LP2 idle-state, but the online status is not touched by the cpuidle. This fixes a storm of warnings once LP2 idling state is enabled on Tegra30. The outer_disable() helper has sanity checks for interrupts and secondary CPUs being disabled and we are pretty confident about the interrupts state during of CPU idling / system suspend. The rail-off status check is added in this patch as equivalent for the "num_online_cpus() > 1". Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 7d9ef26e52a7..d1e1a61b12cf 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -138,6 +138,10 @@ void tegra_pm_set_cpu_in_lp2(void) static int tegra_sleep_cpu(unsigned long v2p) { + if (tegra_cpu_car_ops->rail_off_ready && + WARN_ON(!tegra_cpu_rail_off_ready())) + return -EBUSY; + /* * L2 cache disabling using kernel API only allowed when all * secondary CPU's are offline. Cache have to be disabled with @@ -146,9 +150,10 @@ static int tegra_sleep_cpu(unsigned long v2p) * if any of secondary CPU's is online and this is the LP2-idle * code-path only for Tegra20/30. */ - if (trusted_foundations_registered()) - outer_disable(); - +#ifdef CONFIG_OUTER_CACHE + if (trusted_foundations_registered() && outer_cache.disable) + outer_cache.disable(); +#endif /* * Note that besides of setting up CPU reset vector this firmware * call may also do the following, depending on the FW version: From patchwork Wed Feb 12 23:51:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88DD2C3B186 for ; Wed, 12 Feb 2020 23:52:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5BF8C2173E for ; Wed, 12 Feb 2020 23:52:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lbM0xqpc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729523AbgBLXwu (ORCPT ); Wed, 12 Feb 2020 18:52:50 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:40954 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729402AbgBLXwX (ORCPT ); Wed, 12 Feb 2020 18:52:23 -0500 Received: by mail-lj1-f195.google.com with SMTP id n18so4428281ljo.7; Wed, 12 Feb 2020 15:52:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0sLX75wuAzd6+MMz3Hu9LnmvekmEH4xItVN4J4n6aik=; b=lbM0xqpcsuUE2KPCHz7Ns9UiE49LiAjMu2waKekvSELjm7B7oSgNab/qOKV5IgOHji 70mD6nk+0GOtN+I5KtGfVEuqmDuDzdtRdZw62MgPzIjTwdko2z+ayI2XrLryUE1I5YV2 4rDIL3LAxliytyDqGN4+6PFsZtkNYTQ7jdAEtCDMQ97TmoDzDwMLmSfJwoG8j6lGxGB2 HsSWQmlxxru7PVVy4hbF5G7AbHiACD8avoEVbQGOQK5PmfuDQTL6Wx2eAYrw4mxUZZWZ WMc/hpJPiNE1d3m2OVaRwAJ9KeTYrHIooH1C8FNc6XSQnslaxW1f8MSqZZ3QwNre1nPd sP4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0sLX75wuAzd6+MMz3Hu9LnmvekmEH4xItVN4J4n6aik=; b=hWO5+mAwZp5aIOH8CIhhaG0FUmYoyPdGjXJHPa7rD2d/jPgUcxrkK0qs5YJfzEVEoS oerUp/Se23GSOIARWqkPgZUaoGP58rAElozGJE3CY5ZMOSOAYUogw1BBueYBlycrsRIM 0gSfo7t00HNWotm19vLT/8H/lKSbKi4xhMc9JNHevytoqyX7OLgGTElMv/uv8U5orDTh 16rOla5CDbZGllbS3ArdVdCvWxbIMgUCRxNuBzVPX6nNYLO8c9jYoEBJgCq/XTb6YOIw Ot56iPMckk/RQ3/Bs+4aMwLt4DxfzKK8CY2rQ6Py3cUDeJl5G/00rB000EsFcgdouk46 1L8w== X-Gm-Message-State: APjAAAUa2PEcIy0fPtd0ucYtO5a6Gd2gwLICQYfXAllyH4/MEjk6a6f6 ilML8ZnlA/USz+pklapINu4= X-Google-Smtp-Source: APXvYqyyvNchlbrlwSt+ADuQS9jaIbzHQ/OYWfHnBk18q1l60mPKIz222c45FzndN2chq91/OKRsNg== X-Received: by 2002:a2e:8016:: with SMTP id j22mr8732133ljg.24.1581551540814; Wed, 12 Feb 2020 15:52:20 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:20 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 11/17] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier Date: Thu, 13 Feb 2020 02:51:28 +0300 Message-Id: <20200212235134.12638-12-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is no good justification for smp_rmb() after returning from LP2 because there are no memory operations that require SMP synchronization. Thus remove the confusing barrier. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/cpuidle-tegra20.c | 2 -- arch/arm/mach-tegra/cpuidle-tegra30.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index ccb8b0aa6c46..f8f14c0b79ff 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -194,8 +194,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, local_fiq_enable(); - smp_rmb(); - return entered_lp2 ? index : 0; } #endif diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index a4f0add46a27..80ae64bcdf50 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -113,8 +113,6 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, local_fiq_enable(); - smp_rmb(); - return (entered_lp2) ? index : 0; } #endif From patchwork Wed Feb 12 23:51:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF4B9C352A4 for ; Wed, 12 Feb 2020 23:52:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B89C921569 for ; Wed, 12 Feb 2020 23:52:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Py1K763F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729521AbgBLXwu (ORCPT ); Wed, 12 Feb 2020 18:52:50 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:42468 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729422AbgBLXw0 (ORCPT ); Wed, 12 Feb 2020 18:52:26 -0500 Received: by mail-lf1-f68.google.com with SMTP id y19so2865178lfl.9; Wed, 12 Feb 2020 15:52:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bb/8PsOZHm1+EN8uN3fVWmZcFUvkOwnzeg4adZDUabE=; b=Py1K763F/buPvOGOgWMvRhTzFZo2iSO/6dwj+S/He/Uv1K66QSeJy7+rIJGsw/Kadp TRg2FQZxIGTNfLb/DrEV3UaiV6xdR78gz7LiB0vvx4vTSY1Y9A/SWuzcqGG7VCTSr0+4 E2asXZnQqbLtMd3fYCqRuzDP3FjHBg43WIYId5B/SwLAZMkIxbJoBUXlBGB34io/1gtG i1afx9+llTjFYf0Ol0fo5QHTFpxq+JiQwfDLUAAA4tV/eakVpE8bwdz93/erkzD2EuVf Wm7/Kh7NdDT1q5YRd70qSKjF449AR5C0CHGUU/p9/4xKNYNPL4Gsa6P7UcRmM6AwcLM6 iwVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bb/8PsOZHm1+EN8uN3fVWmZcFUvkOwnzeg4adZDUabE=; b=DEkqq4DFwUCG9oRPq3+a2AUqES8/npGoC7m5bSWBB4ZEs+bMmzJH/eBPomllW0HdFY +PalAzNuJABQ+8u3Z79lq8krFpVRjkuMTezGtF7uFzkzVVykvYbfT/0AWqEwb3vVT7uB ui4+za/l3Iwg/92Hpw4fKJkjfprWUeBwKQ25qYrIdsAehPCdeFsELD3E0UF0S7tPwE+1 43sUMBaHoUSzFWXX50F5/68g4FAdwzpLbdeBiPSqBTxJPMGLqtiv4/uAZLWFZyeIiIQA 2Qh9dX1E7QAkAatX0Foytpp74Sf5GdwXMYLRIn5m0HSZjul6bPCpsly/C9cyT80pirAN D/HQ== X-Gm-Message-State: APjAAAVJHD38/AfBaMaZbktHXMZS4OiTx6Yn7Yk8MnVaRznSfsq6CsMv 55UUZFJLaa7Qgld/ATMmRuw= X-Google-Smtp-Source: APXvYqzkBCwHj9XeTXAC3zOxKwf0gSREVGekVgvpQVyqvZlBrh+YeJdQkfk/69vgrPRQIldiIDqW+w== X-Received: by 2002:ac2:597b:: with SMTP id h27mr7770261lfp.12.1581551543000; Wed, 12 Feb 2020 15:52:23 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:22 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 13/17] cpuidle: tegra: Squash Tegra30 driver into the common driver Date: Thu, 13 Feb 2020 02:51:30 +0300 Message-Id: <20200212235134.12638-14-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra20 and Terga30 SoCs have common C1 and CC6 idling states and thus share the same code paths, there is no point in having separate drivers for a similar hardware. This patch merely moves functionality of the old driver into the new, although the CC6 state is kept disabled for now since old driver had a rudimentary support for this state (allowing to enter into CC6 only when secondary CPUs are put offline), while new driver can provide a full-featured support. The new feature will be enabled by another patch. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 3 - arch/arm/mach-tegra/cpuidle-tegra30.c | 123 -------------------------- arch/arm/mach-tegra/cpuidle.c | 5 +- arch/arm/mach-tegra/cpuidle.h | 1 - drivers/cpuidle/cpuidle-tegra.c | 74 ++++++++++++++-- 5 files changed, 70 insertions(+), 136 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 8425bb5608d5..99c5f4274e5c 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -13,9 +13,6 @@ obj-y += sleep-tegra30.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o -endif obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c deleted file mode 100644 index 80ae64bcdf50..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include "cpuidle.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, -#ifdef CONFIG_PM_SLEEP - .state_count = 2, -#else - .state_count = 1, -#endif - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra30_idle_lp2, - .exit_latency = 2000, - .target_residency = 2200, - .power_usage = 0, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -#ifdef CONFIG_PM_SLEEP -static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - /* All CPUs entering LP2 is not working. - * Don't let CPU0 enter LP2 when any secondary CPU is online. - */ - if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) { - cpu_do_idle(); - return false; - } - - return !tegra_pm_enter_lp2(); -} - -#ifdef CONFIG_SMP -static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - smp_wmb(); - - cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); - - return true; -} -#else -static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return true; -} -#endif - -static int tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - bool entered_lp2 = false; - - local_fiq_disable(); - - tegra_pm_set_cpu_in_lp2(); - cpu_pm_enter(); - - if (dev->cpu == 0) - entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index); - else - entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index); - - cpu_pm_exit(); - tegra_pm_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return (entered_lp2) ? index : 0; -} -#endif - -int __init tegra30_cpuidle_init(void) -{ - return cpuidle_register(&tegra_idle_driver, NULL); -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index eee85d517783..fa0dcf3c2c45 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -24,11 +24,8 @@ void __init tegra_cpuidle_init(void) { switch (tegra_get_chip_id()) { case TEGRA20: - platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); - break; case TEGRA30: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) - tegra30_cpuidle_init(); + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); break; case TEGRA114: case TEGRA124: diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index eeb37baf18e1..5423a05a69f6 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -7,7 +7,6 @@ #define __MACH_TEGRA_CPUIDLE_H #ifdef CONFIG_CPU_IDLE -int tegra30_cpuidle_init(void); int tegra114_cpuidle_init(void); void tegra_cpuidle_init(void); #else diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index a58d2773d45f..59398c76cf68 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -37,6 +37,7 @@ enum tegra_state { TEGRA_C1, + TEGRA_C7, TEGRA_CC6, TEGRA_STATE_COUNT, }; @@ -119,6 +120,11 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu) return ret; } +static int tegra_cpuidle_c7_enter(void) +{ + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); +} + static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev) { if (tegra_pending_sgi()) { @@ -166,6 +172,10 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, cpu_pm_enter(); switch (index) { + case TEGRA_C7: + ret = tegra_cpuidle_c7_enter(); + break; + case TEGRA_CC6: ret = tegra_cpuidle_cc6_enter(cpu); break; @@ -182,6 +192,24 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev, return ret; } +static int tegra_cpuidle_adjust_state_index(int index, unsigned int cpu) +{ + /* + * On Tegra30 CPU0 can't be power-gated separately from secondary + * cores because it gates the whole CPU cluster. + */ + if (cpu > 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30) + return index; + + /* put CPU0 into C1 if C7 is requested and secondaries are online */ + if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1) + index = TEGRA_C1; + else + index = TEGRA_CC6; + + return index; +} + static int tegra_cpuidle_enter(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -189,10 +217,17 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev, unsigned int cpu = cpu_logical_map(dev->cpu); int err; - err = tegra_cpuidle_state_enter(dev, index, cpu); - if (err && err != -EINTR) - pr_err_once("cpu%u failed to enter idle state %d err: %d\n", - cpu, index, err); + index = tegra_cpuidle_adjust_state_index(index, cpu); + if (dev->states_usage[index].disable) + return -1; + + if (index == TEGRA_C1) + err = arm_cpuidle_simple_enter(dev, drv, index); + else + err = tegra_cpuidle_state_enter(dev, index, cpu); + + if (err && (err != -EINTR || index != TEGRA_CC6)) + pr_err_once("failed to enter state %d err: %d\n", index, err); return err ? -1 : index; } @@ -218,6 +253,15 @@ static struct cpuidle_driver tegra_idle_driver = { .name = "tegra_idle", .states = { [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600), + [TEGRA_C7] = { + .enter = tegra_cpuidle_enter, + .exit_latency = 2000, + .target_residency = 2200, + .power_usage = 100, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .name = "C7", + .desc = "CPU core powered off", + }, [TEGRA_CC6] = { .enter = tegra_cpuidle_enter, .exit_latency = 5000, @@ -262,8 +306,28 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) * Tegra-arch core and PMC driver, is unavailable if PM-sleep option * is disabled. */ - if (!IS_ENABLED(CONFIG_PM_SLEEP)) + if (!IS_ENABLED(CONFIG_PM_SLEEP)) { + tegra_cpuidle_disable_state(TEGRA_C7); tegra_cpuidle_disable_state(TEGRA_CC6); + } + + /* + * Generic WFI state (also known as C1 or LP3) and the coupled CPU + * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs. + */ + switch (tegra_get_chip_id()) { + case TEGRA20: + /* Tegra20 isn't capable to power-off individual CPU cores */ + tegra_cpuidle_disable_state(TEGRA_C7); + break; + + case TEGRA30: + tegra_cpuidle_disable_state(TEGRA_CC6); + break; + + default: + return -EINVAL; + } return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); } From patchwork Wed Feb 12 23:51:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBFFAC3B187 for ; Wed, 12 Feb 2020 23:52:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9828A21569 for ; Wed, 12 Feb 2020 23:52:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="m4fQY12S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729392AbgBLXw3 (ORCPT ); Wed, 12 Feb 2020 18:52:29 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:38331 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729429AbgBLXw3 (ORCPT ); Wed, 12 Feb 2020 18:52:29 -0500 Received: by mail-lj1-f196.google.com with SMTP id w1so4444415ljh.5; Wed, 12 Feb 2020 15:52:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZKEEZIia8R+ufMZWjFtVAJL8Wre5/H1rF2/jJQIGBGg=; b=m4fQY12SqUzQHyxpRJUHyXz6BFEdQvraUAgNdKXyz7sjTnAuhwB/OTWlh30h3o4c+k pzgto4F3tLepTxZCLuhL1zyY/G29vLM+n6RsGjpN2A4ST+ldtZTLMG0r5qM8KTtzjhh8 3mXIffaLTswJZEcnvrTJynAow/DmUCIf9ILxUZH4IGspgJdmp4MHQkkMR7bblLa+GTT+ FS3DO8Cu7Nzv4TCdJv47UQ+lmjbWcWpo8+o+/+ogDHaOClX4rqEowQO3MZOQv31uCHTv +kfivUIKE0VbHep7WYCebph/zbX9pbTO8gedZw6ANSdwgdVM7KpxDm7QVxDjKphEVGLk W9Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZKEEZIia8R+ufMZWjFtVAJL8Wre5/H1rF2/jJQIGBGg=; b=r7gD1izPMyx+2RRBgFKw0MtgqQ2T647FGoKpLe1d+xWhcBUvG3EPh2WOhdEvuhZ8g3 RibHxzzxXrVRxMJgY2cLl7XF/og6fzqto8JzpDo3lDsA6YBkIcnqqbuYbBhp8ghtf3aL AJASzVN4DUyRnZSzD7vPRBPRvfmVP94vqknOVS892QeMtNLNuPnPTjtoO+3i8Asy+5wm 1IjmDzTUDUwdmD/k2HWya1Aro4kt0/xlyBjtgE6C3nf3pCj81MNqrLRaKnHPQJhegzXY TYmivsv9mdiLuscxgvGXsKV5PeBFEn83TwOWDZ729mQ0jf/eyNPu34I0Lyj20O1SpFKT SGzA== X-Gm-Message-State: APjAAAVXJG2SbZkZiq1H+aN+bMyunHWCfLzEwJ8ZSuSTFJTklTovpB8H a2S2o+12xp42MZnv8TIJ96M= X-Google-Smtp-Source: APXvYqxghIoDycVMmsm5aCQcQ6Ll5wI7EkkX9K63v2Ob6IlobniAFg1HEBJmqFxQJPAr3URWm1SaJQ== X-Received: by 2002:a05:651c:239:: with SMTP id z25mr8934769ljn.48.1581551544655; Wed, 12 Feb 2020 15:52:24 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:24 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 14/17] cpuidle: tegra: Squash Tegra114 driver into the common driver Date: Thu, 13 Feb 2020 02:51:31 +0300 Message-Id: <20200212235134.12638-15-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra20/30/114/124 SoCs have common idling states, thus there is no much point in having separate drivers for a similar hardware. This patch moves Tegra114/124 arch/ drivers into the common driver without any functional changes. The CC6 state is kept disabled on Tegra114/124 because the core Tegra PM code needs some more work in order to support that state. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/Makefile | 7 -- arch/arm/mach-tegra/cpuidle-tegra114.c | 90 -------------------------- arch/arm/mach-tegra/cpuidle.c | 37 ----------- arch/arm/mach-tegra/cpuidle.h | 16 ----- arch/arm/mach-tegra/tegra.c | 6 +- drivers/cpuidle/cpuidle-tegra.c | 45 ++++++++++++- 6 files changed, 48 insertions(+), 153 deletions(-) delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c delete mode 100644 arch/arm/mach-tegra/cpuidle.c delete mode 100644 arch/arm/mach-tegra/cpuidle.h diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 99c5f4274e5c..07572b5373b8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -10,19 +10,12 @@ obj-y += sleep.o obj-y += tegra.o obj-y += sleep-tegra20.o obj-y += sleep-tegra30.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c deleted file mode 100644 index 858c30cc5dc7..000000000000 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include -#include - -#include "cpuidle.h" -#include "sleep.h" - -#ifdef CONFIG_PM_SLEEP -#define TEGRA114_MAX_STATES 2 -#else -#define TEGRA114_MAX_STATES 1 -#endif - -#ifdef CONFIG_PM_SLEEP -static int tegra114_idle_power_down(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - local_fiq_disable(); - - tegra_pm_set_cpu_in_lp2(); - cpu_pm_enter(); - - call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); - - /* Do suspend by ourselves if the firmware does not implement it */ - if (call_firmware_op(do_idle, 0) == -ENOSYS) - cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); - - cpu_pm_exit(); - tegra_pm_clear_cpu_in_lp2(); - - local_fiq_enable(); - - return index; -} - -static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - tegra114_idle_power_down(dev, drv, index); -} -#endif - -static struct cpuidle_driver tegra_idle_driver = { - .name = "tegra_idle", - .owner = THIS_MODULE, - .state_count = TEGRA114_MAX_STATES, - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), -#ifdef CONFIG_PM_SLEEP - [1] = { - .enter = tegra114_idle_power_down, - .enter_s2idle = tegra114_idle_enter_s2idle, - .exit_latency = 500, - .target_residency = 1000, - .flags = CPUIDLE_FLAG_TIMER_STOP, - .power_usage = 0, - .name = "powered-down", - .desc = "CPU power gated", - }, -#endif - }, -}; - -int __init tegra114_cpuidle_init(void) -{ - if (!psci_smp_available()) - return cpuidle_register(&tegra_idle_driver, NULL); - - return 0; -} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c deleted file mode 100644 index fa0dcf3c2c45..000000000000 --- a/arch/arm/mach-tegra/cpuidle.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-tegra/cpuidle.c - * - * CPU idle driver for Tegra CPUs - * - * Copyright (c) 2010-2012, NVIDIA Corporation. - * Copyright (c) 2011 Google, Inc. - * Author: Colin Cross - * Gary King - * - * Rework for 3.3 by Peter De Schrijver - */ - -#include -#include -#include - -#include - -#include "cpuidle.h" - -void __init tegra_cpuidle_init(void) -{ - switch (tegra_get_chip_id()) { - case TEGRA20: - case TEGRA30: - platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); - break; - case TEGRA114: - case TEGRA124: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) - tegra114_cpuidle_init(); - break; - } -} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h deleted file mode 100644 index 5423a05a69f6..000000000000 --- a/arch/arm/mach-tegra/cpuidle.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. - */ - -#ifndef __MACH_TEGRA_CPUIDLE_H -#define __MACH_TEGRA_CPUIDLE_H - -#ifdef CONFIG_CPU_IDLE -int tegra114_cpuidle_init(void); -void tegra_cpuidle_init(void); -#else -static inline void tegra_cpuidle_init(void) {} -#endif - -#endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 79184a077c84..eeacff626546 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -36,11 +36,11 @@ #include #include #include +#include #include #include "board.h" #include "common.h" -#include "cpuidle.h" #include "iomap.h" #include "pm.h" #include "reset.h" @@ -85,7 +85,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { tegra_init_suspend(); - tegra_cpuidle_init(); if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("compal,paz00")) @@ -98,6 +97,9 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && of_machine_is_compatible("nvidia,tegra30")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) + platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c index 59398c76cf68..b6cdad8437af 100644 --- a/drivers/cpuidle/cpuidle-tegra.c +++ b/drivers/cpuidle/cpuidle-tegra.c @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -32,6 +33,7 @@ #include #include +#include #include #include @@ -45,6 +47,11 @@ enum tegra_state { static atomic_t tegra_idle_barrier; static atomic_t tegra_abort_flag; +static inline bool tegra_cpuidle_using_firmware(void) +{ + return firmware_ops->prepare_idle && firmware_ops->do_idle; +} + static void tegra_cpuidle_report_cpus_state(void) { unsigned long cpu, lcpu, csr; @@ -122,6 +129,16 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu) static int tegra_cpuidle_c7_enter(void) { + int err; + + if (tegra_cpuidle_using_firmware()) { + err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2); + if (err) + return err; + + return call_firmware_op(do_idle, 0); + } + return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend); } @@ -232,6 +249,13 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev, return err ? -1 : index; } +static void tegra114_enter_s2idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + tegra_cpuidle_enter(dev, drv, index); +} + /* * The previous versions of Tegra CPUIDLE driver used a different "legacy" * terminology for naming of the idling states, while this driver uses the @@ -299,6 +323,15 @@ void tegra_cpuidle_pcie_irqs_in_use(void) tegra_cpuidle_disable_state(TEGRA_CC6); } +static void tegra_cpuidle_setup_tegra114_c7_state(void) +{ + struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7]; + + s->enter_s2idle = tegra114_enter_s2idle; + s->target_residency = 1000; + s->exit_latency = 500; +} + static int tegra_cpuidle_probe(struct platform_device *pdev) { /* @@ -307,7 +340,9 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) * is disabled. */ if (!IS_ENABLED(CONFIG_PM_SLEEP)) { - tegra_cpuidle_disable_state(TEGRA_C7); + if (!tegra_cpuidle_using_firmware()) + tegra_cpuidle_disable_state(TEGRA_C7); + tegra_cpuidle_disable_state(TEGRA_CC6); } @@ -325,6 +360,14 @@ static int tegra_cpuidle_probe(struct platform_device *pdev) tegra_cpuidle_disable_state(TEGRA_CC6); break; + case TEGRA114: + case TEGRA124: + tegra_cpuidle_setup_tegra114_c7_state(); + + /* coupled CC6 (LP2) state isn't implemented yet */ + tegra_cpuidle_disable_state(TEGRA_CC6); + break; + default: return -EINVAL; } From patchwork Wed Feb 12 23:51:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 212872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07E12C352A4 for ; Wed, 12 Feb 2020 23:52:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CC38621569 for ; Wed, 12 Feb 2020 23:52:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OU7ZIoH6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729454AbgBLXw3 (ORCPT ); Wed, 12 Feb 2020 18:52:29 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:40050 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729434AbgBLXw3 (ORCPT ); Wed, 12 Feb 2020 18:52:29 -0500 Received: by mail-lf1-f68.google.com with SMTP id c23so2875762lfi.7; Wed, 12 Feb 2020 15:52:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zsiGVctojQQ/6++c4wQ+fRDwiUrqLwmb6/O4RUjlNXE=; b=OU7ZIoH6xa+RHKvzKulLNccHwssYjB1zeJg521ypdoR6sRKoJsmJ2nKPcwohrYHCZr m+j5R/XsjR3vmmdB2r9Rqq2qyYCGq4iX/6ftkIdcJtaPhgQix9G1jallZ3WficK/4MyQ 81LYxBMqhzu/g+JvedxO0kgLrr/99RoACcF63aPmxxQJWzxLC7wfoFPexwTRFnWNic4w j7kVxrxPNAhbbswkCE0VrSTNDqOIUvcXvAQPSONtrsTyeRNKpLS7sqCBwXZuobxzu327 6889rNENjD6+Do/lERUsdv1qmd/1ZOfnR5KaD3xnchMeu8s5q1+At+JiUKAxCQ2PTudD qoxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zsiGVctojQQ/6++c4wQ+fRDwiUrqLwmb6/O4RUjlNXE=; b=Nd0v8/CJwNxuFZQxWsoU3uUfDFokqL4pXp7ioBPNj64E7k0A6ZHjGMNwiLbpU2Ampy KsYuj+ix/BYg4glAm9H9716tfclZs2KUqaPAQ9GV0tLkEqEvg9LAqUfyZwZfkoGsoJRG 6ay3BGys6Wm02/JqlW/FfqOf8OcYs6FiVXr+8Uw9CZ/ZWye0SflHH2UzDI+BgjDeJvQo Dk41kUt/yTUjAQU+HyBC2QwSgyg18tf+iD35qZqv9V60tSQ3Ro7S0t9/p09iAW6d4afS 5Jgji6sWKIQHUvrihKmZr94DUbPNfm9rIEYydLwUY+Ns7n1kGxFL/JL5I57FjhU0fSeG nV/Q== X-Gm-Message-State: APjAAAWNslwnhU3LyGBCpWn661fvXiqS16R1GjOAkNOMfbcrbdZ6sFe4 EuBsKAuLw1ODYH3RrbNUAFY= X-Google-Smtp-Source: APXvYqznhcpF7KnI+KM7LHINL4een5Ysq+21b+f/U4l60sOASA+jqVYxQ1lri4YNGc2FKdl2s0EJDA== X-Received: by 2002:a19:9d5:: with SMTP id 204mr7661617lfj.120.1581551546802; Wed, 12 Feb 2020 15:52:26 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d5sm251686lfb.20.2020.02.12.15.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2020 15:52:26 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano , =?utf-8?q?Micha=C5=82_Miro?= =?utf-8?b?c8WCYXc=?= , Jasper Korten , David Heidelberg , Peter Geis Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 16/17] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Date: Thu, 13 Feb 2020 02:51:33 +0300 Message-Id: <20200212235134.12638-17-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20200212235134.12638-1-digetx@gmail.com> References: <20200212235134.12638-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 017d65f86eba..7c8a1c310bbb 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -113,6 +113,7 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y +CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y