From patchwork Mon Mar 16 10:01:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolin Wang X-Patchwork-Id: 211105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0C80C3F2CE for ; Mon, 16 Mar 2020 10:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D63A2051A for ; Mon, 16 Mar 2020 10:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PortRNUL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730539AbgCPKBs (ORCPT ); Mon, 16 Mar 2020 06:01:48 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:40982 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730518AbgCPKBq (ORCPT ); Mon, 16 Mar 2020 06:01:46 -0400 Received: by mail-pl1-f194.google.com with SMTP id t16so746858plr.8; Mon, 16 Mar 2020 03:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=kgihqax6YeVrCLuO9o57/Db7OP77DO8IEq6SMDC5Qo8=; b=PortRNULQehrdmz+1FjlpE+FsZhu8X5GiKYISyqGV8WLLJR6gDJp+0LK1eSi3qTS/b DblqcKk1vVUDBY/g/5CSwFNEsRvG9SHOWDkeMbO31qwg0m7IcZpdYFFnTo7kXy7ajWad WkY5FPflcExVdKbLeB7ycKHqi7f41tF2TNbVtPQgpYRiUe94kd0P1DTajdn5gGHZrAOw U+ABDadCN0+WhuE/N7LQhDcL8uA9Mm/9Wgji6/XAyxupjV4N6uiraCaKXy/YyG6MgFSu gfebjTCjiznZ3lAEXUhPkSYQArVEsGQlxTxO7R19Jn3LYUyqeqg+NDukZAOduHQR5cUw Yesg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=kgihqax6YeVrCLuO9o57/Db7OP77DO8IEq6SMDC5Qo8=; b=kReQwzjxIcMUKF9Xjm9l8D7INPSjzKSa4PdPXsfsu/M5YUhJu7feEFlf4Wzu2Ddo3N n1ZWqGA1FVXg25hGETmHiwb7WYP26R7L7lEHMVGvtdKeW/BB6lT9SdRy4AltBTIayN/+ Un57ld7IJzFR2l5iQBhbudQeq0cCvkR8vuVvQ6qsfzBn3W2F3O4YvG67iKLEAEem/YWj vYGF2L3ExsZLcDieIZg/EkCmTn+4GhqwBxgZn+J/vVhQO0Wv6C8KhCKeZ390OT6alAgF waYHNs9P0fK7yNC3UXY0tsaOEG+NDSitmHab340oXJlnZSBFOTx+seHVJh57ilQwdpju ygFA== X-Gm-Message-State: ANhLgQ3TTVeL7s4aISdSD/iT2r5OSt3QrzdRGH5s66XPd/1OBZfPEs/c iHQcPlKBqKvEu803MSRLqDDduP1i X-Google-Smtp-Source: ADFU+vvnsLXtTZlSGMbwwvTQ6Lw0KA0Xp8VXqWdE7tOLnB7L0w2mToRedqylW/p5JhGioHwpWJEJsQ== X-Received: by 2002:a17:90b:1a8f:: with SMTP id ng15mr21129827pjb.55.1584352906128; Mon, 16 Mar 2020 03:01:46 -0700 (PDT) Received: from sh03840pcu.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id 136sm63970411pgh.26.2020.03.16.03.01.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 16 Mar 2020 03:01:45 -0700 (PDT) From: Baolin Wang To: axboe@kernel.dk, paolo.valente@linaro.org, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: ming.lei@redhat.com, arnd@arndb.de, linus.walleij@linaro.org, baolin.wang7@gmail.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-mmc@vger.kernel.org, linux-block@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH 2/8] block: Allow sending a batch of requests from the scheduler to hardware Date: Mon, 16 Mar 2020 18:01:19 +0800 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org As we know, some SD/MMC host controllers can support packed request, that means we can package several requests to host controller at one time to improve performence. So the hardware driver expects the blk-mq can dispatch a batch of requests at one time, and driver can use bd.last to indicate if it is the last request in the batch to help to combine requests as much as possible. Thus we should add batch requests setting from the block driver to tell the scheduler how many requests can be dispatched in a batch, as well as changing the scheduler to dispatch more than one request if setting the maximum batch requests number. Signed-off-by: Baolin Wang --- block/bfq-iosched.c | 32 ++++++++++++++-------- block/blk-mq.c | 2 -- block/blk-settings.c | 13 +++++++++ block/kyber-iosched.c | 74 +++++++++++++++++++++++++++----------------------- block/mq-deadline.c | 20 ++++++++++---- include/linux/blkdev.h | 8 ++++++ 6 files changed, 95 insertions(+), 54 deletions(-) diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c index d7a128e..9c1e3aa 100644 --- a/block/bfq-iosched.c +++ b/block/bfq-iosched.c @@ -4793,29 +4793,37 @@ static int bfq_dispatch_requests(struct blk_mq_hw_ctx *hctx, struct list_head *list) { struct bfq_data *bfqd = hctx->queue->elevator->elevator_data; + unsigned int batch_reqs = queue_max_batch_requests(hctx->queue) ? : 1; struct request *rq; struct bfq_queue *in_serv_queue; bool waiting_rq, idle_timer_disabled; + int i; - spin_lock_irq(&bfqd->lock); + for (i = 0; i < batch_reqs; i++) { + spin_lock_irq(&bfqd->lock); - in_serv_queue = bfqd->in_service_queue; - waiting_rq = in_serv_queue && bfq_bfqq_wait_request(in_serv_queue); + in_serv_queue = bfqd->in_service_queue; + waiting_rq = in_serv_queue && bfq_bfqq_wait_request(in_serv_queue); - rq = __bfq_dispatch_request(hctx); + rq = __bfq_dispatch_request(hctx); - idle_timer_disabled = - waiting_rq && !bfq_bfqq_wait_request(in_serv_queue); + idle_timer_disabled = + waiting_rq && !bfq_bfqq_wait_request(in_serv_queue); - spin_unlock_irq(&bfqd->lock); + spin_unlock_irq(&bfqd->lock); - bfq_update_dispatch_stats(hctx->queue, rq, in_serv_queue, - idle_timer_disabled); + bfq_update_dispatch_stats(hctx->queue, rq, in_serv_queue, + idle_timer_disabled); - if (!rq) - return 0; + if (!rq) { + if (list_empty(list)) + return 0; - list_add(&rq->queuelist, list); + return 1; + } + + list_add(&rq->queuelist, list); + } return 1; } diff --git a/block/blk-mq.c b/block/blk-mq.c index a12b176..2588e7a 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1193,8 +1193,6 @@ bool blk_mq_dispatch_rq_list(struct request_queue *q, struct list_head *list, if (list_empty(list)) return false; - WARN_ON(!list_is_singular(list) && got_budget); - /* * Now process all the entries, sending them to the driver. */ diff --git a/block/blk-settings.c b/block/blk-settings.c index c8eda2e..8c0b325 100644 --- a/block/blk-settings.c +++ b/block/blk-settings.c @@ -59,6 +59,7 @@ void blk_set_default_limits(struct queue_limits *lim) lim->io_opt = 0; lim->misaligned = 0; lim->zoned = BLK_ZONED_NONE; + lim->max_batch_reqs = 1; } EXPORT_SYMBOL(blk_set_default_limits); @@ -871,6 +872,18 @@ bool blk_queue_can_use_dma_map_merging(struct request_queue *q, } EXPORT_SYMBOL_GPL(blk_queue_can_use_dma_map_merging); +/** + * blk_queue_max_batch_requests - set max requests for batch processing + * @q: the request queue for the device + * @max_batch_requests: maximum number of requests in a batch + **/ +void blk_queue_max_batch_requests(struct request_queue *q, + unsigned int max_batch_requests) +{ + q->limits.max_batch_reqs = max_batch_requests; +} +EXPORT_SYMBOL(blk_queue_max_batch_requests); + static int __init blk_settings_init(void) { blk_max_low_pfn = max_low_pfn - 1; diff --git a/block/kyber-iosched.c b/block/kyber-iosched.c index 8f58434..3a84a5f 100644 --- a/block/kyber-iosched.c +++ b/block/kyber-iosched.c @@ -801,50 +801,56 @@ static int kyber_dispatch_requests(struct blk_mq_hw_ctx *hctx, { struct kyber_queue_data *kqd = hctx->queue->elevator->elevator_data; struct kyber_hctx_data *khd = hctx->sched_data; + unsigned int batch_reqs = queue_max_batch_requests(hctx->queue) ? : 1; struct request *rq; - int i, ret = 0; + int i, j, ret = 0; spin_lock(&khd->lock); - /* - * First, if we are still entitled to batch, try to dispatch a request - * from the batch. - */ - if (khd->batching < kyber_batch_size[khd->cur_domain]) { - rq = kyber_dispatch_cur_domain(kqd, khd, hctx); - if (rq) { - list_add(&rq->queuelist, list); - ret = 1; - goto out; + for (j = 0; j < batch_reqs; j++) { + /* + * First, if we are still entitled to batch, try to dispatch a + * request from the batch. + */ + if (khd->batching < kyber_batch_size[khd->cur_domain]) { + rq = kyber_dispatch_cur_domain(kqd, khd, hctx); + if (rq) { + list_add(&rq->queuelist, list); + ret = 1; + continue; + } } - } - - /* - * Either, - * 1. We were no longer entitled to a batch. - * 2. The domain we were batching didn't have any requests. - * 3. The domain we were batching was out of tokens. - * - * Start another batch. Note that this wraps back around to the original - * domain if no other domains have requests or tokens. - */ - khd->batching = 0; - for (i = 0; i < KYBER_NUM_DOMAINS; i++) { - if (khd->cur_domain == KYBER_NUM_DOMAINS - 1) - khd->cur_domain = 0; - else - khd->cur_domain++; - rq = kyber_dispatch_cur_domain(kqd, khd, hctx); - if (rq) { - list_add(&rq->queuelist, list); - ret = 1; - goto out; + /* + * Either, + * 1. We were no longer entitled to a batch. + * 2. The domain we were batching didn't have any requests. + * 3. The domain we were batching was out of tokens. + * + * Start another batch. Note that this wraps back around to the + * original domain if no other domains have requests or tokens. + */ + khd->batching = 0; + for (i = 0; i < KYBER_NUM_DOMAINS; i++) { + if (khd->cur_domain == KYBER_NUM_DOMAINS - 1) + khd->cur_domain = 0; + else + khd->cur_domain++; + + rq = kyber_dispatch_cur_domain(kqd, khd, hctx); + if (rq) { + list_add(&rq->queuelist, list); + ret = 1; + break; + } } } -out: spin_unlock(&khd->lock); + + if (list_empty(list)) + ret = 0; + return ret; } diff --git a/block/mq-deadline.c b/block/mq-deadline.c index 9fbffba..4e3d58a 100644 --- a/block/mq-deadline.c +++ b/block/mq-deadline.c @@ -382,16 +382,24 @@ static int dd_dispatch_requests(struct blk_mq_hw_ctx *hctx, struct list_head *list) { struct deadline_data *dd = hctx->queue->elevator->elevator_data; + unsigned int batch_reqs = queue_max_batch_requests(hctx->queue) ? : 1; struct request *rq; + int i; - spin_lock(&dd->lock); - rq = __dd_dispatch_request(dd); - spin_unlock(&dd->lock); + for (i = 0; i < batch_reqs; i++) { + spin_lock(&dd->lock); + rq = __dd_dispatch_request(dd); + spin_unlock(&dd->lock); - if (!rq) - return 0; + if (!rq) { + if (list_empty(list)) + return 0; - list_add(&rq->queuelist, list); + return 1; + } + + list_add(&rq->queuelist, list); + } return 1; } diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 053ea4b..d7032a0 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -338,6 +338,7 @@ struct queue_limits { unsigned int max_write_zeroes_sectors; unsigned int discard_granularity; unsigned int discard_alignment; + unsigned int max_batch_reqs; unsigned short max_segments; unsigned short max_integrity_segments; @@ -1109,6 +1110,8 @@ extern void blk_queue_required_elevator_features(struct request_queue *q, unsigned int features); extern bool blk_queue_can_use_dma_map_merging(struct request_queue *q, struct device *dev); +extern void blk_queue_max_batch_requests(struct request_queue *q, + unsigned int max_batch_requests); /* * Number of physical segments as sent to the device. @@ -1291,6 +1294,11 @@ static inline unsigned int queue_max_segment_size(const struct request_queue *q) return q->limits.max_segment_size; } +static inline unsigned int queue_max_batch_requests(const struct request_queue *q) +{ + return q->limits.max_batch_reqs; +} + static inline unsigned queue_logical_block_size(const struct request_queue *q) { int retval = 512; From patchwork Mon Mar 16 10:01:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolin Wang X-Patchwork-Id: 211102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62F98C3F2CE for ; Mon, 16 Mar 2020 10:02:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 39EA62073E for ; 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Mon, 16 Mar 2020 03:01:53 -0700 (PDT) From: Baolin Wang To: axboe@kernel.dk, paolo.valente@linaro.org, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: ming.lei@redhat.com, arnd@arndb.de, linus.walleij@linaro.org, baolin.wang7@gmail.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-mmc@vger.kernel.org, linux-block@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH 4/8] mmc: host: sdhci: Introduce ADMA3 transfer mode Date: Mon, 16 Mar 2020 18:01:21 +0800 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The standard SD host controller can support ADMA3 transfer mode optionally. The ADMA3 uses command descriptor to issue an SD command, and a multi-block data transfer is programmed by using a pair of command descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using integrated descriptor. This is a preparation patch to add ADMA3 structures and help to expand the ADMA buffer for support ADMA3 transfer mode. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci.c | 106 +++++++++++++++++++++++++++++++++++++++-------- drivers/mmc/host/sdhci.h | 48 +++++++++++++++++++++ 2 files changed, 137 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 4febbcb..6238b5c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -772,7 +772,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, * If this triggers then we have a calculation bug * somewhere. :/ */ - WARN_ON((desc - host->adma_table) >= host->adma_table_sz); + WARN_ON((desc - host->adma_table) >= + host->adma_table_sz * host->adma3_table_cnt); } if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { @@ -4012,10 +4013,17 @@ int sdhci_setup_host(struct sdhci_host *host) (host->caps & SDHCI_CAN_DO_ADMA2)) host->flags |= SDHCI_USE_ADMA; + if ((host->quirks2 & SDHCI_QUIRK2_USE_ADMA3_SUPPORT) && + (host->flags & SDHCI_USE_ADMA) && + (host->caps1 & SDHCI_CAN_DO_ADMA3)) { + DBG("Enable ADMA3 mode for data transfer\n"); + host->flags |= SDHCI_USE_ADMA3; + } + if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && (host->flags & SDHCI_USE_ADMA)) { DBG("Disabling ADMA as it is marked broken\n"); - host->flags &= ~SDHCI_USE_ADMA; + host->flags &= ~(SDHCI_USE_ADMA | SDHCI_USE_ADMA3); } if (sdhci_can_64bit_dma(host)) @@ -4048,7 +4056,7 @@ int sdhci_setup_host(struct sdhci_host *host) if (ret) { pr_warn("%s: No suitable DMA available - falling back to PIO\n", mmc_hostname(mmc)); - host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); + host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_ADMA3); ret = 0; } @@ -4070,31 +4078,68 @@ int sdhci_setup_host(struct sdhci_host *host) host->desc_sz = host->alloc_desc_sz; host->adma_table_sz = host->adma_table_cnt * host->desc_sz; + host->adma3_table_cnt = 1; + + if (host->flags & SDHCI_USE_ADMA3) { + /* We can package maximum 16 requests once */ + host->adma3_table_cnt = SDHCI_MAX_ADMA3_ENTRIES; + + if (host->flags & SDHCI_USE_64_BIT_DMA) + host->integr_desc_sz = SDHCI_INTEGR_64_DESC_SZ; + else + host->integr_desc_sz = SDHCI_INTEGR_32_DESC_SZ; + + host->cmd_desc_sz = SDHCI_ADMA3_CMD_DESC_SZ; + host->cmd_table_sz = host->adma3_table_cnt * + SDHCI_ADMA3_CMD_DESC_SZ * SDHCI_ADMA3_CMD_DESC_ENTRIES; + + buf = dma_alloc_coherent(mmc_dev(mmc), + host->adma3_table_cnt * + host->integr_desc_sz, + &dma, GFP_KERNEL); + if (!buf) { + pr_warn("%s: Unable to allocate ADMA3 integrated buffers - falling back to ADMA\n", + mmc_hostname(mmc)); + host->flags &= ~SDHCI_USE_ADMA3; + host->adma3_table_cnt = 1; + } else { + host->integr_table = buf; + host->integr_addr = dma; + } + } + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; /* * Use zalloc to zero the reserved high 32-bits of 128-bit * descriptors so that they never need to be written. */ buf = dma_alloc_coherent(mmc_dev(mmc), - host->align_buffer_sz + host->adma_table_sz, + host->align_buffer_sz * + host->adma3_table_cnt + + host->cmd_table_sz + + host->adma_table_sz * + host->adma3_table_cnt, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", mmc_hostname(mmc)); - host->flags &= ~SDHCI_USE_ADMA; - } else if ((dma + host->align_buffer_sz) & + host->flags &= ~(SDHCI_USE_ADMA | SDHCI_USE_ADMA3); + } else if ((dma + host->align_buffer_sz * host->adma3_table_cnt) & (SDHCI_ADMA2_DESC_ALIGN - 1)) { pr_warn("%s: unable to allocate aligned ADMA descriptor\n", mmc_hostname(mmc)); - host->flags &= ~SDHCI_USE_ADMA; - dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + - host->adma_table_sz, buf, dma); + host->flags &= ~(SDHCI_USE_ADMA | SDHCI_USE_ADMA3); + dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz * + host->adma3_table_cnt + + host->cmd_table_sz + + host->adma_table_sz * + host->adma3_table_cnt, buf, dma); } else { host->align_buffer = buf; host->align_addr = dma; - host->adma_table = buf + host->align_buffer_sz; - host->adma_addr = dma + host->align_buffer_sz; + host->adma_table = buf + host->align_buffer_sz * host->adma3_table_cnt; + host->adma_addr = dma + host->align_buffer_sz * host->adma3_table_cnt; } } @@ -4495,12 +4540,21 @@ int sdhci_setup_host(struct sdhci_host *host) regulator_disable(mmc->supply.vqmmc); undma: if (host->align_buffer) - dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + - host->adma_table_sz, host->align_buffer, + dma_free_coherent(mmc_dev(mmc), + host->align_buffer_sz * host->adma3_table_cnt + + host->cmd_table_sz + + host->adma_table_sz * host->adma3_table_cnt, + host->align_buffer, host->align_addr); host->adma_table = NULL; host->align_buffer = NULL; + if (host->integr_table) + dma_free_coherent(mmc_dev(mmc), + host->adma3_table_cnt * host->integr_desc_sz, + host->integr_table, host->integr_addr); + host->integr_table = NULL; + return ret; } EXPORT_SYMBOL_GPL(sdhci_setup_host); @@ -4513,8 +4567,11 @@ void sdhci_cleanup_host(struct sdhci_host *host) regulator_disable(mmc->supply.vqmmc); if (host->align_buffer) - dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + - host->adma_table_sz, host->align_buffer, + dma_free_coherent(mmc_dev(mmc), + host->align_buffer_sz * host->adma3_table_cnt + + host->cmd_table_sz + + host->adma_table_sz * host->adma3_table_cnt, + host->align_buffer, host->align_addr); if (host->use_external_dma) @@ -4522,6 +4579,12 @@ void sdhci_cleanup_host(struct sdhci_host *host) host->adma_table = NULL; host->align_buffer = NULL; + + if (host->integr_table) + dma_free_coherent(mmc_dev(mmc), + host->adma3_table_cnt * host->integr_desc_sz, + host->integr_table, host->integr_addr); + host->integr_table = NULL; } EXPORT_SYMBOL_GPL(sdhci_cleanup_host); @@ -4650,8 +4713,11 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) regulator_disable(mmc->supply.vqmmc); if (host->align_buffer) - dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + - host->adma_table_sz, host->align_buffer, + dma_free_coherent(mmc_dev(mmc), + host->align_buffer_sz * host->adma3_table_cnt + + host->cmd_table_sz + + host->adma_table_sz * host->adma3_table_cnt, + host->align_buffer, host->align_addr); if (host->use_external_dma) @@ -4659,6 +4725,12 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) host->adma_table = NULL; host->align_buffer = NULL; + + if (host->integr_table) + dma_free_coherent(mmc_dev(mmc), + host->adma3_table_cnt * host->integr_desc_sz, + host->integr_table, host->integr_addr); + host->integr_table = NULL; } EXPORT_SYMBOL_GPL(sdhci_remove_host); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5507a73..96aed99 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -274,6 +274,9 @@ #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 +#define SDHCI_ADMA3_ADDRESS 0x78 +#define SDHCI_ADMA3_ADDRESS_HI 0x7c + #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE @@ -346,6 +349,41 @@ struct sdhci_adma2_64_desc { #define ADMA2_NOP_END_VALID 0x3 #define ADMA2_END 0x2 +#define SDHCI_MAX_ADMA3_ENTRIES 16 + +/* ADMA3 command descriptor */ +struct sdhci_adma3_cmd_desc { + __le32 cmd; + __le32 reg; +} __packed __aligned(4); + +#define ADMA3_TRAN_VALID 0x9 +#define ADMA3_TRAN_END 0xb + +/* ADMA3 command descriptor size */ +#define SDHCI_ADMA3_CMD_DESC_ENTRIES 4 +#define SDHCI_ADMA3_CMD_DESC_SZ 8 + +/* ADMA3 integrated 32-bit descriptor */ +struct sdhci_integr_32_desc { + __le32 cmd; + __le32 addr; +} __packed __aligned(4); + +#define SDHCI_INTEGR_32_DESC_SZ 8 + +/* ADMA3 integrated 64-bit descriptor. */ +struct sdhci_integr_64_desc { + __le32 cmd; + __le32 addr_lo; + __le32 addr_hi; +} __packed __aligned(4); + +#define SDHCI_INTEGR_64_DESC_SZ 16 + +#define ADMA3_INTEGR_TRAN_VALID 0x39 +#define ADMA3_INTEGR_TRAN_END 0x3b + /* * Maximum segments assuming a 512KiB maximum requisition size and a minimum * 4KiB page size. @@ -484,6 +522,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* use ADMA3 for data read/write if hardware supports */ +#define SDHCI_QUIRK2_USE_ADMA3_SUPPORT (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ @@ -520,6 +560,7 @@ struct sdhci_host { #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ +#define SDHCI_USE_ADMA3 (1<<17) /* Host is ADMA3 capable */ unsigned int version; /* SDHCI spec. version */ @@ -552,15 +593,20 @@ struct sdhci_host { void *adma_table; /* ADMA descriptor table */ void *align_buffer; /* Bounce buffer */ + void *integr_table; /* ADMA3 intergrate descriptor table */ size_t adma_table_sz; /* ADMA descriptor table size */ size_t align_buffer_sz; /* Bounce buffer size */ + size_t cmd_table_sz; /* ADMA3 command descriptor table size */ dma_addr_t adma_addr; /* Mapped ADMA descr. table */ dma_addr_t align_addr; /* Mapped bounce buffer */ + dma_addr_t integr_addr; /* Mapped ADMA3 intergrate descr. table */ unsigned int desc_sz; /* ADMA current descriptor size */ unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ + unsigned int cmd_desc_sz; /* ADMA3 command descriptor size */ + unsigned int integr_desc_sz; /* ADMA3 intergrate descriptor size */ struct workqueue_struct *complete_wq; /* Request completion wq */ struct work_struct complete_work; /* Request completion work */ @@ -611,6 +657,8 @@ struct sdhci_host { /* Host ADMA table count */ u32 adma_table_cnt; + /* Host ADMA3 table count */ + u32 adma3_table_cnt; u64 data_timeout; From patchwork Mon Mar 16 10:01:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolin Wang X-Patchwork-Id: 211104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6478EC18E5B for ; Mon, 16 Mar 2020 10:02:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E29820738 for ; Mon, 16 Mar 2020 10:02:02 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 16 Mar 2020 03:01:56 -0700 (PDT) From: Baolin Wang To: axboe@kernel.dk, paolo.valente@linaro.org, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: ming.lei@redhat.com, arnd@arndb.de, linus.walleij@linaro.org, baolin.wang7@gmail.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-mmc@vger.kernel.org, linux-block@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH 5/8] mmc: host: sdhci: Factor out the command configuration Date: Mon, 16 Mar 2020 18:01:22 +0800 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Move the SD command configuration into one separate function to simplify the sdhci_send_command(). Moreover this function can be used to support ADMA3 transfer mode in following patches. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci.c | 65 ++++++++++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6238b5c..4de0f48 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1546,9 +1546,43 @@ static void sdhci_finish_data(struct sdhci_host *host) } } -void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +static int sdhci_get_command(struct sdhci_host *host, struct mmc_command *cmd) { int flags; + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + pr_err("%s: Unsupported response type!\n", + mmc_hostname(host->mmc)); + cmd->error = -EINVAL; + sdhci_finish_mrq(host, cmd->mrq); + return -EINVAL; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + + /* CMD19 is special in that the Data Present Select should be set */ + if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || + cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) + flags |= SDHCI_CMD_DATA; + + return SDHCI_MAKE_CMD(cmd->opcode, flags); +} + +void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + int command; u32 mask; unsigned long timeout; @@ -1605,32 +1639,9 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) sdhci_set_transfer_mode(host, cmd); - if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { - pr_err("%s: Unsupported response type!\n", - mmc_hostname(host->mmc)); - cmd->error = -EINVAL; - sdhci_finish_mrq(host, cmd->mrq); + command = sdhci_get_command(host, cmd); + if (command < 0) return; - } - - if (!(cmd->flags & MMC_RSP_PRESENT)) - flags = SDHCI_CMD_RESP_NONE; - else if (cmd->flags & MMC_RSP_136) - flags = SDHCI_CMD_RESP_LONG; - else if (cmd->flags & MMC_RSP_BUSY) - flags = SDHCI_CMD_RESP_SHORT_BUSY; - else - flags = SDHCI_CMD_RESP_SHORT; - - if (cmd->flags & MMC_RSP_CRC) - flags |= SDHCI_CMD_CRC; - if (cmd->flags & MMC_RSP_OPCODE) - flags |= SDHCI_CMD_INDEX; - - /* CMD19 is special in that the Data Present Select should be set */ - if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || - cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) - flags |= SDHCI_CMD_DATA; timeout = jiffies; if (host->data_timeout) @@ -1644,7 +1655,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) if (host->use_external_dma) sdhci_external_dma_pre_transfer(host, cmd); - sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); + sdhci_writew(host, command, SDHCI_COMMAND); } EXPORT_SYMBOL_GPL(sdhci_send_command); From patchwork Mon Mar 16 10:01:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolin Wang X-Patchwork-Id: 211103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB8E7C3F2CE for ; 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Mon, 16 Mar 2020 03:02:08 -0700 (PDT) From: Baolin Wang To: axboe@kernel.dk, paolo.valente@linaro.org, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: ming.lei@redhat.com, arnd@arndb.de, linus.walleij@linaro.org, baolin.wang7@gmail.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-mmc@vger.kernel.org, linux-block@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH 8/8] mmc: host: sdhci-sprd: Add MMC packed request support Date: Mon, 16 Mar 2020 18:01:25 +0800 Message-Id: <060083eadc085cc93149475f3259cf2eb9d81d83.1584350380.git.baolin.wang7@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Enable the ADMA3 transfer mode as well as adding packed operations to support MMC packed requests to improve IO performance. Signed-off-by: Baolin Wang --- drivers/mmc/host/sdhci-sprd.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c index 49afe1c..daa38ed 100644 --- a/drivers/mmc/host/sdhci-sprd.c +++ b/drivers/mmc/host/sdhci-sprd.c @@ -390,6 +390,12 @@ static void sdhci_sprd_request_done(struct sdhci_host *host, mmc_request_done(host->mmc, mrq); } +static void sdhci_sprd_packed_request_done(struct sdhci_host *host, + struct mmc_packed_request *prq) +{ + mmc_hsq_finalize_packed_request(host->mmc, prq); +} + static struct sdhci_ops sdhci_sprd_ops = { .read_l = sdhci_sprd_readl, .write_l = sdhci_sprd_writel, @@ -404,6 +410,7 @@ static void sdhci_sprd_request_done(struct sdhci_host *host, .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, .get_ro = sdhci_sprd_get_ro, .request_done = sdhci_sprd_request_done, + .packed_request_done = sdhci_sprd_packed_request_done, }; static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) @@ -546,10 +553,18 @@ static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, SDHCI_QUIRK_MISSING_CAPS, .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | SDHCI_QUIRK2_USE_32BIT_BLK_CNT | - SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_USE_ADMA3_SUPPORT, .ops = &sdhci_sprd_ops, }; +static const struct hsq_packed_ops packed_ops = { + .packed_algo = mmc_hsq_packed_algo_rw, + .prepare_hardware = sdhci_prepare_packed, + .unprepare_hardware = sdhci_unprepare_packed, + .packed_request = sdhci_packed_request, +}; + static int sdhci_sprd_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -676,7 +691,18 @@ static int sdhci_sprd_probe(struct platform_device *pdev) goto err_cleanup_host; } - ret = mmc_hsq_init(hsq, host->mmc, NULL, 0); + /* + * If the host controller can support ADMA3 mode, we can enable the + * packed request mode to improve the read/write performance. + * + * Considering the maximum ADMA3 entries (default is 16) and the request + * latency, we set the default maximum packed requests number is 8. + */ + if (host->flags & SDHCI_USE_ADMA3) + ret = mmc_hsq_init(hsq, host->mmc, &packed_ops, + SDHCI_MAX_ADMA3_ENTRIES / 2); + else + ret = mmc_hsq_init(hsq, host->mmc, NULL, 0); if (ret) goto err_cleanup_host;