From patchwork Mon Apr 6 09:27:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 211045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 562A2C2BA80 for ; Mon, 6 Apr 2020 09:28:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 28C16206F5 for ; Mon, 6 Apr 2020 09:28:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SPJXejwP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726898AbgDFJ2Z (ORCPT ); Mon, 6 Apr 2020 05:28:25 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:22353 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726621AbgDFJ2X (ORCPT ); Mon, 6 Apr 2020 05:28:23 -0400 X-UUID: 1955524c2a5a4241a0b1b4b93527f277-20200406 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MWNDe8xiBMP9rQl7Ip5z2SzbYK+nzQInXthBu/WoeY4=; b=SPJXejwP86lXCRSA/h1CdJVVoQx3OSO2PCusnTh5m3ug5sVTY5ID/dOpTgrty0mo2iFYErC7jXbqZyitRPBB5RsPr/Z1qDEBNvVlKoswjDdeRUxg/g6YKap/YXDbthFYkb2ydpvYJonHtcUI+MyFpxBpag702L9cMgMPigBSbTo=; X-UUID: 1955524c2a5a4241a0b1b4b93527f277-20200406 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 724451446; Mon, 06 Apr 2020 17:28:04 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Apr 2020 17:28:03 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Apr 2020 17:28:02 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH 2/5] [2/5] mmc: host: Remove redundant host CQE bindings Date: Mon, 6 Apr 2020 17:27:58 +0800 Message-ID: <1586165281-11888-3-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586165281-11888-1-git-send-email-chun-hung.wu@mediatek.com> References: <1586165281-11888-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 3A9531E2BC7618BFEB04D1E964ADCBD4D2135A383C34C28A1E705DD966F2B10A2000:8 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org CQE bindings "supports-cqe" and "disable-cqe-dcmd" is parsed in mmc_of_parse(). Remove vendor code which parses CQE bindings, and use mmc_host->caps2 to decide support CQE or not. Signed-off-by: Chun-Hung Wu --- drivers/mmc/host/sdhci-brcmstb.c | 11 ++++++----- drivers/mmc/host/sdhci-msm.c | 3 +-- drivers/mmc/host/sdhci-of-arasan.c | 3 --- drivers/mmc/host/sdhci-tegra.c | 2 +- 4 files changed, 8 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index ad01f64..07c90c6 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -247,10 +247,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) return res; memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); - if (device_property_read_bool(&pdev->dev, "supports-cqe")) { - has_cqe = true; - match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; - } brcmstb_pdata.ops = match_priv->ops; host = sdhci_pltfm_init(pdev, &brcmstb_pdata, sizeof(struct sdhci_brcmstb_priv)); @@ -261,7 +257,6 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); priv = sdhci_pltfm_priv(pltfm_host); - priv->has_cqe = has_cqe; /* Map in the non-standard CFG registers */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); @@ -276,6 +271,12 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) if (res) goto err; + if (host->mmc->caps2 & MMC_CAP2_CQE) { + has_cqe = true; + match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; + } + priv->has_cqe = has_cqe; + /* * If the chip has enhanced strobe and it's enabled, add * callback diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index c3a160c..fbb2f57 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1880,7 +1880,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) u8 core_major; const struct sdhci_msm_offset *msm_offset; const struct sdhci_msm_variant_info *var_info; - struct device_node *node = pdev->dev.of_node; host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); if (IS_ERR(host)) @@ -2076,7 +2075,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(&pdev->dev); host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; - if (of_property_read_bool(node, "supports-cqe")) + if (host->mmc->caps2 & MMC_CAP2_CQE) ret = sdhci_msm_cqe_add_host(host, pdev); else ret = sdhci_add_host(host); diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index e49b44b..359eff6 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1281,9 +1281,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_voltage_switch; sdhci_arasan->has_cqe = true; host->mmc->caps2 |= MMC_CAP2_CQE; - - if (!of_property_read_bool(np, "disable-cqe-dcmd")) - host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; } ret = sdhci_arasan_add_host(sdhci_arasan); diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 403ac44..d09abdd 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -715,7 +715,7 @@ static void tegra_sdhci_parse_dt(struct sdhci_host *host) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); - if (device_property_read_bool(host->mmc->parent, "supports-cqe")) + if (host->mmc->caps2 & MMC_CAP2_CQE) tegra_host->enable_hwcq = true; else tegra_host->enable_hwcq = false; From patchwork Mon Apr 6 09:27:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= X-Patchwork-Id: 211044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBE9BC2BA1E for ; Mon, 6 Apr 2020 09:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9F18720644 for ; Mon, 6 Apr 2020 09:29:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Dn51w+Ct" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726701AbgDFJ3A (ORCPT ); Mon, 6 Apr 2020 05:29:00 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:51800 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726799AbgDFJ3A (ORCPT ); Mon, 6 Apr 2020 05:29:00 -0400 X-UUID: d772543e96b54573b2ed972ec2b4dd80-20200406 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=muWMIkHaWKYbNBLLo8XrACMV/YRyMZLJ8+ep+aobtGo=; b=Dn51w+Ctn/Y8eAldEDwwqJ069eZO5nsMpzhVCwjjCE2sMToIhL4vi9BBeujNsmtnIWQutmmX47JO7Dir1b/iZS6i24z0opg+CHwChYIKAQoJ790QvyjiGc77aNQPQj1nqOVi2QnS3mQMP78zLstny5T/eZlPNr6T/nVNEUvsOL0=; X-UUID: d772543e96b54573b2ed972ec2b4dd80-20200406 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1198615902; Mon, 06 Apr 2020 17:28:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Apr 2020 17:28:03 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Apr 2020 17:28:02 +0800 From: Chun-Hung Wu To: , Jonathan Hunter , Al Cooper , Adrian Hunter , Florian Fainelli , , Andy Gross , Bjorn Andersson , Michal Simek , Thierry Reding , Chaotian Jing , Ulf Hansson , Rob Herring , Mark Rutland , Matthias Brugger , Linus Walleij , Pavel Machek , Kate Stewart , Greg Kroah-Hartman , Martin Blumenstingl , Pan Bian , Thomas Gleixner , Allison Randal , Mathieu Malaterre , Stanley Chu , Kuohong Wang CC: , , , , , , , , , Chun-Hung Wu Subject: [PATCH 3/5] [3/5] mmc: mediatek: refine msdc timeout api Date: Mon, 6 Apr 2020 17:27:59 +0800 Message-ID: <1586165281-11888-4-git-send-email-chun-hung.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1586165281-11888-1-git-send-email-chun-hung.wu@mediatek.com> References: <1586165281-11888-1-git-send-email-chun-hung.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 16F3C6724004E6AA8460B143588F4E3011ADAC7C8487500B14833265BC6D0BD32000:8 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Extract msdc timeout api common part to have better code architecture and avoid redundent code. Signed-off-by: Chun-Hung Wu --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 7726dcf..a2328fb 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -699,21 +699,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -723,9 +723,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host)