From patchwork Fri Apr 24 03:55:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E128C55194 for ; Fri, 24 Apr 2020 03:56:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EEC0B206CD for ; Fri, 24 Apr 2020 03:56:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="AsokAc8o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726497AbgDXDzX (ORCPT ); Thu, 23 Apr 2020 23:55:23 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:10764 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726473AbgDXDzW (ORCPT ); Thu, 23 Apr 2020 23:55:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:53:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:21 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:21 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:21 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 23 Apr 2020 20:55:20 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Date: Thu, 23 Apr 2020 20:55:07 -0700 Message-ID: <1587700513-28449-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700404; bh=Aw2TIrfzrAVXZOn1lDfsAGIvwrb7U15QVjnSRgzRbvc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AsokAc8oTHwGnGdDwDHlGI0qfSZUcdQxWbHKrSCVhbGFdBGAu/kNQ+Z9Bq5MbrRmT mpX7XjmCKz8pWChqNy5b5D+zqeGhZtVzzXt3zc6KFXdymR8QcU425tvnehu8DqLojy UFWUa5xytTc6V9z9MI0QIdHkzVEvVUF8sqwk56MYSXZaJ7MHcUCGoBNjbQ6X8RDELR ZxtGSB6lg/TmqVStfKjiRMN6H85c9RBjJcFU914bCQ3QsmryQdUlOOAolYLr6D2S5d pdbQZPrwubWgnbAbaF+d+quLY/6HUouloD1W4Bf416R4msvoPLGIwGRO43+M+D505D ZfkC7YXZTRXCg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 uses PLLD out internally for CSI TPG. This patch adds clk id for this CSI TPG clock from PLLD. Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b..d8909e0 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,7 +351,7 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ +#define TEGRA210_CLK_CSI_TPG 320 /* 321 */ #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 From patchwork Fri Apr 24 03:55:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B23AEC5518A for ; Fri, 24 Apr 2020 03:55:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 921F82076C for ; Fri, 24 Apr 2020 03:55:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="F4UQ1v1b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726522AbgDXDzY (ORCPT ); Thu, 23 Apr 2020 23:55:24 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10171 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726364AbgDXDzX (ORCPT ); Thu, 23 Apr 2020 23:55:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:55:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:22 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:22 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:22 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 23 Apr 2020 20:55:21 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Thu, 23 Apr 2020 20:55:08 -0700 Message-ID: <1587700513-28449-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700510; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=F4UQ1v1bB3nYBGTUCsx8GYrB0gASzlutZmT3SyaKvYUGAiGxhboRhuWIVcVhoOak9 0mWFNjb2yTa166ojO9g5/n7vr8hlZpiiko/4oKOg3vO1cdKHgSUZWmBYCWMG5wln7i /8+NMNKVm2BS/1uYBO+Xce5pFfORGap2a3ScuEXFy75rpgckZJAwGZs4rX+m6Y4Ea1 2y4Iz5uCCybTGsDX/etuTyiROvbXKnA2YG9OF1V2yGp7oX6rO6GubjbydM7vedCV5f UuxB6/FZPKKCHQ7BQzMSXb5kLNMZ74lm4IWyyRmMi5SwECnjvGbboWI5+ctK5qhGmy yNm2kzVRAQxDA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, From patchwork Fri Apr 24 03:55:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1C54C55195 for ; Fri, 24 Apr 2020 03:55:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80F63216FD for ; Fri, 24 Apr 2020 03:55:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="f5EN0UcO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726654AbgDXDzr (ORCPT ); Thu, 23 Apr 2020 23:55:47 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4623 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726557AbgDXDz1 (ORCPT ); Thu, 23 Apr 2020 23:55:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:54:23 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Apr 2020 20:55:26 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:26 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:26 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 23 Apr 2020 20:55:25 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 7/9] MAINTAINERS: Add Tegra Video driver section Date: Thu, 23 Apr 2020 20:55:11 -0700 Message-ID: <1587700513-28449-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700463; bh=BMQVVr+zunu9dob90MEf4wUgkZwVcUqgaAtE7fDWMfE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=f5EN0UcOMSIv3t36rmln5EqxjNU+A+dYHTnq9aFbrgdOGRCRvio4/bezLObDmxqKR RwBezvk/V3tc7bVpG8OzZtCUJTtJEMD7w4/opJ0l6bc9F+WuRd+ciJ7m6qBDAXvJhs UIAAZhqrmtg5nkTaaKpeyu1Ub2cx2Rh5C4KeLC3q6SUoTNY9Dk/E0H95aqAWcAHMYA s1TTMswpqTBI0pMzQL8mbgRIyABLeLofC2MEOTKc1pbdhZSfNSqQWoigGwXA7y8a6t KfgBppyi1xU508L7vWDQDDZvChXC7fObirA8PRou+INTOZOFHDb/ptmkF9xUHRF/Cj fuLCbyjylknAw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add maintainers and mailing list entries to Tegra Video driver section. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 973b7db..795b201 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16644,6 +16644,16 @@ M: Laxman Dewangan S: Supported F: drivers/spi/spi-tegra* +TEGRA VIDEO DRIVER +M: Thierry Reding +M: Jonathan Hunter +M: Sowjanya Komatineni +L: linux-media@vger.kernel.org +L: linux-tegra@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +F: drivers/staging/media/tegra/ + TEGRA XUSB PADCTL DRIVER M: JC Kuo S: Supported From patchwork Fri Apr 24 03:55:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E128C55186 for ; Fri, 24 Apr 2020 03:55:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E9F0214AF for ; Fri, 24 Apr 2020 03:55:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ncMOXkoQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726592AbgDXDzc (ORCPT ); Thu, 23 Apr 2020 23:55:32 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:10180 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726565AbgDXDz2 (ORCPT ); Thu, 23 Apr 2020 23:55:28 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Apr 2020 20:55:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 23 Apr 2020 20:55:27 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 23 Apr 2020 20:55:27 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 24 Apr 2020 03:55:27 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 24 Apr 2020 03:55:27 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 23 Apr 2020 20:55:26 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v10 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Thu, 23 Apr 2020 20:55:12 -0700 Message-ID: <1587700513-28449-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587700515; bh=KEZ1lHNwQNYea9tamUq6xhOd3Wa4inGS2Z794lURij8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ncMOXkoQgz34dfn7yyo9E6OnmCDtW2lGwJxCjCL4ly93JM9W/N3dFFs7Yv/etZkDh NqcViAQRVpUot7xZ9gUjrEPOlnRC8x2bRUvjN/tD9gWgzJlzRcN9pBNLp9nnCJ8zv9 2O980BWI29IBqAxzRBvEoNZ65dJg7HgmvYKyl5l2p31O4ag8bjEdiOeRhSCfA8gzsn ob+ME80BekKLTjYDSfI+HyWcW21hsDqZUJ8dnL0cOdp4CSiUoL61wMu2CFo6dkf/Ns geWCZXIC7IIj1rhn2AxVvBDq5V2rKIozmbeCL5mLL1CttHVPDMucRDicXb0ijL2Anh 5zqho6E/SPVxA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */