From patchwork Wed Jun 17 01:41:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7358DC433E0 for ; Wed, 17 Jun 2020 01:41:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4EA7D21508 for ; Wed, 17 Jun 2020 01:41:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="KkYEVn8K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726680AbgFQBje (ORCPT ); Tue, 16 Jun 2020 21:39:34 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:13776 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726653AbgFQBjb (ORCPT ); Tue, 16 Jun 2020 21:39:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:39:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:30 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:30 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:30 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:29 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 02/18] arm64: tegra: Add missing clocks and power-domains to Tegra210 VI I2C Date: Tue, 16 Jun 2020 18:41:18 -0700 Message-ID: <1592358094-23459-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357957; bh=aZpfEHCdQO79JYgaC0ZbsOUqg2JPUB+AZNA7nau630I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=KkYEVn8Kf6GcKAVADnWt6lNIC/7yA1teAFAB6cF2S3qLTpTLS4x0lyNSPT6022CcP 0zU0jKf9rIVqHCYfb+ftFkWwgweOsCD6xMMt4ChrjNtyK7gBJsfzgzoc0trx/qopjF w/F9zmodADSjCvu1a8Bukk+M7SMTVzLj7tKpKJTCCF0fRIbt6Q/S9Av14lTuuTc3ou KJu9kgEcD8EVoQSYmBMitknwrvx4R0B1IbqQBUShgEapSn1gW5XkXeFm9nzf21haMF kh2C4pzWkNyZbjfgw+fGw1yYdHk2x3O2VpCMhs17q8HKE6OKMBWi24Chzjv+0ieZ7U PTEpX41W+JLxg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 VI I2C is in VE power domain and i2c-vi node should have power-domains property. Current Tegra210 i2c-vi device node is missing both VI I2C clocks and power-domains property. This patch adds them. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0865508..3a4ed10 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -376,6 +376,12 @@ compatible = "nvidia,tegra210-i2c-vi"; reg = <0x0 0x546c0000 0x0 0x00040000>; interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, + <&tegra_car TEGRA210_CLK_I2CSLOW>; + clock-names = "div-clk", "slow"; + resets = <&tegra_car TEGRA210_CLK_VI_I2C>; + reset-names = "i2c"; + power-domains = <&pd_venc>; status = "disabled"; }; }; From patchwork Wed Jun 17 01:41:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D12F4C433E2 for ; Wed, 17 Jun 2020 01:41:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD7E42100A for ; Wed, 17 Jun 2020 01:41:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="avFJMyVY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727021AbgFQBlW (ORCPT ); Tue, 16 Jun 2020 21:41:22 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19551 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726679AbgFQBje (ORCPT ); Tue, 16 Jun 2020 21:39:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:37:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:33 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:33 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:32 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 04/18] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume Date: Tue, 16 Jun 2020 18:41:20 -0700 Message-ID: <1592358094-23459-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357875; bh=6abRkuk51eYz02OURFdOxftlQrZtHyE/TdE1BX0E3mw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=avFJMyVYBuHGK6NEmjBP/w5n8BiEz8ZKF/4tkD8XHOS4OU1h7iFCyv8LarNHY63c5 KKn8R5vif9cX7Lce5YbJIyNH3vhSGMVv4fXUrSu5iA4Uo/4eW/RkVqcbt8HNgs4Iqs pBHLiMFWWTSk2mOtAiz9YO86V682bH9li7XcOnfLOAK6IH4GXS0PI7KcjlhE/yqm1B E0xsVOmMJV9UDl6s/I9hAdhxglxCSEy2pEu8wkpJATsCij2k1CFhhgxvBbv7DXbpGC l8/pD5mbY24yRYMUosbXi4kd2tHO0t7hXvcuzOvcTcli4OAByV+wvE1e3+sbRtk/CK LTWphNU8wp7hw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org tegra_i2c_runtime_resume does not disable prior enabled clocks properly. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3be1018..1b459ca 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -668,7 +668,7 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) ret = clk_enable(i2c_dev->slow_clk); if (ret < 0) { dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; + goto disable_fast_clk; } } @@ -676,11 +676,16 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) if (ret < 0) { dev_err(i2c_dev->dev, "Enabling div clk failed, err %d\n", ret); - clk_disable(i2c_dev->fast_clk); - return ret; + goto disable_slow_clk; } return 0; + +disable_slow_clk: + clk_disable(i2c_dev->slow_clk); +disable_fast_clk: + clk_disable(i2c_dev->fast_clk); + return ret; } static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) From patchwork Wed Jun 17 01:41:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84B42C433E1 for ; Wed, 17 Jun 2020 01:39:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BBB820DD4 for ; Wed, 17 Jun 2020 01:39:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="IRk0LbrV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726715AbgFQBjh (ORCPT ); Tue, 16 Jun 2020 21:39:37 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18379 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726698AbgFQBjf (ORCPT ); Tue, 16 Jun 2020 21:39:35 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:38:46 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:35 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:35 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:34 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 06/18] i2c: tegra: Avoid tegra_i2c_init_dma() for Tegra210 vi i2c Date: Tue, 16 Jun 2020 18:41:22 -0700 Message-ID: <1592358094-23459-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357926; bh=0OuCjrabnjZNSWZBX+Waj7ikSIdYTTfQz4eoEiBUxOY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IRk0LbrV+LKwJyjoWLfOdWptknzlWv8TvzfFU0Ejz04VertO7g1I/oOkw9aCWV2Y4 VUXCvQehTdsTuokE2A+gnlOVzxy11/Gxu61JgXEXXZJkNVSY/kOlzZ1rOCWr1IYqFs NUPtUiLulJlK4pAhlWtfnZWzt+nwY64SA68r9aqukzBqYHAxxhQq/CVc0zeyq+fKFn Zi4c5zTiU4N6ehey239ehDJ2cmFKUF6nECke9O97kYKMPUpU9m5jWIyprdpeugDfOX PsN8L797lfsf2pJTFI/1ya6L+3v64I83wNQ6msPjA+5vLsQiLvcMWN8eF4sgThOw4b bodA1ZJMXe9WQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org VI I2C is on host1x bus so APB DMA can't be used for Tegra210 VI I2C and there are no tx and rx dma channels for VI I2C. So, avoid attempt of requesting DMA channels. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index e7aad64..9a80aa6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -421,7 +421,7 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) dma_addr_t dma_phys; int err; - if (!i2c_dev->hw->has_apb_dma) + if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) return 0; if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { From patchwork Wed Jun 17 01:41:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 910BFC433E6 for ; Wed, 17 Jun 2020 01:41:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F0E32100A for ; Wed, 17 Jun 2020 01:41:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="aTIouQcg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726737AbgFQBjk (ORCPT ); Tue, 16 Jun 2020 21:39:40 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19562 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726706AbgFQBjh (ORCPT ); Tue, 16 Jun 2020 21:39:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:37:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:36 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:36 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 07/18] media: tegra-video: Fix channel format alignment Date: Tue, 16 Jun 2020 18:41:23 -0700 Message-ID: <1592358094-23459-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357878; bh=8GJbUvoTqNXQhoilqMQO06MgCPv5IgO6eahUeR7/0ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=aTIouQcgByMRJ9NhRrcFmaaSZrlobZN5zHCw29VRXBlXOMjYq/y2ueRa87weqqEwA hWOA8tV3jePCJVWbiQs+eCKJjYZowbnG/JcFUxMWulx7Fw7utXOecvGyvdU4JuDaTu LIGImlg3LVa3skUioGvfTvX0uZP/ukNZpE86gWxMvqsszOVwmA7PVFft7+6iditwhy BG3/2t59DadkaD+9lr7XnqlNNnCAqVm97G22XQLVBHtlwce/u2/jOhOuG2EgQ8g1fZ hVsV1uj3JgQ4+cqpOLXaoqsnHc5MUun0yzttVTXecyFbMXvQhr47c73bOhNQ0v2l9R JtylBGI3Jybkg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 1b5e660..d621ebc 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per From patchwork Wed Jun 17 01:41:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1727C433E1 for ; Wed, 17 Jun 2020 01:40:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF67D207C4 for ; Wed, 17 Jun 2020 01:40:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="BQqe1sEB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726926AbgFQBke (ORCPT ); Tue, 16 Jun 2020 21:40:34 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:13811 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726752AbgFQBjm (ORCPT ); Tue, 16 Jun 2020 21:39:42 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:39:28 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:41 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:40 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:40 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 11/18] media: tegra-video: Add support for external sensor capture Date: Tue, 16 Jun 2020 18:41:27 -0700 Message-ID: <1592358094-23459-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357968; bh=bHsUvS/CHxdInwyGZjqZfD/1xwOeDhsYPrqVzf9pCLY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BQqe1sEBgIVe9pNi6jwvZsnVKISVIW1oDufSZq524FZtpQk8olezQz6e6DpmcPlBV VSqLF+rfS2B0UFZBHMtQGYvZINvvvIdBVWu2fiomC2W+C9r+oNojlK7WLNUbATKDM1 c/klh4o52aUM9kuMOKy6i+MTqCKB2ni9+67vlepbyJOr23cYl+xrHJLl5zmM43vLT9 zJoUIZMUu0XBEkpnuKYDnDSSgDH2deNWZgDu5hGWpNYubln5ly0IZ4VMbMUhC6eRc3 zGC2pG3cnkhOiPxEbreQafhgq1OU8HVutp2S4xA74ZeSqpebTee9YWAUXiyfNAag+L cQOnCjE8Skyzw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds support to capture from the external sensor based on device graph in the device tree. Driver walks through the device graph to create media links between the entities and registers and unregisters video devices when the corresponding sub-devices are bound and unbound. Channel formats are enumerated based on available formats from the sensor and the corresponding matched formats from the Tegra supported video formats list. Each Tegra CSI instance can be configured as 4-lane or 2-lane based on supported lane configuration from the sensor through the device tree. Currently this driver supports V4L2 video node centric only. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/Kconfig | 1 + drivers/staging/media/tegra-video/csi.c | 128 +++++- drivers/staging/media/tegra-video/csi.h | 1 + drivers/staging/media/tegra-video/tegra210.c | 2 +- drivers/staging/media/tegra-video/vi.c | 623 +++++++++++++++++++++++++-- drivers/staging/media/tegra-video/vi.h | 23 +- 6 files changed, 726 insertions(+), 52 deletions(-) diff --git a/drivers/staging/media/tegra-video/Kconfig b/drivers/staging/media/tegra-video/Kconfig index 566da62..1f35da4 100644 --- a/drivers/staging/media/tegra-video/Kconfig +++ b/drivers/staging/media/tegra-video/Kconfig @@ -5,6 +5,7 @@ config VIDEO_TEGRA depends on VIDEO_V4L2 select MEDIA_CONTROLLER select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE help Choose this option if you have an NVIDIA Tegra SoC. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index fb667df..3959d17 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -9,10 +9,13 @@ #include #include #include +#include #include #include #include +#include + #include "csi.h" #include "video.h" @@ -285,26 +288,99 @@ static const struct v4l2_subdev_ops tegra_csi_ops = { .pad = &tegra_csi_pad_ops, }; +static int tegra_csi_channel_alloc(struct tegra_csi *csi, + struct device_node *node, + unsigned int port_num, unsigned int lanes, + unsigned int num_pads) +{ + struct tegra_csi_channel *chan; + + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + list_add_tail(&chan->list, &csi->csi_chans); + chan->csi = csi; + chan->csi_port_num = port_num; + chan->numlanes = lanes; + chan->of_node = node; + chan->numpads = num_pads; + if (num_pads & 0x2) { + chan->pads[0].flags = MEDIA_PAD_FL_SINK; + chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; + } else { + chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + } + + return 0; +} + static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) { struct device_node *node = csi->dev->of_node; unsigned int port_num; - struct tegra_csi_channel *chan; unsigned int tpg_channels = csi->soc->csi_max_channels; + int ret; /* allocate CSI channel for each CSI x2 ports */ for (port_num = 0; port_num < tpg_channels; port_num++) { - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; - - list_add_tail(&chan->list, &csi->csi_chans); - chan->csi = csi; - chan->csi_port_num = port_num; - chan->numlanes = 2; - chan->of_node = node; - chan->numpads = 1; - chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; + ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_csi_channels_alloc(struct tegra_csi *csi) +{ + struct device_node *node = csi->dev->of_node; + struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; + struct fwnode_handle *fwh; + struct device_node *channel; + struct device_node *ep; + unsigned int lanes, portno, num_pads; + int ret; + + for_each_child_of_node(node, channel) { + if (!of_node_name_eq(channel, "channel")) + continue; + + ret = of_property_read_u32(channel, "reg", &portno); + if (ret < 0) + continue; + + if (portno >= csi->soc->csi_max_channels) { + dev_err(csi->dev, "invalid port num %d\n", portno); + return -EINVAL; + } + + ep = of_graph_get_endpoint_by_regs(channel, 0, 0); + if (!ep) + continue; + + fwh = of_fwnode_handle(ep); + ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); + of_node_put(ep); + if (ret) { + dev_err(csi->dev, + "failed to parse v4l2 endpoint: %d\n", ret); + return ret; + } + + lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; + if (!lanes || ((lanes & (lanes - 1)) != 0)) { + dev_err(csi->dev, "invalid data-lanes %d\n", lanes); + return -EINVAL; + } + + num_pads = of_graph_get_endpoint_count(channel); + if (num_pads == TEGRA_CSI_PADS_NUM) { + ret = tegra_csi_channel_alloc(csi, channel, portno, + lanes, num_pads); + if (ret < 0) + return ret; + } } return 0; @@ -350,6 +426,15 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) return ret; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = v4l2_async_register_subdev(subdev); + if (ret < 0) { + dev_err(csi->dev, + "failed to register subdev: %d\n", ret); + return ret; + } + } + return 0; } @@ -389,8 +474,12 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { subdev = &chan->subdev; - if (subdev->dev) + if (subdev->dev) { + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_unregister_subdev(subdev); media_entity_cleanup(&subdev->entity); + } + list_del(&chan->list); kfree(chan); } @@ -427,13 +516,14 @@ static int tegra_csi_init(struct host1x_client *client) INIT_LIST_HEAD(&csi->csi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_csi_tpg_channels_alloc(csi); - if (ret < 0) { - dev_err(csi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto cleanup; - } + else + ret = tegra_csi_channels_alloc(csi); + if (ret < 0) { + dev_err(csi->dev, + "failed to allocate channels: %d\n", ret); + goto cleanup; } ret = tegra_csi_channels_init(csi); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 93bd2a0..78a5110 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -7,6 +7,7 @@ #define __TEGRA_CSI_H__ #include +#include #include /* diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 3492a8a..4f5080a 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -230,7 +230,7 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) tegra_channel_capture_setup(chan); /* recover CSI block */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, false); tegra_csi_error_recover(subdev); } diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 52d751f..506c263 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,12 @@ to_tegra_channel_buffer(struct vb2_v4l2_buffer *vb) return container_of(vb, struct tegra_channel_buffer, buf); } +static inline struct tegra_vi_graph_entity * +to_tegra_vi_graph_entity(struct v4l2_async_subdev *asd) +{ + return container_of(asd, struct tegra_vi_graph_entity, asd); +} + static int tegra_get_format_idx_by_code(struct tegra_vi *vi, unsigned int code, unsigned int offset) @@ -146,7 +153,7 @@ static void tegra_channel_buffer_queue(struct vb2_buffer *vb) } struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) +tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor) { struct media_pad *pad; struct v4l2_subdev *subdev; @@ -156,6 +163,24 @@ tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan) entity = pad->entity; subdev = media_entity_to_v4l2_subdev(entity); + if (sensor) { + while (1) { + if ((pad->index - 1) < 0) + break; + + pad = &entity->pads[pad->index - 1]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_entity_remote_pad(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + } + } + return subdev; } @@ -165,7 +190,15 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) int ret; /* stream CSI */ - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, !on); + ret = v4l2_subdev_call(subdev, video, s_stream, on); + if (on && ret < 0 && ret != -ENOIOCTLCMD) + return ret; + + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + subdev = tegra_channel_get_remote_subdev(chan, on); ret = v4l2_subdev_call(subdev, video, s_stream, on); if (on && ret < 0 && ret != -ENOIOCTLCMD) return ret; @@ -252,7 +285,7 @@ static int tegra_channel_g_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); return v4l2_g_parm_cap(&chan->video, subdev, a); } @@ -262,7 +295,7 @@ static int tegra_channel_s_parm(struct file *file, void *fh, struct tegra_vi_channel *chan = video_drvdata(file); struct v4l2_subdev *subdev; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); return v4l2_s_parm_cap(&chan->video, subdev, a); } @@ -284,7 +317,7 @@ static int tegra_channel_enum_framesizes(struct file *file, void *fh, fse.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); ret = v4l2_subdev_call(subdev, pad, enum_frame_size, NULL, &fse); if (ret) return ret; @@ -316,7 +349,7 @@ static int tegra_channel_enum_frameintervals(struct file *file, void *fh, fie.code = fmtinfo->code; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); ret = v4l2_subdev_call(subdev, pad, enum_frame_interval, NULL, &fie); if (ret) return ret; @@ -335,6 +368,9 @@ static int tegra_channel_enum_format(struct file *file, void *fh, unsigned int index = 0, i; unsigned long *fmts_bitmap = chan->tpg_fmts_bitmap; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + fmts_bitmap = chan->fmts_bitmap; + if (f->index >= bitmap_weight(fmts_bitmap, MAX_FORMAT_NUM)) return -EINVAL; @@ -391,8 +427,9 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, struct v4l2_subdev *subdev; struct v4l2_subdev_format fmt; struct v4l2_subdev_pad_config *pad_cfg; + int ret; - subdev = tegra_channel_get_remote_subdev(chan); + subdev = tegra_channel_get_remote_subdev(chan, true); pad_cfg = v4l2_subdev_alloc_pad_config(subdev); if (!pad_cfg) return -ENOMEM; @@ -412,7 +449,10 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fmt.which = V4L2_SUBDEV_FORMAT_TRY; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + ret = v4l2_subdev_call(subdev, pad, set_fmt, pad_cfg, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -452,8 +492,11 @@ static int tegra_channel_set_format(struct file *file, void *fh, fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; fmt.pad = 0; v4l2_fill_mbus_format(&fmt.format, pix, fmtinfo->code); - subdev = tegra_channel_get_remote_subdev(chan); - v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); + if (ret < 0) + return ret; + v4l2_fill_pix_format(pix, &fmt.format); tegra_channel_fmt_align(chan, pix, fmtinfo->bpp); @@ -463,15 +506,52 @@ static int tegra_channel_set_format(struct file *file, void *fh, return 0; } +static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) +{ + int ret, index; + const struct tegra_video_format *fmtinfo; + struct v4l2_subdev *subdev; + struct v4l2_subdev_format fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + /* + * Initialize channel format to the sub-device active format if there + * is corresponding match in the Tegra supported video formats. + */ + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret) + return ret; + + index = tegra_get_format_idx_by_code(chan->vi, fmt.format.code, 0); + fmtinfo = &chan->vi->soc->video_formats[index]; + if (!fmtinfo) + return -EINVAL; + + chan->fmtinfo = fmtinfo; + v4l2_fill_pix_format(&chan->format, &fmt.format); + chan->format.pixelformat = chan->fmtinfo->fourcc; + chan->format.bytesperline = chan->format.width * chan->fmtinfo->bpp; + chan->format.sizeimage = chan->format.bytesperline * + chan->format.height; + tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + + return 0; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { - /* currently driver supports internal TPG only */ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + if (inp->index) return -EINVAL; inp->type = V4L2_INPUT_TYPE_CAMERA; - strscpy(inp->name, "Tegra TPG", sizeof(inp->name)); + subdev = tegra_channel_get_remote_subdev(chan, true); + strscpy(inp->name, subdev->name, sizeof(inp->name)); return 0; } @@ -578,6 +658,19 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) v4l2_ctrl_handler_free(&chan->ctrl_handler); return chan->ctrl_handler.error; } +#else + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_subdev(chan, true); + ret = v4l2_ctrl_add_handler(&chan->ctrl_handler, subdev->ctrl_handler, + NULL, true); + if (ret < 0) { + dev_err(chan->vi->dev, + "failed to add subdev %s ctrl handler: %d\n", + subdev->name, ret); + v4l2_ctrl_handler_free(&chan->ctrl_handler); + return ret; + } #endif /* setup the controls */ @@ -608,6 +701,57 @@ static void vi_tpg_fmts_bitmap_init(struct tegra_vi_channel *chan) bitmap_set(chan->tpg_fmts_bitmap, index, 1); } +static void vi_fmts_bitmap_init(struct tegra_vi_channel *chan) +{ + int index, ret, match_code = 0; + struct v4l2_subdev *subdev; + struct v4l2_subdev_mbus_code_enum code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + + bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM); + + /* + * Set the bitmap bits based on all the matched formats between the + * available media bus formats of sub-device and the pre-defined Tegra + * supported video formats. + */ + subdev = tegra_channel_get_remote_subdev(chan, true); + while (1) { + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code, + NULL, &code); + if (ret < 0) + break; + + index = tegra_get_format_idx_by_code(chan->vi, code.code, 0); + while (index >= 0) { + bitmap_set(chan->fmts_bitmap, index, 1); + if (!match_code) + match_code = code.code; + /* look for other formats with same mbus code */ + index = tegra_get_format_idx_by_code(chan->vi, + code.code, + index + 1); + } + + code.index++; + } + + /* + * Set the bitmap bit corresponding to default tegra video format if + * there are no matched formats. + */ + if (!match_code) { + match_code = tegra_default_format.code; + index = tegra_get_format_idx_by_code(chan->vi, match_code, 0); + if (index >= 0) + bitmap_set(chan->fmts_bitmap, index, 1); + } + + /* initialize channel format to the sub-device active format */ + tegra_channel_set_subdev_active_fmt(chan); +} + static void tegra_channel_cleanup(struct tegra_vi_channel *chan) { v4l2_ctrl_handler_free(&chan->ctrl_handler); @@ -720,6 +864,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) goto free_v4l2_ctrl_hdl; } + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + v4l2_async_notifier_init(&chan->notifier); + return 0; free_v4l2_ctrl_hdl: @@ -733,28 +880,84 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) return ret; } -static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, + struct device_node *node) { struct tegra_vi_channel *chan; + + /* + * Do not use devm_kzalloc as memory is freed immediately + * when device instance is unbound but application might still + * be holding the device node open. Channel memory allocated + * with kzalloc is freed during video device release callback. + */ + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + + chan->vi = vi; + chan->portno = port_num; + chan->of_node = node; + list_add_tail(&chan->list, &vi->vi_chans); + + return 0; +} + +static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) +{ unsigned int port_num; unsigned int nchannels = vi->soc->vi_max_channels; + int ret; for (port_num = 0; port_num < nchannels; port_num++) { - /* - * Do not use devm_kzalloc as memory is freed immediately - * when device instance is unbound but application might still - * be holding the device node open. Channel memory allocated - * with kzalloc is freed during video device release callback. - */ - chan = kzalloc(sizeof(*chan), GFP_KERNEL); - if (!chan) - return -ENOMEM; + ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node); + if (ret < 0) + return ret; + } + + return 0; +} + +static int tegra_vi_channels_alloc(struct tegra_vi *vi) +{ + struct device_node *node = vi->dev->of_node; + struct device_node *ep = NULL; + struct device_node *ports; + struct device_node *port; + unsigned int port_num; + int ret; + + ports = of_get_child_by_name(node, "ports"); + if (!ports) + return -ENODEV; + + for_each_child_of_node(ports, port) { + if (!of_node_name_eq(port, "port")) + continue; + + ret = of_property_read_u32(port, "reg", &port_num); + if (ret < 0) + continue; + + if (port_num > vi->soc->vi_max_channels) { + of_node_put(ports); + dev_err(vi->dev, "invalid port num %d\n", port_num); + return -EINVAL; + } + + ep = of_get_child_by_name(port, "endpoint"); + if (!ep) + continue; - chan->vi = vi; - chan->portno = port_num; - list_add_tail(&chan->list, &vi->vi_chans); + of_node_put(ep); + ret = tegra_vi_channel_alloc(vi, port_num, port); + if (ret < 0) { + of_node_put(ports); + return ret; + } } + of_node_put(ports); return 0; } @@ -909,6 +1112,352 @@ static int __maybe_unused vi_runtime_suspend(struct device *dev) return 0; } +/* + * Graph Management + */ +static struct tegra_vi_graph_entity * +tegra_vi_graph_find_entity(struct tegra_vi_channel *chan, + const struct fwnode_handle *fwnode) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + if (entity->asd.match.fwnode == fwnode) + return entity; + } + + return NULL; +} + +static int tegra_vi_graph_build(struct tegra_vi_channel *chan, + struct tegra_vi_graph_entity *entity) +{ + struct tegra_vi *vi = chan->vi; + struct tegra_vi_graph_entity *ent; + struct fwnode_handle *ep = NULL; + struct v4l2_fwnode_link link; + struct media_entity *local = entity->entity; + struct media_entity *remote; + struct media_pad *local_pad; + struct media_pad *remote_pad; + u32 link_flags = MEDIA_LNK_FL_ENABLED; + int ret = 0; + + dev_dbg(vi->dev, "creating links for entity %s\n", local->name); + + while (1) { + ep = fwnode_graph_get_next_endpoint(entity->asd.match.fwnode, + ep); + if (!ep) + break; + + ret = v4l2_fwnode_parse_link(ep, &link); + if (ret < 0) { + dev_err(vi->dev, "failed to parse link for %pOF: %d\n", + to_of_node(ep), ret); + continue; + } + + if (link.local_port >= local->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.local_port, to_of_node(link.local_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + local_pad = &local->pads[link.local_port]; + /* Remote node is vi node. So use channel video entity and pad + * as remote/sink. + */ + if (link.remote_node == of_fwnode_handle(vi->dev->of_node)) { + remote = &chan->video.entity; + remote_pad = &chan->pad; + goto create_link; + } + + /* + * Skip sink ports, they will be processed from the other end + * of the link. + */ + if (local_pad->flags & MEDIA_PAD_FL_SINK) { + dev_dbg(vi->dev, "skipping sink port %pOF:%u\n", + to_of_node(link.local_node), link.local_port); + v4l2_fwnode_put_link(&link); + continue; + } + + /* find the remote entity from notifier list */ + ent = tegra_vi_graph_find_entity(chan, link.remote_node); + if (!ent) { + dev_err(vi->dev, "no entity found for %pOF\n", + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -ENODEV; + break; + } + + remote = ent->entity; + if (link.remote_port >= remote->num_pads) { + dev_err(vi->dev, "invalid port number %u on %pOF\n", + link.remote_port, + to_of_node(link.remote_node)); + v4l2_fwnode_put_link(&link); + ret = -EINVAL; + break; + } + + remote_pad = &remote->pads[link.remote_port]; + +create_link: + dev_dbg(vi->dev, "creating %s:%u -> %s:%u link\n", + local->name, local_pad->index, + remote->name, remote_pad->index); + + ret = media_create_pad_link(local, local_pad->index, + remote, remote_pad->index, + link_flags); + v4l2_fwnode_put_link(&link); + if (ret < 0) { + dev_err(vi->dev, + "failed to create %s:%u -> %s:%u link: %d\n", + local->name, local_pad->index, + remote->name, remote_pad->index, ret); + break; + } + } + + fwnode_handle_put(ep); + return ret; +} + +static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct tegra_vi_graph_entity *entity; + struct v4l2_async_subdev *asd; + struct v4l2_subdev *subdev; + struct tegra_vi_channel *chan; + struct tegra_vi *vi; + int ret; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + dev_dbg(vi->dev, "notify complete, all subdevs registered\n"); + + ret = video_register_device(&chan->video, VFL_TYPE_VIDEO, -1); + if (ret < 0) { + dev_err(vi->dev, + "failed to register video device: %d\n", ret); + goto unregister_video; + } + + /* create links between the entities */ + list_for_each_entry(asd, &chan->notifier.asd_list, asd_list) { + entity = to_tegra_vi_graph_entity(asd); + ret = tegra_vi_graph_build(chan, entity); + if (ret < 0) + goto unregister_video; + } + + ret = tegra_channel_setup_ctrl_handler(chan); + if (ret < 0) { + dev_err(vi->dev, + "failed to setup channel controls: %d\n", ret); + goto unregister_video; + } + + vi_fmts_bitmap_init(chan); + subdev = tegra_channel_get_remote_subdev(chan, false); + v4l2_set_subdev_hostdata(subdev, chan); + + return 0; + +unregister_video: + video_unregister_device(&chan->video); + return ret; +} + +static int tegra_vi_graph_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + /* + * Locate the entity corresponding to the bound subdev and store the + * subdev pointer. + */ + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (!entity) { + dev_err(vi->dev, "no entity for subdev %s\n", subdev->name); + return -EINVAL; + } + + if (entity->subdev) { + dev_err(vi->dev, "duplicate subdev for node %pOF\n", + to_of_node(entity->asd.match.fwnode)); + return -EINVAL; + } + + dev_dbg(vi->dev, "subdev %s bound\n", subdev->name); + entity->entity = &subdev->entity; + entity->subdev = subdev; + + return 0; +} + +static void tegra_vi_graph_notify_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct tegra_vi_graph_entity *entity; + struct tegra_vi *vi; + struct tegra_vi_channel *chan; + + chan = container_of(notifier, struct tegra_vi_channel, notifier); + vi = chan->vi; + + video_unregister_device(&chan->video); + + media_entity_remove_links(&chan->video.entity); + entity = tegra_vi_graph_find_entity(chan, subdev->fwnode); + if (entity) { + if (entity->entity) + media_entity_remove_links(entity->entity); + entity->entity = NULL; + entity->subdev = NULL; + } + + dev_dbg(vi->dev, "subdev %s unbind\n", subdev->name); +} + +static const struct v4l2_async_notifier_operations tegra_vi_async_ops = { + .bound = tegra_vi_graph_notify_bound, + .complete = tegra_vi_graph_notify_complete, + .unbind = tegra_vi_graph_notify_unbind, +}; + +static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, + struct fwnode_handle *fwnode) +{ + struct tegra_vi *vi = chan->vi; + struct fwnode_handle *ep = NULL; + struct fwnode_handle *remote = NULL; + struct v4l2_async_subdev *asd; + struct device_node *node = NULL; + int ret; + + dev_dbg(vi->dev, "parsing node %pOF\n", to_of_node(fwnode)); + + /* parse all the remote entities and put them into the list */ + for_each_endpoint_of_node(to_of_node(fwnode), node) { + ep = of_fwnode_handle(node); + remote = fwnode_graph_get_remote_port_parent(ep); + if (!remote) { + dev_err(vi->dev, + "remote device at %pOF not found\n", node); + ret = -EINVAL; + goto cleanup; + } + + /* skip entities that are already processed */ + if (remote == dev_fwnode(vi->dev) || + tegra_vi_graph_find_entity(chan, remote)) { + fwnode_handle_put(remote); + continue; + } + + asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, + remote, sizeof(struct tegra_vi_graph_entity)); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + dev_err(vi->dev, + "failed to add subdev to notifier: %d\n", ret); + fwnode_handle_put(remote); + goto cleanup; + } + + ret = tegra_vi_graph_parse_one(chan, remote); + if (ret < 0) { + fwnode_handle_put(remote); + goto cleanup; + } + + fwnode_handle_put(remote); + } + + return 0; + +cleanup: + dev_err(vi->dev, "failed parsing the graph: %d\n", ret); + v4l2_async_notifier_cleanup(&chan->notifier); + of_node_put(node); + return ret; +} + +static int tegra_vi_graph_init(struct tegra_vi *vi) +{ + struct tegra_video_device *vid = dev_get_drvdata(vi->client.host); + struct tegra_vi_channel *chan; + struct fwnode_handle *fwnode = dev_fwnode(vi->dev); + int ret; + struct fwnode_handle *remote = NULL; + + /* + * Walk the links to parse the full graph. Each channel will have + * one endpoint of the composite node. Start by parsing the + * composite node and parse the remote entities in turn. + * Each channel will register v4l2 async notifier to make the graph + * independent between the channels so we can the current channel + * in case of something wrong during graph parsing and continue with + * next channels. + */ + list_for_each_entry(chan, &vi->vi_chans, list) { + remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0); + if (!remote) + continue; + + ret = tegra_vi_graph_parse_one(chan, remote); + fwnode_handle_put(remote); + if (ret < 0 || list_empty(&chan->notifier.asd_list)) + continue; + + chan->notifier.ops = &tegra_vi_async_ops; + ret = v4l2_async_notifier_register(&vid->v4l2_dev, + &chan->notifier); + if (ret < 0) { + dev_err(vi->dev, + "failed to register channel %d notifier: %d\n", + chan->portno, ret); + v4l2_async_notifier_cleanup(&chan->notifier); + } + } + + return 0; +} + +static void tegra_vi_graph_cleanup(struct tegra_vi *vi) +{ + struct tegra_vi_channel *chan; + + list_for_each_entry(chan, &vi->vi_chans, list) { + video_unregister_device(&chan->video); + mutex_lock(&chan->video_lock); + vb2_queue_release(&chan->queue); + mutex_unlock(&chan->video_lock); + v4l2_async_notifier_unregister(&chan->notifier); + v4l2_async_notifier_cleanup(&chan->notifier); + } +} + static int tegra_vi_init(struct host1x_client *client) { struct tegra_video_device *vid = dev_get_drvdata(client->host); @@ -922,13 +1471,14 @@ static int tegra_vi_init(struct host1x_client *client) INIT_LIST_HEAD(&vi->vi_chans); - if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) ret = tegra_vi_tpg_channels_alloc(vi); - if (ret < 0) { - dev_err(vi->dev, - "failed to allocate tpg channels: %d\n", ret); - goto free_chans; - } + else + ret = tegra_vi_channels_alloc(vi); + if (ret < 0) { + dev_err(vi->dev, + "failed to allocate vi channels: %d\n", ret); + goto free_chans; } ret = tegra_vi_channels_init(vi); @@ -937,6 +1487,12 @@ static int tegra_vi_init(struct host1x_client *client) vid->vi = vi; + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { + ret = tegra_vi_graph_init(vi); + if (ret < 0) + goto free_chans; + } + return 0; free_chans: @@ -950,6 +1506,8 @@ static int tegra_vi_init(struct host1x_client *client) static int tegra_vi_exit(struct host1x_client *client) { + struct tegra_vi *vi = host1x_client_to_vi(client); + /* * Do not cleanup the channels here as application might still be * holding video device nodes. Channels cleanup will happen during @@ -957,6 +1515,9 @@ static int tegra_vi_exit(struct host1x_client *client) * device nodes are released. */ + if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + tegra_vi_graph_cleanup(vi); + return 0; } diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index 6272c9a..98f6d575 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,19 @@ struct tegra_vi { }; /** + * struct tegra_vi_graph_entity - Entity in the video graph + * + * @asd: subdev asynchronous registration information + * @entity: media entity from the corresponding V4L2 subdev + * @subdev: V4L2 subdev + */ +struct tegra_vi_graph_entity { + struct v4l2_async_subdev asd; + struct media_entity *entity; + struct v4l2_subdev *subdev; +}; + +/** * struct tegra_vi_channel - Tegra video channel * * @list: list head for this entry @@ -138,10 +152,13 @@ struct tegra_vi { * @done_lock: protects the capture done queue list * * @portno: VI channel port number + * @of_node: device node of VI channel * * @ctrl_handler: V4L2 control handler of this video channel + * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats * @tpg_fmts_bitmap: a bitmap for supported TPG formats * @pg_mode: test pattern generator mode (disabled/direct/patch) + * @notifier: V4L2 asynchronous subdevs notifier */ struct tegra_vi_channel { struct list_head list; @@ -174,10 +191,14 @@ struct tegra_vi_channel { spinlock_t done_lock; unsigned char portno; + struct device_node *of_node; struct v4l2_ctrl_handler ctrl_handler; + DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); enum tegra_vi_pg_mode pg_mode; + + struct v4l2_async_notifier notifier; }; /** @@ -249,7 +270,7 @@ extern const struct tegra_vi_soc tegra210_vi_soc; #endif struct v4l2_subdev * -tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan); +tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor); int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); void tegra_channel_release_buffers(struct tegra_vi_channel *chan, enum vb2_buffer_state state); From patchwork Wed Jun 17 01:41:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2399DC433E3 for ; Wed, 17 Jun 2020 01:40:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F33C4207C4 for ; Wed, 17 Jun 2020 01:40:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Tg3lahZY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726891AbgFQBkY (ORCPT ); Tue, 16 Jun 2020 21:40:24 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:13817 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726771AbgFQBjo (ORCPT ); Tue, 16 Jun 2020 21:39:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:39:30 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:43 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:43 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:43 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:42 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 13/18] gpu: host1x: mipi: Update tegra_mipi_request() to be node based Date: Tue, 16 Jun 2020 18:41:29 -0700 Message-ID: <1592358094-23459-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357970; bh=kCDex2voNG6qTIY1Ta7QIgB/EQkB6udXUuVzRgnTSpc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Tg3lahZYzRoKd0bxhIGM95MH01LHqDAi27S8bJiL7oNdd/leRgRcAhPUzRKh58Xvl q4knR2P+o1ywQiDW+t66BxkwsPXhqta0TlJndatEq2eqGivOWgMEazUV4OHYfNYi+v Z+zmzXwZilHKHSCRKgse1cVzqzM1DJv9mS4UX06vfdhpT2DdfS5SlGYHWcviUNEZ+S NSxV04MdVruSOkss+609AHej7Dp2U90c6OXXE0HJcDPnXyHNznDzTvURpjh97p6P5M hN1yhhlD0huSnzKm8xlcWo3bTFc43W9A54Zg9st+2x1F5TZLywm1bDs1VEH72FZ3B0 pjIMg54c7yByA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra CSI driver need a separate MIPI device for each channel as calibration of corresponding MIPI pads for each channel should happen independently. So, this patch updates tegra_mipi_request() API to add a device_node pointer argument to allow creating mipi device for specific device node rather than a device. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/drm/tegra/dsi.c | 2 +- drivers/gpu/host1x/mipi.c | 7 +++++-- include/linux/host1x.h | 3 ++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 38beab9..0443589 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -1618,7 +1618,7 @@ static int tegra_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->regs)) return PTR_ERR(dsi->regs); - dsi->mipi = tegra_mipi_request(&pdev->dev); + dsi->mipi = tegra_mipi_request(&pdev->dev, NULL); if (IS_ERR(dsi->mipi)) return PTR_ERR(dsi->mipi); diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index e00809d..93b354b 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -206,13 +206,16 @@ static int tegra_mipi_power_down(struct tegra_mipi *mipi) return 0; } -struct tegra_mipi_device *tegra_mipi_request(struct device *device) +struct tegra_mipi_device *tegra_mipi_request(struct device *device, + struct device_node *np) { - struct device_node *np = device->of_node; struct tegra_mipi_device *dev; struct of_phandle_args args; int err; + if (!np) + np = device->of_node; + err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate", "#nvidia,mipi-calibrate-cells", 0, &args); diff --git a/include/linux/host1x.h b/include/linux/host1x.h index c230b4e..61dc577 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -325,7 +325,8 @@ int host1x_client_resume(struct host1x_client *client); struct tegra_mipi_device; -struct tegra_mipi_device *tegra_mipi_request(struct device *device); +struct tegra_mipi_device *tegra_mipi_request(struct device *device, + struct device_node *np); void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); From patchwork Wed Jun 17 01:41:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AD14C433DF for ; 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by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:45 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:44 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:43 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 14/18] gpu: host1x: mipi: Split tegra_mipi_calibrate and tegra_mipi_wait Date: Tue, 16 Jun 2020 18:41:30 -0700 Message-ID: <1592358094-23459-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357886; bh=O5AZ1YsJyVgIvzzx4UikQW0HGSpF8jhWcrl9iX7G1sw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EphXYlUesGN2f54pb5yFegg+T9OllayVCcfPcs+x0iosgUxgLUw5ssotw4EvOD7mJ 4O0ylnb7tDe5aKBxSBwrL7WeET3wNQLQp2m3Y5EnFhUsEl8TapJVNd7Gh/MZKbnF7T Vo21X0IFvcrqbn2kESBkTwfg9sK+4AjkAhZV1JLHI+yuz6K5FI5caZSxP/+aen1LMx jar6UX32EME8otgaGMiiOKn8onleNT4cp6EapRD3MIYvK22/Nh/buUfy44AuAlhsNM 7Z1ZOOzuuI0dBUZT5qYWlFgDrONMn4Eet5lh0Zw7rsexgfKfDz8toHXXfYvI+jodnr jDan0Cpr4pawg== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org SW can trigger MIPI pads calibration any time after power on but calibration results will be latched and applied to the pads by MIPI CAL unit only when the link is in LP-11 state and then status register will be updated. For CSI, trigger of pads calibration happen during CSI stream enable where CSI receiver is kept ready prior to sensor or CSI transmitter stream start. So, pads may not be in LP-11 at this time and waiting for the calibration to be done immediate after calibration start will result in timeout. This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() so triggering for calibration and waiting for it to complete can happen at different stages. Signed-off-by: Sowjanya Komatineni --- drivers/gpu/drm/tegra/dsi.c | 7 ++++++- drivers/gpu/host1x/mipi.c | 23 +++++++++++++++++------ include/linux/host1x.h | 1 + 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 0443589..93e9d85 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -670,6 +670,7 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { u32 value; + int ret; /* * XXX Is this still needed? The module reset is deasserted right @@ -693,7 +694,11 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - return tegra_mipi_calibrate(dsi->mipi); + ret = tegra_mipi_calibrate(dsi->mipi); + if (ret < 0) + return ret; + + return tegra_mipi_wait(dsi->mipi); } static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index 93b354b..99ea36f 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -296,22 +296,35 @@ int tegra_mipi_disable(struct tegra_mipi_device *dev) } EXPORT_SYMBOL(tegra_mipi_disable); -static int tegra_mipi_wait(struct tegra_mipi *mipi) +int tegra_mipi_wait(struct tegra_mipi_device *device) { + struct tegra_mipi *mipi = device->mipi; unsigned long timeout = jiffies + msecs_to_jiffies(250); u32 value; + int err; + + err = clk_enable(device->mipi->clk); + if (err < 0) + return err; + + mutex_lock(&device->mipi->lock); while (time_before(jiffies, timeout)) { value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && (value & MIPI_CAL_STATUS_DONE) != 0) - return 0; + goto done; usleep_range(10, 50); } - return -ETIMEDOUT; + err = -ETIMEDOUT; +done: + mutex_unlock(&device->mipi->lock); + clk_disable(device->mipi->clk); + return err; } +EXPORT_SYMBOL(tegra_mipi_wait); int tegra_mipi_calibrate(struct tegra_mipi_device *device) { @@ -377,12 +390,10 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) value |= MIPI_CAL_CTRL_START; tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); - err = tegra_mipi_wait(device->mipi); - mutex_unlock(&device->mipi->lock); clk_disable(device->mipi->clk); - return err; + return 0; } EXPORT_SYMBOL(tegra_mipi_calibrate); diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 61dc577..cf45ec2 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -331,5 +331,6 @@ void tegra_mipi_free(struct tegra_mipi_device *device); int tegra_mipi_enable(struct tegra_mipi_device *device); int tegra_mipi_disable(struct tegra_mipi_device *device); int tegra_mipi_calibrate(struct tegra_mipi_device *device); +int tegra_mipi_wait(struct tegra_mipi_device *device); #endif From patchwork Wed Jun 17 01:41:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79DABC433DF for ; Wed, 17 Jun 2020 01:40:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50D3220679 for ; Wed, 17 Jun 2020 01:40:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="c3FI6qgC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726795AbgFQBkQ (ORCPT ); Tue, 16 Jun 2020 21:40:16 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18417 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726782AbgFQBjq (ORCPT ); Tue, 16 Jun 2020 21:39:46 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Jun 2020 18:38:56 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 16 Jun 2020 18:39:45 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 16 Jun 2020 18:39:45 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:45 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 15/18] media: tegra-video: Add CSI MIPI pads calibration Date: Tue, 16 Jun 2020 18:41:31 -0700 Message-ID: <1592358094-23459-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357936; bh=pFN8DnnC9/K7LVPWiAD9FZmHigPVX/3jS0nLw4/yVns=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=c3FI6qgCXORvgx7GZyrxobpmBBU8cF2NU5nB7BZMzehgD5o5wrqvMCdbTfaB0j60V qqxsljIn9SYMDRen5xKuTN5D/m2JEEgxqwt4tmJzue+JoinYdibXyfOPyiNdpfrwR4 IBOq22PzN51wpIo03qR3DYLV+2urfaCeWqAQtB31uiUQ+V2zdVj1SlJxj8Cx0t/yv0 vomZ6/GHFN4lCdebbyJmNZUmHPjFBtQyQwtb0dyqmWu5U3Z9C2+RwrEDEJF5uW9iy/ pe7C0yhpKTgq9SBCq87j+puf85IZ5r6em7Km53TqDoNC8iStuehBJoVjXYsaTOjPpA Q7FrkMV4ov81g== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org CSI MIPI pads need to be enabled and calibrated for capturing from the external sensor or transmitter. MIPI CAL unit calibrates MIPI pads pull-up, pull-down and termination impedances. Calibration is done by co-work of MIPI BIAS pad and MIPI CAL control unit. Triggering calibration start can happen any time after MIPI pads are enabled but calibration results will be latched and applied to MIPI pads by MIPI CAL unit only when the link is in LP11 state and then calibration status register gets updated. This patch enables CSI MIPI pads and calibrates them during streaming. Tegra CSI receiver is able to catch the very first clock transition. So, CSI receiver is always enabled prior to sensor streaming and trigger of calibration start is done during CSI subdev streaming and status of calibration is verified after sensor stream on. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/csi.c | 44 +++++++++++++++++++++++++++++++-- drivers/staging/media/tegra-video/csi.h | 2 ++ drivers/staging/media/tegra-video/vi.c | 18 ++++++++++++++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 3959d17..f598b76 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -252,15 +252,42 @@ static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) return ret; } + if (csi_chan->mipi) { + ret = tegra_mipi_enable(csi_chan->mipi); + if (ret < 0) { + dev_err(csi->dev, + "failed to enable MIPI pads: %d\n", + ret); + goto rpm_put; + } + + /* + * CSI MIPI pads PULLUP, PULLDN and TERM impedances + * need to be calibrated after power on. + * So, trigger the calibration start here and results + * will be latched and applied to the pads when link is + * in LP11 state during start of sensor streaming. + */ + tegra_mipi_calibrate(csi_chan->mipi); + } + ret = csi->ops->csi_start_streaming(csi_chan); if (ret < 0) - goto rpm_put; + goto disable_mipi; return 0; } csi->ops->csi_stop_streaming(csi_chan); +disable_mipi: + if (csi_chan->mipi) { + ret = tegra_mipi_disable(csi_chan->mipi); + if (ret < 0) + dev_err(csi->dev, + "failed to disable MIPI pads: %d\n", ret); + } + rpm_put: pm_runtime_put(csi->dev); return ret; @@ -294,6 +321,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; + int ret = 0; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -312,7 +340,16 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; } - return 0; + if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) + return 0; + + chan->mipi = tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret = PTR_ERR(chan->mipi); + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } + + return ret; } static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) @@ -473,6 +510,9 @@ static void tegra_csi_channels_cleanup(struct tegra_csi *csi) struct tegra_csi_channel *chan, *tmp; list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { + if (chan->mipi) + tegra_mipi_free(chan->mipi); + subdev = &chan->subdev; if (subdev->dev) { if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 78a5110..0d50fc3 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -50,6 +50,7 @@ struct tegra_csi; * @framerate: active framerate for TPG * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format + * @mipi: mipi device for corresponding csi channel pads */ struct tegra_csi_channel { struct list_head list; @@ -65,6 +66,7 @@ struct tegra_csi_channel { unsigned int framerate; unsigned int h_blank; unsigned int v_blank; + struct tegra_mipi_device *mipi; }; /** diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index f9eb96b..8dc23f3 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -187,6 +187,7 @@ tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan, bool sensor) int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) { struct v4l2_subdev *subdev; + struct tegra_csi_channel *csi_chan; int ret; /* stream CSI */ @@ -198,11 +199,28 @@ int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on) if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) return 0; + if (on) + csi_chan = v4l2_get_subdevdata(subdev); + subdev = tegra_channel_get_remote_subdev(chan, on); ret = v4l2_subdev_call(subdev, video, s_stream, on); if (on && ret < 0 && ret != -ENOIOCTLCMD) return ret; + /* + * CSI subdev stream on triggers start of MIPI pads calibration. + * Calibration results are latched and applied to the pads when + * link is in LP11 state which will hapen during sensor streaming. + * So, wait for calibration to complete here. + */ + if (on && csi_chan->mipi) { + ret = tegra_mipi_wait(csi_chan->mipi); + if (ret < 0) + dev_err(csi_chan->csi->dev, + "MIPI calibration failed: %d\n", ret); + return ret; + } + return 0; } From patchwork Wed Jun 17 01:41:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 209398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B30CDC433DF for ; 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by hqpgpgate101.nvidia.com on Tue, 16 Jun 2020 18:39:49 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 17 Jun 2020 01:39:49 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 17 Jun 2020 01:39:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.186]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Jun 2020 18:39:48 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v2 18/18] arm64: tegra: Enable Tegra VI CSI support for Jetson Nano Date: Tue, 16 Jun 2020 18:41:34 -0700 Message-ID: <1592358094-23459-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> References: <1592358094-23459-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592357976; bh=SY37x9I8FIxsGnkaaa43HhEyCfrzG7BzBuiyswO6da0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iiRx+dfGO6SuQLvAj9gL6WEGTY3c8ViPNzvI/HV7ane5+rZct4mdlT+LszFnxnlSp vfDpNGFyhlcEMFGxAwGZXHPeOuOHxZkXeiErCSOZfNC6ZDhycAgO0XRZ1Zk+r2eAVy OgGfXxl2NlsiYccNZ2yYuecvmgDg0j4D6eRDb7v2YuC7qyZ5eRM8b+2Sb+qhkfiNQI 9sncl/e5SWhS5MGjO0LLwB4fdxxF+uBzpbVqt0ZR8ljnSm8g4qAj+7A0TB/7lTh74+ RxSlpQBuqbkIQ+yjnvZbc9ouwrcu7sEzWwOGP+esF8hitq6Wt7dMlf1KQvGsUYQt+u FnTOW15dMcD3Q== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch enables VI and CSI in device tree for Jetson Nano. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9bc52fd..eab5c5e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -64,6 +64,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_sys_1v2>; + + csi@838 { + status = "okay"; + }; + }; + sor@54540000 { status = "okay";