From patchwork Thu Aug 31 12:03:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111377 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp2441018qge; Thu, 31 Aug 2017 05:04:57 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7P5E7URB3T907eb7Ab7yhTazEmAUqAcAgVkjGif4zZJy1ICQoMNFY/Lco6iJNjnvM9SgYw X-Received: by 10.99.122.82 with SMTP id j18mr2099259pgn.356.1504181097296; Thu, 31 Aug 2017 05:04:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504181097; cv=none; d=google.com; s=arc-20160816; b=Ko25Gck5nDadSTUEp7uWBfM7vuRL2t+DqwhSmns40XaitGMh5QSxmJSI+gufula/vo Ix76X/ikggb4bxRzVwEY/81Gi9E1lw8aKvtiqZVmfQteQLwCIleqZj4d8abtBv0/jid0 IebKuhRxMFpphRZDMrfCBS74UYulNHINzPh6dGUOnJts7qR2E6mylvTC7inIrt6fcMLB 4M7oilnJ5qTIKifFH92AH+fK/K/bXQZ6ECVKwEYcW/FPuIMuGHm7ENlv45AsOWncEcX1 ZhTJNS++7NQ/glPCStBbQLuCpGNo0pX/pUAHUvvdWoc01trpT9GnEft9glzXg1UowPn9 IzZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=1HINortDRNfI+aJ5qTzgnZD1om4IoZs1mY63LpotqsU=; b=AUXCg1CLuv5a7e7UHozML9J2z6e0HnchK5ZTSorPw0/2jBX6axL0VBLvZPjW1NF2a6 G9SK0wZoHP7x4oEI1Xb5PsglgF5G3ZFyKMwcKmh3f2Y+fJKCtPSX5gju5ijdvUprpdWj Ct37MiYDrP5jxtoBR8/RP7VuAP1A9xuCh4SRpuUEnTIqwxj8ZuEnVUbc86eSt2M9cBOh U3v23B+Iv6nwIz6132WoLPg+/Ky2wXr9QSALn5o5DVJZvC9LQv/80nsuwlx1isHJ75qI 0sBxm7TjNtuNGx9waxmWiUMEbTnySpo0TFRyZGeSQtJVIksxYnIiU58iM+gFNqZGr5bR df6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=YzFlQdKd; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 44si6726825plc.373.2017.08.31.05.04.56; Thu, 31 Aug 2017 05:04:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=YzFlQdKd; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751419AbdHaME4 (ORCPT + 6 others); Thu, 31 Aug 2017 08:04:56 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:27001 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751237AbdHaMEz (ORCPT ); Thu, 31 Aug 2017 08:04:55 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-08.nifty.com with ESMTP id v7VC3laX025207; Thu, 31 Aug 2017 21:03:47 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com v7VC3laX025207 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1504181028; bh=L89fBidJxsSTs+T235tioaFjmtkYcQ68C/NuTSDYiMg=; h=From:To:Cc:Subject:Date:From; b=YzFlQdKdlulaIlCV9b5dIosC/Of6t5Ftwu1MKaJEXjUoqB9jC7uYEfELE6zhQFcDM 1bi73j3uQob6p2GRTUkMiShKpw/wRjqw4Ny1r2vg/NI5eEMUqKU7qKSnOAf6gvDmCv EfKpM/YCLh5Zpmr3I532RMhAgMPB00YC9RW+PzXDVrmKM1kp5O3nrxpqGSXBV71Rs2 9+Y990VQ8Z3Z5HFXVLUZnBN73UFxXny2hFUtumhIK/ulv7FF/2SShxKsEX1WkJ7ois gUgYkM841wYNvC2G3HuXhh9mbDHqqy4pTcanFyDhfvtQpYadz/ep51v0Ald0cxxX9g xBviCarg0IcYg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-clk@vger.kernel.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH] clk: uniphier: add PXs3 clock data Date: Thu, 31 Aug 2017 21:03:36 +0900 Message-Id: <1504181016-16457-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada --- I confirmed this patch can be cleanly applied on clk-next branch (commit 69a6beab085264) .../devicetree/bindings/clock/uniphier-clock.txt | 3 +++ drivers/clk/uniphier/clk-uniphier-core.c | 12 +++++++++ drivers/clk/uniphier/clk-uniphier-sys.c | 30 ++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 1 + 4 files changed, 46 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt index 2aec32d..7b5f602 100644 --- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt +++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt @@ -13,6 +13,7 @@ Required properties: "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-clock" - for LD11 SoC. "socionext,uniphier-ld20-clock" - for LD20 SoC. + "socionext,uniphier-pxs3-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: @@ -54,6 +55,7 @@ Required properties: "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-mio-clock" - for LD11 SoC. "socionext,uniphier-ld20-sd-clock" - for LD20 SoC. + "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: @@ -97,6 +99,7 @@ Required properties: "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC. "socionext,uniphier-ld11-peri-clock" - for LD11 SoC. "socionext,uniphier-ld20-peri-clock" - for LD20 SoC. + "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC - #clock-cells: should be 1. Example: diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index cb6ae26..e09f3dd46 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -138,6 +138,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-clock", .data = uniphier_ld20_sys_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-clock", + .data = uniphier_pxs3_sys_clk_data, + }, /* Media I/O clock, SD clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", @@ -167,6 +171,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-sd-clock", .data = uniphier_pro5_sd_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-sd-clock", + .data = uniphier_pro5_sd_clk_data, + }, /* Peripheral clock */ { .compatible = "socionext,uniphier-ld4-peri-clock", @@ -196,6 +204,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-peri-clock", .data = uniphier_pro4_peri_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-peri-clock", + .data = uniphier_pro4_peri_clk_data, + }, { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 6fcf781..7e77b09 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -195,3 +195,33 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { "spll/4", "spll/8", "s2pll/4", "s2pll/8"), { /* sentinel */ } }; + +const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { + UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */ + UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */ + UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */ + UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), + UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), + UNIPHIER_LD20_SYS_CLK_SD, + UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_LD11_SYS_CLK_EMMC(4), + UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x2104, 4), /* =GIO0 */ + UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x2104, 5), /* =GIO1 */ + UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x2104, 6), /* =GIO1-1 */ + UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16), + UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18), + UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20), + UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17), + UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19), + /* CPU gears */ + UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), + UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), + UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8), + UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8, + "cpll/2", "spll/2", "cpll/3", "spll/3", + "spll/4", "spll/8", "cpll/4", "cpll/8"), + UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8, + "s2pll/2", "spll/2", "s2pll/3", "spll/3", + "spll/4", "spll/8", "s2pll/4", "s2pll/8"), + { /* sentinel */ } +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 8271640..d10a009 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -154,6 +154,7 @@ extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; +extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[]; extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[]; extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];