From patchwork Thu Jan 30 20:45:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 208238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7527AC2D0DB for ; Thu, 30 Jan 2020 20:45:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 548B520674 for ; Thu, 30 Jan 2020 20:45:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727240AbgA3Upa (ORCPT ); Thu, 30 Jan 2020 15:45:30 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35081 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727235AbgA3UpY (ORCPT ); Thu, 30 Jan 2020 15:45:24 -0500 Received: by mail-wr1-f65.google.com with SMTP id g17so5876781wro.2; Thu, 30 Jan 2020 12:45:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=c3k6VjpBHrIjrTaQQqSSGNBzkMebYDOeyw44+9Ugl28=; b=BZbL7AZmPKc+N/zSWqpQwIg9PS5WhatQpMDFlKj9pbvh1MPpjOzOeI35auwFWimMqh km4io1AwxZ0BGwZ/sZx8gu71qjj5Igb22xaJssDy84Md3aEEvrtYvFwAigu/HxlMKRIK TeTXehQbW9+Q6atDHlk9F8j4lPLd4eu/yECKzOH2VGtcDnuh0lheQCUUQf1saD6y6Q8b esaHUs7CkrnsPownPc9EcXKcVZ3UhyqpXZnJdQc9yM2oD7BrwZfUXHOsJ8paXMXsz3xT wwx/FJlcFJWRoWlDS8y4mLzbAMLr+eJy7Q6aaxmFFXdMX0PBSa5OiDYv6c9Iozpwe5VW YQBw== X-Gm-Message-State: APjAAAXWrWJkmhZfr3jbMlQhKWGLdF1kG0tpJ1WXTuQz0Bn/Cuq40ktE 2j+frSH3YR0dvZDXXETJBApdGbU/R2I= X-Google-Smtp-Source: APXvYqzufaKIH2yFtJKt/PAlyEiLYKiQxZwNEqm75p8FMQ5XDYt4a/jHjsFBr4WM0QP6oZC70qK17A== X-Received: by 2002:a05:6000:8c:: with SMTP id m12mr1285707wrx.142.1580417120933; Thu, 30 Jan 2020 12:45:20 -0800 (PST) Received: from 1aq-andre.garage.tyco.com ([77.107.218.170]) by smtp.gmail.com with ESMTPSA id x7sm8874885wrq.41.2020.01.30.12.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 12:45:20 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: linux-kernel@vger.kernel.org Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Anson Huang , Dmitry Torokhov , =?utf-8?q?Horia_Geant=C4=83?= , Aymen Sghaier , Herbert Xu , "David S. Miller" , Rob Herring , Mark Rutland , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-input@vger.kernel.org Subject: [PATCH 1/3] ARM: dts: imx7s: add snvs clock to pwrkey Date: Thu, 30 Jan 2020 20:45:14 +0000 Message-Id: <20200130204516.4760-1-git@andred.net> X-Mailer: git-send-email 2.23.0.rc1 MIME-Version: 1.0 Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org On i.MX7, the SNVS requires a clock. This is similar to the clock bound to the SNVS RTC node, but if the SNVS RTC driver isn't enabled, then SNVS doesn't work, and as such the pwrkey driver doesn't work (i.e. hangs the kernel, as the clock isn't enabled). Also see commit ec2a844ef7c1 ("ARM: dts: imx7s: add snvs rtc clock") for a similar fix. Signed-off-by: André Draszik Cc: Anson Huang Cc: Dmitry Torokhov Cc: "Horia Geantă" Cc: Aymen Sghaier Cc: Herbert Xu Cc: "David S. Miller" Cc: Rob Herring Cc: Mark Rutland Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-input@vger.kernel.org --- .../devicetree/bindings/crypto/fsl-sec4.txt | 17 +++++++++++++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 2 files changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 2fe245ca816a..755c2838d658 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -449,6 +449,19 @@ System ON/OFF key driver Value type: Definition: this is phandle to the register map node. + - clocks + Usage: optional, required if SNVS LP requires explicit + enablement of clocks + Value type: + Definition: a clock specifier describing the clock required for + enabling and disabling SNVS LP RTC. + + - clock-names + Usage: optional, required if SNVS LP requires explicit + enablement of clocks + Value type: + Definition: clock name string should be "snvs-pwrkey". + EXAMPLE: snvs-pwrkey@020cc000 { compatible = "fsl,sec-v4.0-pwrkey"; @@ -456,6 +469,8 @@ EXAMPLE: interrupts = <0 4 0x4> linux,keycode = <116>; /* KEY_POWER */ wakeup-source; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; }; ===================================================================== @@ -547,6 +562,8 @@ FULL EXAMPLE interrupts = <0 4 0x4>; linux,keycode = <116>; /* KEY_POWER */ wakeup-source; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1b812f4e7453..6240a6f58048 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -614,6 +614,8 @@ linux,keycode = ; wakeup-source; status = "disabled"; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; }; }; From patchwork Thu Jan 30 20:45:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 208239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64F3FC2D0DB for ; Thu, 30 Jan 2020 20:45:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4005F20674 for ; Thu, 30 Jan 2020 20:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727277AbgA3UpY (ORCPT ); Thu, 30 Jan 2020 15:45:24 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:35064 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727089AbgA3UpY (ORCPT ); Thu, 30 Jan 2020 15:45:24 -0500 Received: by mail-wm1-f68.google.com with SMTP id b17so5993987wmb.0; Thu, 30 Jan 2020 12:45:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aMCqGO6pzPjnIyQyehlTcprRJgNKArYeT/n5QqHWbwU=; b=UA36xoDgTEicI4r5nCLrlVqzHgrzXysWdmtx31gNpABAIOsJuk0v+3QP2ouvk+YhlJ 2vH5O2sWoMbksgVYszFsqclSd+57iH4e84b1rZYInAjYbBEZ3bD/cSuI89kgfOv55bLX NBFBagHCc/H8p04ZiSW/y1UWtJn7ulqcvbIcf2Z2F+yMHXZo64R6f6EN9oES1nb5ZFop yp1H1NOEdOPvJ/trTWVu4J1nILdWtuvRKVrgETMv/YU66GQfKP2zOk7rC6ioQj0ExDet Cc0c3bhHvQftpynu1ab95jQKnIlGs6eTBa2XJ+VhfopEAyaBa6d2x8+DDpVLik0/Iump x6kA== X-Gm-Message-State: APjAAAWhzuxAkSZkufRYW1sOw1krY4VPOuPcTYK9q9xbSQfqYeEu9ais dsOyWFrk1iC9IM8oGayxc1mBstDjdGs= X-Google-Smtp-Source: APXvYqzrgdzJcsprJtbQOSYTQznza0XkNwRyr+mAW4GFha2hvfsajM2WB3HFwV4uoD1PbB+UUbeBsA== X-Received: by 2002:a1c:7d93:: with SMTP id y141mr7380983wmc.111.1580417121978; Thu, 30 Jan 2020 12:45:21 -0800 (PST) Received: from 1aq-andre.garage.tyco.com ([77.107.218.170]) by smtp.gmail.com with ESMTPSA id x7sm8874885wrq.41.2020.01.30.12.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2020 12:45:21 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: linux-kernel@vger.kernel.org Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Anson Huang , Dmitry Torokhov , =?utf-8?q?Horia_Geant=C4=83?= , Aymen Sghaier , Herbert Xu , "David S. Miller" , Rob Herring , Mark Rutland , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-input@vger.kernel.org Subject: [PATCH 2/3] Input: snvs_pwrkey - enable snvs clock as needed Date: Thu, 30 Jan 2020 20:45:15 +0000 Message-Id: <20200130204516.4760-2-git@andred.net> X-Mailer: git-send-email 2.23.0.rc1 In-Reply-To: <20200130204516.4760-1-git@andred.net> References: <20200130204516.4760-1-git@andred.net> MIME-Version: 1.0 Sender: linux-input-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-input@vger.kernel.org At the moment, enabling this driver without the SNVS RTC driver being active will hang the kernel as soon as the power button is pressed. The reason is that in that case the SNVS isn't enabled, and any attempt to read the SNVS registers will simply hang forever. Ensure the clock is enabled (during the interrupt handler) to make this driver work. Also see commit 7f8993995410 ("drivers/rtc/rtc-snvs: add clock support") and commit edb190cb1734 ("rtc: snvs: make sure clock is enabled for interrupt handle") for similar updates to the snvs rtc driver. Signed-off-by: André Draszik Cc: Anson Huang Cc: Dmitry Torokhov Cc: "Horia Geantă" Cc: Aymen Sghaier Cc: Herbert Xu Cc: "David S. Miller" Cc: Rob Herring Cc: Mark Rutland Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-input@vger.kernel.org --- drivers/input/keyboard/snvs_pwrkey.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/input/keyboard/snvs_pwrkey.c b/drivers/input/keyboard/snvs_pwrkey.c index 2f5e3ab5ed63..c29711d8735c 100644 --- a/drivers/input/keyboard/snvs_pwrkey.c +++ b/drivers/input/keyboard/snvs_pwrkey.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,7 @@ struct pwrkey_drv_data { int wakeup; struct timer_list check_timer; struct input_dev *input; + struct clk *clk; u8 minor_rev; }; @@ -72,6 +74,9 @@ static irqreturn_t imx_snvs_pwrkey_interrupt(int irq, void *dev_id) struct input_dev *input = pdata->input; u32 lp_status; + if (pdata->clk) + clk_enable(pdata->clk); + pm_wakeup_event(input->dev.parent, 0); regmap_read(pdata->snvs, SNVS_LPSR_REG, &lp_status); @@ -96,6 +101,9 @@ static irqreturn_t imx_snvs_pwrkey_interrupt(int irq, void *dev_id) /* clear SPO status */ regmap_write(pdata->snvs, SNVS_LPSR_REG, SNVS_LPSR_SPO); + if (pdata->clk) + clk_disable(pdata->clk); + return IRQ_HANDLED; } @@ -140,6 +148,25 @@ static int imx_snvs_pwrkey_probe(struct platform_device *pdev) if (pdata->irq < 0) return -EINVAL; + pdata->clk = devm_clk_get(&pdev->dev, "snvs-pwrkey"); + if (IS_ERR(pdata->clk)) { + pdata->clk = NULL; + } else { + error = clk_prepare_enable(pdata->clk); + if (error) { + dev_err(&pdev->dev, + "Could not prepare or enable the snvs clock\n"); + return error; + } + error = devm_add_action_or_reset(&pdev->dev, + (void(*)(void *))clk_disable_unprepare, + pdata->clk); + if (error) { + dev_err(&pdev->dev, "failed to add reset action on 'snvs-pwrkey'"); + return error; + } + } + regmap_read(pdata->snvs, SNVS_HPVIDR1_REG, &vid); pdata->minor_rev = vid & 0xff;