From patchwork Tue Apr 21 05:06:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 207042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C25CBC55185 for ; Tue, 21 Apr 2020 05:06:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A130922253 for ; Tue, 21 Apr 2020 05:06:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="LyU/7qBi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726527AbgDUFGx (ORCPT ); Tue, 21 Apr 2020 01:06:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726516AbgDUFGv (ORCPT ); Tue, 21 Apr 2020 01:06:51 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37FFEC061BD3 for ; Mon, 20 Apr 2020 22:06:51 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id ms17so877918pjb.0 for ; Mon, 20 Apr 2020 22:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kSeuRl9u6GyicN//nHBoTuV+Y0T22TYVbPnayCqsBO8=; b=LyU/7qBiH/aG71draN5jUS2+mq97YNmFoEqf+sblKY9Kb1Nm1gPztdPY4WZ8PaqNbH oqikhJbyQ2BKNRLsg9jHEVPFG6hON/3WpanZx958wyihOFFNzqRSudzpR55RIgiLzfyq qTiVlBx1/z2Ob78BDAQ9PxqTc1nTl5uIviV70= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kSeuRl9u6GyicN//nHBoTuV+Y0T22TYVbPnayCqsBO8=; b=DK6trjX3NqWOkNsjTiF0hDsJDwrjsfMdWuwxAntuqZfd51VnCE1xa6UVj04SR0Pbvj 88Zw7SSlo3Kgl6OPX9lkLbtaEsjYBEg6TyZ45bJpA4abqDSCZ2NzsmY41WS65BzyLUgz bXJq21shysuPWEDTDDa7bb0tc7ZXofor6kEqKh/KfwVj5L26Kk/kDtrhpE/1pNL5vYUl RfLxdyaqQomTsrCR4bpZnTnlUSFqZNjqkTMCjFxySFg/Fj4G7SS/8+9/ueHEBa4i3fiO HS6ozaRfBJDjDbkSr1x5T6nbZSWAhTyh451svqwxiJFA/s6yuhD/lyMWf3rXqOnWYcKB EP1A== X-Gm-Message-State: AGi0Pua86w+DylhDFiLaG31ObMJtimFveq2sBRtOnVJYYWB+OWjl5W3J jRYpuy19Y05sI1QeUhFD3pglbw== X-Google-Smtp-Source: APiQypJzFod9tNAuAnsTCpNj/cBg+/8U/+LymAlvnSKQAem9cQnrWeTZHNYSnYef18mwk6N/WqT05w== X-Received: by 2002:a17:90a:f995:: with SMTP id cq21mr3440366pjb.56.1587445610633; Mon, 20 Apr 2020 22:06:50 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id p68sm1184780pfb.89.2020.04.20.22.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 22:06:50 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, jernej.skrabec@siol.net, swboyd@chromium.org, bjorn.andersson@linaro.org, robdclark@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux Date: Mon, 20 Apr 2020 22:06:17 -0700 Message-Id: <20200420220458.v2.1.Ia50267a5549392af8b37e67092ca653a59c95886@changeid> X-Mailer: git-send-email 2.26.1.301.g55bc3eb7cb9-goog In-Reply-To: <20200421050622.8113-1-dianders@chromium.org> References: <20200421050622.8113-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can be used as GPIOs in a system. Each pin can be configured as input, output, or a special function for the bridge chip. These are: - GPIO1: SUSPEND Input - GPIO2: DSIA VSYNC - GPIO3: DSIA HSYNC or VSYNC - GPIO4: PWM Let's expose these pins as GPIOs. A few notes: - Access to ti-sn65dsi86 is via i2c so we set "can_sleep". - These pins can't be configured for IRQ. - There are no programmable pulls or other fancy features. - Keeping the bridge chip powered might be expensive. The driver is setup such that if all used GPIOs are only inputs we'll power the bridge chip on just long enough to read the GPIO and then power it off again. Setting a GPIO as output will keep the bridge powered. - If someone releases a GPIO we'll implicitly switch it to an input so we no longer need to keep the bridge powered for it. Becaue of all of the above limitations we just need to implement a bare-bones GPIO driver. The device tree bindings already account for this device being a GPIO controller so we only need the driver changes for it. NOTE: Despite the fact that these pins are nominally muxable I don't believe it makes sense to expose them through the pinctrl interface as well as the GPIO interface. The special functions are things that the bridge chip driver itself would care about and it can just configure the pins as needed. Signed-off-by: Douglas Anderson Cc: Linus Walleij Cc: Bartosz Golaszewski --- Changes in v2: - ("Export...GPIOs") is 1/2 of replacement for ("Allow...bridge GPIOs") drivers/gpu/drm/bridge/ti-sn65dsi86.c | 165 ++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 6ad688b320ae..d04c2b83d699 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -54,6 +56,13 @@ #define BPP_18_RGB BIT(0) #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) +#define SN_GPIO_IO_REG 0x5E +#define SN_GPIO_INPUT_SHIFT 4 +#define SN_GPIO_OUTPUT_SHIFT 0 +#define SN_GPIO_CTRL_REG 0x5F +#define SN_GPIO_MUX_INPUT 0 +#define SN_GPIO_MUX_OUTPUT 1 +#define SN_GPIO_MUX_SPECIAL 2 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) #define SN_AUX_ADDR_19_16_REG 0x74 #define SN_AUX_ADDR_15_8_REG 0x75 @@ -102,6 +111,9 @@ struct ti_sn_bridge { struct gpio_desc *enable_gpio; struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; int dp_lanes; + + struct gpio_chip gchip; + atomic_t gchip_output; }; static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { @@ -874,6 +886,153 @@ static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) return 0; } +static struct ti_sn_bridge *gchip_to_pdata(struct gpio_chip *chip) +{ + return container_of(chip, struct ti_sn_bridge, gchip); +} + +static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); + + return (atomic_read(&pdata->gchip_output) & BIT(offset)) ? + GPIOF_DIR_OUT : GPIOF_DIR_IN; +} + +static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); + unsigned int val; + int ret; + + /* + * When the pin is an input we don't forcibly keep the bridge + * powered--we just power it on to read the pin. NOTE: part of + * the reason this works is that the bridge defaults to all 4 + * GPIOs being configured as GPIO input. Also note that if + * something else is keeping the chip powered the pm_runtime + * functions are lightweight increments of a refcount. + */ + pm_runtime_get_sync(pdata->dev); + ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); + pm_runtime_put(pdata->dev); + + if (ret) + return ret; + + return (val >> (SN_GPIO_INPUT_SHIFT + offset)) & 1; +} + +static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, + int val) +{ + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); + int ret; + + if (!(atomic_read(&pdata->gchip_output) & BIT(offset))) { + dev_err(pdata->dev, "Ignoring GPIO set while input\n"); + return; + } + + val &= 1; + ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, + BIT(SN_GPIO_OUTPUT_SHIFT + offset), + val << (SN_GPIO_OUTPUT_SHIFT + offset)); +} + +static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); + int shift = offset * 2; + int old_gchip_output; + int ret; + + old_gchip_output = atomic_fetch_andnot(BIT(offset), + &pdata->gchip_output); + if (!(old_gchip_output & BIT(offset))) + return 0; + + ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, + 0x3 << shift, SN_GPIO_MUX_INPUT << shift); + if (ret) { + atomic_or(BIT(offset), &pdata->gchip_output); + return ret; + } + + pm_runtime_put(pdata->dev); + + return 0; +} + +static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); + int shift = offset * 2; + int old_gchip_output; + int ret; + + old_gchip_output = atomic_fetch_or(BIT(offset), &pdata->gchip_output); + if (old_gchip_output & BIT(offset)) + return 0; + + pm_runtime_get_sync(pdata->dev); + + /* Set value first to avoid glitching */ + ti_sn_bridge_gpio_set(chip, offset, val); + + /* Set direction */ + ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, + 0x3 << shift, SN_GPIO_MUX_OUTPUT << shift); + if (ret) { + atomic_andnot(BIT(offset), &pdata->gchip_output); + pm_runtime_put(pdata->dev); + } + + return ret; +} + +static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + /* We won't keep pm_runtime if we're input, so switch there on free */ + ti_sn_bridge_gpio_direction_input(chip, offset); +} + +static const char * const ti_sn_bridge_gpio_names[] = { + "GPIO1", "GPIO2", "GPIO3", "GPIO4" +}; + +static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) +{ + int ret; + + /* Only init if someone is going to use us as a GPIO controller */ + if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) + return 0; + + pdata->gchip.label = dev_name(pdata->dev); + pdata->gchip.parent = pdata->dev; + pdata->gchip.owner = THIS_MODULE; + pdata->gchip.free = ti_sn_bridge_gpio_free; + pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; + pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; + pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; + pdata->gchip.get = ti_sn_bridge_gpio_get; + pdata->gchip.set = ti_sn_bridge_gpio_set; + pdata->gchip.can_sleep = true; + pdata->gchip.names = ti_sn_bridge_gpio_names; + pdata->gchip.ngpio = ARRAY_SIZE(ti_sn_bridge_gpio_names); + ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); + if (ret) { + dev_err(pdata->dev, "can't add gpio chip\n"); + return ret; + } + + return 0; +} + static int ti_sn_bridge_probe(struct i2c_client *client, const struct i2c_device_id *id) { @@ -937,6 +1096,12 @@ static int ti_sn_bridge_probe(struct i2c_client *client, pm_runtime_enable(pdata->dev); + ret = ti_sn_setup_gpio_controller(pdata); + if (ret) { + pm_runtime_disable(pdata->dev); + return ret; + } + i2c_set_clientdata(client, pdata); pdata->aux.name = "ti-sn65dsi86-aux"; From patchwork Tue Apr 21 05:06:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 207040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14413C5518B for ; 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Mon, 20 Apr 2020 22:06:54 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id p68sm1184780pfb.89.2020.04.20.22.06.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 22:06:54 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, jernej.skrabec@siol.net, swboyd@chromium.org, bjorn.andersson@linaro.org, robdclark@chromium.org, Douglas Anderson , Krzysztof Kozlowski , Paul Walmsley , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] dt-bindings: drm/bridge: ti-sn65dsi86: Convert to yaml Date: Mon, 20 Apr 2020 22:06:20 -0700 Message-Id: <20200420220458.v2.4.Ifcdc4ecb12742a27862744ee1e8753cb95a38a7f@changeid> X-Mailer: git-send-email 2.26.1.301.g55bc3eb7cb9-goog In-Reply-To: <20200421050622.8113-1-dianders@chromium.org> References: <20200421050622.8113-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This moves the bindings over, based a lot on toshiba,tc358768.yaml. Unless there's someone known to be better, I've set the maintainer in the yaml as the first person to submit bindings. Signed-off-by: Douglas Anderson --- Changes in v2: - specification => specifier. - power up => power. - Added back missing suspend-gpios. - data-lanes and lane-polarities are are the right place now. - endpoints don't need to be patternProperties. - Specified more details for data-lanes and lane-polarities. - Added old example back in, fixing bugs in it. - Example i2c bus is just called "i2c", not "i2c1" now. .../bindings/display/bridge/ti,sn65dsi86.txt | 87 ------ .../bindings/display/bridge/ti,sn65dsi86.yaml | 279 ++++++++++++++++++ 2 files changed, 279 insertions(+), 87 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt deleted file mode 100644 index 8ec4a7f2623a..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt +++ /dev/null @@ -1,87 +0,0 @@ -SN65DSI86 DSI to eDP bridge chip --------------------------------- - -This is the binding for Texas Instruments SN65DSI86 bridge. -http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf - -Required properties: -- compatible: Must be "ti,sn65dsi86" -- reg: i2c address of the chip, 0x2d as per datasheet -- enable-gpios: gpio specification for bridge_en pin (active high) - -- vccio-supply: A 1.8V supply that powers up the digital IOs. -- vpll-supply: A 1.8V supply that powers up the displayport PLL. -- vcca-supply: A 1.2V supply that powers up the analog circuits. -- vcc-supply: A 1.2V supply that powers up the digital core. - -Optional properties: -- interrupts-extended: Specifier for the SN65DSI86 interrupt line. - -- gpio-controller: Marks the device has a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify flags. - See ../../gpio/gpio.txt for more information. -- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of - the cell formats. - -- clock-names: should be "refclk" -- clocks: Specification for input reference clock. The reference - clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. - -- data-lanes: See ../../media/video-interface.txt -- lane-polarities: See ../../media/video-interface.txt - -- suspend-gpios: specification for GPIO1 pin on bridge (active low) - -Required nodes: -This device has two video ports. Their connections are modelled using the -OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for DSI input -- Video port 1 for eDP output - -Example -------- - -edp-bridge@2d { - compatible = "ti,sn65dsi86"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2d>; - - enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; - suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>; - - interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; - - vccio-supply = <&pm8916_l17>; - vcca-supply = <&pm8916_l6>; - vpll-supply = <&pm8916_l17>; - vcc-supply = <&pm8916_l6>; - - clock-names = "refclk"; - clocks = <&input_refclk>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - edp_bridge_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - edp_bridge_out: endpoint { - data-lanes = <2 1 3 0>; - lane-polarities = <0 1 0 1>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; -} diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml new file mode 100644 index 000000000000..6d7d40ad45ac --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -0,0 +1,279 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SN65DSI86 DSI to eDP bridge chip + +maintainers: + - Sandeep Panda + +description: | + The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. + http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +properties: + compatible: + const: ti,sn65dsi86 + + reg: + const: 0x2d + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge_en pin (active high). + + suspend-gpios: + maxItems: 1 + description: GPIO specifier for GPIO1 pin on bridge (active low). + + vccio-supply: + description: A 1.8V supply that powers the digital IOs. + + vpll-supply: + description: A 1.8V supply that powers the DisplayPort PLL. + + vcca-supply: + description: A 1.2V supply that powers the analog circuits. + + vcc-supply: + description: A 1.2V supply that powers the digital core. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + Clock specifier for input reference clock. The reference clock rate must + be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. + + clock-names: + const: refclk + + gpio-controller: true + '#gpio-cells': + const: 2 + description: + First cell is pin number, second cell is flags. GPIO pin numbers are + 1-based to match the datasheet. See ../../gpio/gpio.txt for more + information. + + '#pwm-cells': + const: 1 + description: See ../../pwm/pwm.yaml for description of the cell formats. + + ports: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + additionalProperties: false + + description: + Video port for MIPI DSI input + + properties: + reg: + const: 0 + + endpoint: + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: + - 0 + - 1 + - 2 + - 3 + description: See ../../media/video-interface.txt + + lane-polarities: + minItems: 1 + maxItems: 4 + items: + enum: + - 0 + - 1 + description: See ../../media/video-interface.txt + + dependencies: + data-lanes: [lane-polarities] + + required: + - reg + + port@1: + type: object + additionalProperties: false + + description: + Video port for eDP output (panel or connector). + + properties: + reg: + const: 1 + + endpoint: + type: object + additionalProperties: false + + properties: + remote-endpoint: true + + data-lanes: + minItems: 1 + maxItems: 4 + items: + enum: + - 0 + - 1 + - 2 + - 3 + description: See ../../media/video-interface.txt + + lane-polarities: + minItems: 1 + maxItems: 4 + items: + enum: + - 0 + - 1 + description: See ../../media/video-interface.txt + + dependencies: + data-lanes: [lane-polarities] + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - vccio-supply + - vpll-supply + - vcca-supply + - vcc-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + + interrupt-parent = <&tlmm>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&src_pp1800_s4a>; + vccio-supply = <&src_pp1800_s4a>; + vcca-supply = <&src_pp1200_l2a>; + vcc-supply = <&src_pp1200_l2a>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; + }; + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>; + + interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + data-lanes = <2 1 3 0>; + lane-polarities = <0 1 0 1>; + remote-endpoint = <&edp_panel_in>; + }; + }; + }; + }; + }; From patchwork Tue Apr 21 05:06:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 207041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA6B8C54FC9 for ; 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Mon, 20 Apr 2020 22:06:56 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id p68sm1184780pfb.89.2020.04.20.22.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 22:06:55 -0700 (PDT) From: Douglas Anderson To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, narmstrong@baylibre.com, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com, spanda@codeaurora.org Cc: jonas@kwiboo.se, jeffrey.l.hugo@gmail.com, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, jernej.skrabec@siol.net, swboyd@chromium.org, bjorn.andersson@linaro.org, robdclark@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd Date: Mon, 20 Apr 2020 22:06:21 -0700 Message-Id: <20200420220458.v2.5.I72892d485088e57378a4748c86bc0f6c2494d807@changeid> X-Mailer: git-send-email 2.26.1.301.g55bc3eb7cb9-goog In-Reply-To: <20200421050622.8113-1-dianders@chromium.org> References: <20200421050622.8113-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The ti-sn65dsi86 MIPI DSI to eDP bridge chip has a dedicated hardware HPD (Hot Plug Detect) pin on it, but it's mostly useless for eDP because of excessive debouncing in hardware. Specifically there is no way to disable the debouncing and for eDP debouncing hurts you because HPD is just used for knowing when the panel is ready, not for detecting physical plug events. Currently the driver in Linux just assumes that nobody has HPD hooked up. It relies on folks setting the "no-hpd" property in the panel node to specify that HPD isn't hooked up and then the panel driver using this to add some worst case delays when turning on the panel. Apparently it's also useful to specify "no-hpd" in the bridge node so that the bridge driver can make sure it's doing the right thing without peeking into the panel [1]. This would be used if anyone ever found it useful implement support for the HW HPD pin on the bridge. Let's add this property to the bindings. NOTES: - This is somewhat of a backward-incompatible change. All current known users of ti-sn65dsi86 didn't have "no-hpd" specified in the bridge node yet none of them had HPD hooked up. This worked because the current Linux driver just assumed that HPD was never hooked up. We could make it less incompatible by saying that for this bridge it's assumed HPD isn't hooked up _unless_ a property is defined, but "no-hpd" is much more standard and it's unlikely to matter unless someone quickly goes and implements HPD in the driver. - It is sensible to specify "no-hpd" at the bridge chip level and specify "hpd-gpios" at the panel level. That would mean HPD is hooked up to some other GPIO in the system, just not the hardware HPD pin on the bridge chip. [1] https://lore.kernel.org/r/20200417180819.GE5861@pendragon.ideasonboard.com Signed-off-by: Douglas Anderson --- Changes in v2: - ("dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd") new for v2. .../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml index 6d7d40ad45ac..5746416b0f73 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml @@ -28,6 +28,10 @@ properties: maxItems: 1 description: GPIO specifier for GPIO1 pin on bridge (active low). + no-hpd: + type: boolean + description: Set if the HPD line on the bridge isn't hooked up to anything. + vccio-supply: description: A 1.8V supply that powers the digital IOs. @@ -207,6 +211,8 @@ examples: clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>;