From patchwork Tue Aug 29 09:34:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111200 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061236qge; Tue, 29 Aug 2017 02:35:49 -0700 (PDT) X-Received: by 10.99.36.7 with SMTP id k7mr3422085pgk.232.1503999349740; Tue, 29 Aug 2017 02:35:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999349; cv=none; d=google.com; s=arc-20160816; b=WRzso1hyl1nPQg2EA+KbhqDsXU4PvHeh2gLSNMRnJ6cFTfYM+UdZ3878+0PJawrGg4 FelKAi1Fvn4V39I0Pz5T4DLrXkozaYRcvBFzAzph3u9XKTZUCTOv9otE0sYTu5a1224S Q9+H9TATB4KwoTX+BTPGXz5yZ+XSgfxyix+mwBrnsZj9MrFj0loTf8+kqt9kQw+2brLh 4hnkkYoqwNu1LxAICqLpOXUY7apk6aYabBd5ux0TtmNJUEbYcsNbtYCdinhPHW0IAG8j bwG9m5a7mKARBmEfpIHoZ7wr4E1j1YUsAv4xCcnGXYS7lkmJ9rQNJq7Lm89rEaByHv+B Ywrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+h+hmPrJLvNpWCLn0aX18bfUUv+hP+ZJglKHjqgelho=; b=aD64n7E6fTAEmME0mpl7+Flm2rDEI5BXEG+A8kG2OqdOVwPhSvgstvHqEu8c2z5Qa2 BEWNWE4awW/RBNvHK6YKA6OtZyZqsMQsuBzip3rvhFM3tidsQbrIhmzSHp1ppHXONgzL McDPsBr4uG2rENkkFcJbXaojh6t8Ar+jQa6SSYOmsvaSoXqQuFk9x+M7ZHt6iAjaOrDk fS3l0rHn9A8nQIiSJleNKAyKgW4pmSxCNza0yrkfYZbf18iuDOmyDDfMwAWIKMQdjPFX B++/6wnN9bCmppAVo+GEC5fsaephuxm1Ur8OZ4q/JcsHZV1nU4n2oexOmx9VECOVOp3i cm8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YfqzHefI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b4si2002571pfj.87.2017.08.29.02.35.49; Tue, 29 Aug 2017 02:35:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YfqzHefI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbdH2Jfs (ORCPT + 6 others); Tue, 29 Aug 2017 05:35:48 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33392 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751227AbdH2Jfr (ORCPT ); Tue, 29 Aug 2017 05:35:47 -0400 Received: by mail-wm0-f48.google.com with SMTP id b14so18796792wme.0 for ; Tue, 29 Aug 2017 02:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=; b=YfqzHefIteA/tsBkVY2vL91PnjqLdaz4B5181dSdPjhxwffgdlyvTKTCunNh25kJFC LKwzWogzZMg6pHM2OJ0q2t7pYsiHoiT7IYq7aAWsp2krpCKC23zem/HHd+kjmHp6QEQy s6pGXCuk5zX7wSHYuXBOvpL6YY93c4PYV5nwo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=; b=l+zRv4fpQfzoAuaBvNQ8Y9fBje6+cgFdKKGEOZuiwVkIupz6fLbLayPKRf44Mlju2d FHMltbW2JuSPBmFcDILAoNDlA+kO2RGWGKT0xhTWjTt617FXARywX/0bfvXBIeqRTLWQ re2JsULBHvTdWjKx0yMytKl+6biB6CzseI9ZdWu2sd2cOCo8UZB+7eQ+i6u/Vb0qxUU4 HOHo695xzv0FD6dOsZRLtEMRScknDydbASlzfErcEOu+BKFHkbps1UonBn9q5mFRYNE8 gAY2VewtXKQ3ljWUWIkYY5ab6Ort4kNBFctxcinU0qWdS2eqb2dniBhWCU+UiAC74mBv szww== X-Gm-Message-State: AHYfb5ju9xjT8CctswU1lQlE5GeS6oxTAiJLodTuZC+65DEoge5Z3L6z QkY2sERJbw/g6lr6Z660lw== X-Received: by 10.28.187.4 with SMTP id l4mr1915456wmf.168.1503999346620; Tue, 29 Aug 2017 02:35:46 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:45 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dong Aisheng , Mark Rutland , devicetree@vger.kernel.org, Shawn Guo , Bai Ping , Rob Herring , Rob Herring Subject: [PATCH 1/9] dt-bindings: timer: Add nxp tpm timer binding doc Date: Tue, 29 Aug 2017 11:34:19 +0200 Message-Id: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20170829093354.GA2572@mai> References: <20170829093354.GA2572@mai> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dong Aisheng Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM) binding doc. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Shawn Guo Cc: Bai Ping Acked-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/nxp,tpm-timer.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt new file mode 100644 index 0000000..b4aa7dd --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt @@ -0,0 +1,28 @@ +NXP Low Power Timer/Pulse Width Modulation Module (TPM) + +The Timer/PWM Module (TPM) supports input capture, output compare, +and the generation of PWM signals to control electric motor and power +management applications. The counter, compare and capture registers +are clocked by an asynchronous clock that can remain enabled in low +power modes. TPM can support global counter bus where one TPM drives +the counter bus for the others, provided bit width is the same. + +Required properties: + +- compatible : should be "fsl,imx7ulp-tpm" +- reg : Specifies base physical address and size of the register sets + for the clock event device and clock source device. +- interrupts : Should be the clock event device interrupt. +- clocks : The clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : Must include the following entries: "igp" and "per". + +Example: +tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; +}; From patchwork Tue Aug 29 09:34:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111203 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061570qge; Tue, 29 Aug 2017 02:36:09 -0700 (PDT) X-Received: by 10.99.125.18 with SMTP id y18mr3296554pgc.223.1503999368917; Tue, 29 Aug 2017 02:36:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999368; cv=none; d=google.com; s=arc-20160816; b=Ui5nNAeJxUP7fwKVit5CwBZ51gCT6adCHPu1d07fyb0M+5JVLbVVgQWeOq1mvQBjgt 0+DHteKsPPaCVcrvHyU9HBWmDrUEjgpN6tZJ5sBvOD5tvtwJFhrcr4bkh2d1/+2dxo1R iLoYxVVQWD9OZFma8iZOy4juaYlBINv0fxHyUofJbpnVMI+uyZNfKgSFhpANwqad6C/Z 7QQQ4A3lEe1Y6cCYHraoDXkCFJXqAjbv4qSGV8oFwQAXmcuoaToo+9inj6kTaa8mW5bX HPTMLBOIRH1kqcsSv03OIVumT0jhn6xfZ6fKSWF3y94vBS5jDSjvAblfOcpOmra68/uA c9bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mTgplr63fPLKmAg7iAnNUrw+sJkWDqMYD+ML9mU1dp0=; b=hWJQsyKJnIDxRGzsTt2nieX7JfatNHuW6gCBNkwqHyH1zLU1dwFFbndSLd/GkVF6bG rspRYDFPwJRQ8fEekyKB3rw8gZlJczQoviuOP7F08w9+oizlvdIBAvvURCjTOOS7EwMk 89LcCp4THO2nnWIiyF7cpyumtPbeISuAjhn24W6qfnQk6WmHAS3E8kA9qt6NL6bOX2/6 qSVxxAOFC6FZrGM8Ghi7wvDEKunUXhmLOMoYKvNur4aivARYjMXmenpC4u8lRVILshWH 1wTjU4l663sGMfYCa5+N7xIncaPPRMaDOqQs+ZIVcu9c4aiTlS238Ndoc5ufAxFs2rXd +rQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L+CzjkQK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u1si1968855pgc.810.2017.08.29.02.36.08; Tue, 29 Aug 2017 02:36:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L+CzjkQK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752136AbdH2JgG (ORCPT + 6 others); Tue, 29 Aug 2017 05:36:06 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:34179 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdH2JgD (ORCPT ); Tue, 29 Aug 2017 05:36:03 -0400 Received: by mail-wm0-f41.google.com with SMTP id f13so18676655wme.1 for ; Tue, 29 Aug 2017 02:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hw8SPcc7bdppz8KvYUFfFEcjTWQWrd10aHA8KkB1/hM=; b=L+CzjkQK4etCafApqAtlI6CDwT9/xDlQV+zbqRZyqLXrvBf5l/Dcs3IiroTEo+L8Ro UHUza4gRfYATL9OCRywdEO25oQSbXgNa+iwKsXhKpfnqOpo/Xe01NGM/hFGdiElMbLOV Ll/zmJ2cv8VK6jssS69XOjRDzMK3jSLVcgwjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hw8SPcc7bdppz8KvYUFfFEcjTWQWrd10aHA8KkB1/hM=; b=erB6ZNjZ1xWVenVvcmXxHDV8FrjshlSFB9BWT1nLvdA8UN9/D8FecFdrjkrXa5pba3 LGGZakO85kaxMKzbSKaa63F+IKT9UbYLk0i+BJtpYx9rVq3yCIPFOgijr+JIyoDu7kmq 2wKqy++B5kMDI+V/xh20CDE3s1mFz/uhhqHrG1PBwviygOMT2CdNAm+2Yl1Myg/x9z3M azm0w5CiEWVrLMJg9lb5kRAyAMdArwYv8Zzs/J+t6DP3fAnCPurgX+tRyATBlRKmSfTc JRgyJK7gpaM9rKRDL1xFNZ8RS254kO81E11C5RiNexdQ/5y7sbZ8OKPRXAWnb40jcG17 Rmeg== X-Gm-Message-State: AHYfb5jwjWQYpj/PaG1gj5YezFOx5q9u1IyEsUA6bjYrHwhpG2v8qlUC axFD6nW7YYZ4u9wz X-Received: by 10.28.105.24 with SMTP id e24mr1099111wmc.47.1503999362509; Tue, 29 Aug 2017 02:36:02 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.36.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:36:02 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 6/9] devicetree: bindings: Deprecate property, update example Date: Tue, 29 Aug 2017 11:34:24 +0200 Message-Id: <1503999271-15712-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Magnus Damm Deprecate "renesas,channels-mask" and update the r8a7790 CMT example. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index e81e0d2..8fb7c93 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -60,21 +60,31 @@ Required Properties: in clock-names. - clock-names: must contain "fck" for the functional clock. - - renesas,channels-mask: bitmask of the available channels. + - renesas,channels-mask: , information kept in device driver. -Example: R8A7790 (R-Car H2) CMT0 node - - CMT0 on R8A7790 implements hardware channels 5 and 6 only and names - them channels 0 and 1 in the documentation. +Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; + compatible = "renesas,cmt0-r8a7790", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 142 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_CMT0>; clock-names = "fck"; + }; - renesas,channels-mask = <0x60>; + cmt1: timer@e6130000 { + compatible = "renesas,cmt1-r8a7790", "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clock-names = "fck"; };