From patchwork Thu Jun 18 11:33:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 206743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79AB3C433E1 for ; Thu, 18 Jun 2020 11:34:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E1F42071A for ; Thu, 18 Jun 2020 11:34:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="QSyKmhg4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729568AbgFRLeg (ORCPT ); Thu, 18 Jun 2020 07:34:36 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:51063 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729506AbgFRLeO (ORCPT ); Thu, 18 Jun 2020 07:34:14 -0400 X-UUID: 8f7a796946cc4843a9fb0c2a7297c535-20200618 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=YOyQ+xNoYb3LVTxsjHvGeSZpfP5WbSuesuRvHY3x/ss=; b=QSyKmhg4bn0fcCogFJ2e7S+UQoFJu+JZ5C6mUCkF0nVrDcsn8lCQZi4KqHD2aUWD3kqX8io654fogPGXPRbuNsYomtodJYcNw4rD8+I98nxBucL7BpHvvQypa/7MITcpLHCCAVopm7wbJY2rDNcDiYovxv4WMylqIW3yoIKF5cg=; X-UUID: 8f7a796946cc4843a9fb0c2a7297c535-20200618 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 773315099; Thu, 18 Jun 2020 19:34:05 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 19:34:01 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Jun 2020 19:34:01 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Sean Wang CC: mtk01761 , Andy Teng , , , , , , , , CC Hwang , Loda Chou Subject: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Date: Thu, 18 Jun 2020 19:33:32 +0800 Message-ID: <1592480018-3340-2-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 591640295288D394FECD5647B9F01693616AD9C0716C35C57EF74C52D2E77B222000:8 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Andy Teng Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng --- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml -- 1.7.9.5 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 0000000..85819a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: + const: mediatek,mt6779-pinctrl + + reg: + minItems: 9 + maxItems: 9 + description: | + physical address base for gpio-related control registers. + + reg-names: + description: | + GPIO base register names. The names are "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: | + Specifies the summary IRQ. + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': + type: object + patternProperties: + '-pins*$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/-pinfunc.h directly. + + bias-disable: + type: boolean + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + input-enable: + type: boolean + + input-disable: + type: boolean + + output-low: + type: boolean + + output-high: + type: boolean + + input-schmitt-enable: + type: boolean + + input-schmitt-disable: + type: boolean + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + drive-strength: + description: | + Selects the drive strength for the specified pins in mA. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [2, 4, 6, 8, 10, 12, 14, 16] + + required: + - pinmux + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + mmc0_pins_default: mmc0-0 { + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + mediatek,pull-up-adv = <1>; + }; + clk-pins { + pinmux = ; + mediatek,pull-down-adv = <2>; + }; + rst-pins { + pinmux = ; + mediatek,pull-up-adv = <0>; + }; + }; + }; + + mmc0 { + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-names = "default"; + }; From patchwork Thu Jun 18 11:33:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 206742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70051C433E2 for ; Thu, 18 Jun 2020 11:34:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B8F3206C3 for ; Thu, 18 Jun 2020 11:34:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="I9pzrWDe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729506AbgFRLet (ORCPT ); Thu, 18 Jun 2020 07:34:49 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:21807 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728261AbgFRLeL (ORCPT ); Thu, 18 Jun 2020 07:34:11 -0400 X-UUID: 727a8d93be484cf38b0cce88d0ec8727-20200618 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hw1Pb8jVQk9FC4VBMjRDMJKfMp8kJn7O5WM3f/NAK3Y=; b=I9pzrWDeR3L1ilz8GlkAFVNlwhrc38UXhd9YtRESy9AfoWZOPapGnwkhGd0bbZ6P1vJ1j1Jp9Tm1srnjv1NoF6Kiw0q3v/HJSDojKY81TuCXVEDJwWB+ariMDb8y73PedUnpFIySOhK5Ke9r17xJaZRfBYLgApTKg4AJH2dxAtI=; X-UUID: 727a8d93be484cf38b0cce88d0ec8727-20200618 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 218966080; Thu, 18 Jun 2020 19:34:05 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 19:34:02 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Jun 2020 19:34:02 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Sean Wang CC: mtk01761 , Andy Teng , , , , , , , , CC Hwang , Loda Chou , Hanks Chen , Mars Cheng Subject: [PATCH v6 3/7] pinctrl: mediatek: avoid virtual gpio trying to set reg Date: Thu, 18 Jun 2020 19:33:34 +0800 Message-ID: <1592480018-3340-4-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org for virtual gpios, they should not do reg setting and should behave as expected for eint function. Signed-off-by: Hanks Chen Signed-off-by: Mars Cheng --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 ++++++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + drivers/pinctrl/mediatek/pinctrl-paris.c | 7 ++++++ 3 files changed, 33 insertions(+) -- 1.7.9.5 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index b77b18f..c53e2c3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -243,6 +243,28 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) return EINT_NA; } +/* + * Virtual GPIO only used inside SOC and not being exported to outside SOC. + * Some modules use virtual GPIO as eint (e.g. pmif or usb). + * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping + * and we can set GPIO as eint. + * But some modules use specific eint which doesn't have real GPIO pin. + * So we use virtual GPIO to map it. + */ + +bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n) +{ + const struct mtk_pin_desc *desc; + bool virt_gpio = false; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; + + if (desc->funcs && !desc->funcs[desc->eint.eint_m].name) + virt_gpio = true; + + return virt_gpio; +} + static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n, struct gpio_chip **gpio_chip) @@ -295,6 +317,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) if (err) return err; + if (mtk_is_virt_gpio(hw, gpio_n)) + return 0; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 27df087..bd079f4f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -315,4 +315,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val); +bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n); #endif /* __PINCTRL_MTK_COMMON_V2_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 90a432b..a23c182 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -769,6 +769,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) if (gpio >= hw->soc->npins) return -EINVAL; + /* + * "Virtual" GPIOs are always and only used for interrupts + * Since they are only used for interrupts, they are always inputs + */ + if (mtk_is_virt_gpio(hw, gpio)) + return 1; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value); From patchwork Thu Jun 18 11:33:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 206744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D3A6C433DF for ; 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X-UUID: a94d3c64965642309da38fbdceb20e6d-20200618 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 676282247; Thu, 18 Jun 2020 19:34:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 19:34:01 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Jun 2020 19:34:02 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Sean Wang CC: mtk01761 , Andy Teng , , , , , , , , CC Hwang , Loda Chou , Hanks Chen Subject: [PATCH v6 6/7] clk: mediatek: add UART0 clock support Date: Thu, 18 Jun 2020 19:33:37 +0800 Message-ID: <1592480018-3340-7-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: FB95E0EE193F82EDDAB6AE7DE289638071D94AEE1E98FE6F6EB8A722D1B67CE12000:8 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add MT6779 UART0 clock support. Signed-off-by: Hanks Chen Signed-off-by: mtk01761 --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.7.9.5 diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",