From patchwork Mon Aug 28 14:29:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111170 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4922461qge; Mon, 28 Aug 2017 07:32:12 -0700 (PDT) X-Received: by 10.99.180.2 with SMTP id s2mr719379pgf.183.1503930731952; Mon, 28 Aug 2017 07:32:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930731; cv=none; d=google.com; s=arc-20160816; b=Ve1PM5gN+J2RdeEl6KdcWtApJgKD1pYJB2VHoDCJ9y/APKpC6BA3ueoInWquSfnn2F SE9IMk9Qpcnv8J9GNFs0WaMVJhMgKaa/ziuirq1Q/1NodpOKRgx1uXC7W9k1plLVpnIQ om4XFm6qiG0qqx7u7YoAqeKmNRWwAoFh2BbXnmdkKOPW/aAh4f5PEgYuMB/NFA/dF8jN F6Xl9zbeoN14SZoMNP/5niePbvt26No0MxOAQxXIp+Itdvk1+nDoGSR2Z9y3hZmUKHbq 1aH7BlrWolcjNCf/VTn67Ql9SfphioLX6ySs+ECXT/QKgI1c85ZIo70Q183fe7zj74Nc 9bAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=DROVhI4wEKUjPn/upt3yg7EKO4xwfiSsCnakhqcU3DA=; b=QYHp0r+wzIS1MKgVP31hOJaR2lYcBtWk6lfhta0LHgCWzTYgMDD4d8WMF4nIx2wint 6Br8NhdWLBLtFBEnh0nT6GxWxQ0y7EkNM8/ksMYeGo3AXiw0+WEZjOKTFkcQsGstnMbU 62UgSIIC/7NZDOw7HDWUE7KGmjHxlcP3aEzYyGZrAQWHeh9Pilkiyr9hpnlS0asE1vp7 PHDfW5j9OTqof9GF7v5Uxbc6kudx2eKyLPwYT12AGpIpBLUKlAyfKDDb4mEsMLIE4xk0 Lhoqx0U4XjRkme3MgqNd8LjzsRhxOm1rXc3AkyJPLGHQHMFiQ+rUs0Vgq321csZzxOfK K2Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=R6Vo+OmJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c188si367538pfa.427.2017.08.28.07.32.11; Mon, 28 Aug 2017 07:32:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=R6Vo+OmJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751775AbdH1OcJ (ORCPT + 26 others); Mon, 28 Aug 2017 10:32:09 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:38607 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751231AbdH1O3W (ORCPT ); Mon, 28 Aug 2017 10:29:22 -0400 Received: by mail-wm0-f41.google.com with SMTP id t201so4742132wmt.1 for ; Mon, 28 Aug 2017 07:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DROVhI4wEKUjPn/upt3yg7EKO4xwfiSsCnakhqcU3DA=; b=R6Vo+OmJ7a1VwwWwAkMP8AVtHGXpsUf1/X1ISWLj6rt6T+4ZygJTRvoZqxIZp8c6R1 fzsBPhdU6/uEY5tECTotXWPyT67YMl3N6DYHs7WmqwboW3ibGXEU7/iLapZMMFGoF+jv gPuC/iNaSnhypLhHqgPfcBaWMQw3+WrGhPajheCnAGB0UFEmBgzYu1h1L3ORZh2mOk+/ zaZrQ0MbOrVc9aZgIM9R+Nno0AtW8ceex3Pnyr718QWhxb5LgRlA50AcUHYysUMr8rbK QA3hFLsTd5KU9nvuFBlLNxZV9Z9VgwJ41ivtb9xMJHMX3FqXyN/Ztsrs7hLRCZTxvfx7 aDWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DROVhI4wEKUjPn/upt3yg7EKO4xwfiSsCnakhqcU3DA=; b=OMhWOjYIOCLicF8Z7JJXINwQm+I1axaJfR89vhN4+OTJgefk79cOYcnTpM34N9VNSp kd32Tll/Cq3cq/nG41YVw2bWXZiZ1RFISCnrE2Ia59ytxjSY1sOpq1GVFnHpEJvVWf+O 3RVt+9KT1wVNC6OWEKqBF6uJbWLOsBSziuT8bVQqhL1RbRywANtGW2ioV4QEo3gE+BNs /AbcKskBxo6IYoevXg1mr9fMN3GhiQvAio7DTVa536qcS9GOB1YcsNBVRuPhOLUMq9V5 mPyPAqrNiz8eAfXeGg6MwSbuBKHTl5qS6WDpepzOjDhMfo+tvXMWM/7PjNyZ7el8I5Ys SQaw== X-Gm-Message-State: AHYfb5iWirRRhS2ey7wcYgvnvR3NMbV5Hj9fuNOwwDME6D4wZuwiAGJx AHM/nX6LBpFMVxyf X-Received: by 10.28.188.67 with SMTP id m64mr450998wmf.174.1503930561406; Mon, 28 Aug 2017 07:29:21 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:20 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/13] mmc: meson-gx: cfg init overwrite values Date: Mon, 28 Aug 2017 16:29:04 +0200 Message-Id: <20170828142915.27020-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org cfg init function overwrite values set in the clk init function Remove the cfg pokes from the clk init. Actually, trying to use the CLK_AUTO, like initially tried in clk_init, would break the card initialization Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index d2de5c11cdce..7d14d382cb1c 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -337,7 +337,7 @@ static int meson_mmc_clk_init(struct meson_host *host) int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; const char *clk_div_parents[1]; - u32 clk_reg, cfg; + u32 clk_reg; /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = 0; @@ -402,12 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) return PTR_ERR(host->cfg_div_clk); - /* Ensure clock starts in "auto" mode, not "always on" */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg &= ~CFG_CLK_ALWAYS_ON; - cfg |= CFG_AUTO_CLK; - writel(cfg, host->regs + SD_EMMC_CFG); - ret = clk_prepare_enable(host->cfg_div_clk); if (ret) return ret; @@ -956,6 +950,9 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto err_core_clk; + /* set config to sane default */ + meson_mmc_cfg_init(host); + /* Stop execution */ writel(0, host->regs + SD_EMMC_START); @@ -964,9 +961,6 @@ static int meson_mmc_probe(struct platform_device *pdev) writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); - /* set config to sane default */ - meson_mmc_cfg_init(host); - ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, meson_mmc_irq_thread, IRQF_SHARED, NULL, host); From patchwork Mon Aug 28 14:29:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111161 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4918347qge; Mon, 28 Aug 2017 07:29:35 -0700 (PDT) X-Received: by 10.84.130.76 with SMTP id 70mr996653plc.258.1503930575222; Mon, 28 Aug 2017 07:29:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930575; cv=none; d=google.com; s=arc-20160816; b=hVlnDmm6jTNYLAjBbRRB6u5RSn0i2lhPrhpgp6vaws6TNFBAhgKLhdiEHjEJLrZm2i C+TRGDVQh9HFcGCEh1e/6hCdRJvyCfE57LroTSunqJS5Qs682LkPuBSB0LQEF5ads8yF kBcnltgNwL0ufzqVA6fggl2vD/IPWUKt8OlsEmyFBPrMcHfuZHH7Hlax9pLIN3qFVEJZ 8ZmZD38gXwL4ZClMXYnYewXyXjoJKL9dnfT3Nmxf3lbEf+aaWW8CUtFdjlJCILFr5ysT n7mDX6bP6xk5O/YfaHtd+cayNQkSu91xTLUJUBeCl8fXOc43LBcyai3bI+ruyBKxhzSx fn8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nY5vKq86mNqda4qj8Dd1b9Eoxv8nkED9wOV2EJqvD+Q=; b=J/VCE9RZzzlSW/3hJTdOQj1tu9tPXq765smNuEkSE3EbkP4rsFOhl1er4zwmQ5dW18 baQeYceg2GnnL6fYS5OnKew9QFV8wxdA1ujHim37QNOclIl6dAIOJZFBfD4IpG6aaE2/ StJRgfvie+TARClqIMCjkYkngZo4/4TNSbVV73XjF05hBVIFjSUO1kDP8Z/rucRRLNeI JqAsvGHGo2q0netEQzK+3/NrKuS5Lg80UJ6cPsyfrQvNKGV8T8KLILLws0tcuxcAZUZP YBlimTfyf/vXatVOHJE/Ftuqaj/oS74KV1njLrqdoc/FP4efrC7knDjRgFpQmm9mLk9I gu1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ADrsH5hz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s36si400338pld.335.2017.08.28.07.29.32; Mon, 28 Aug 2017 07:29:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ADrsH5hz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751390AbdH1O31 (ORCPT + 26 others); Mon, 28 Aug 2017 10:29:27 -0400 Received: from mail-wr0-f181.google.com ([209.85.128.181]:35340 "EHLO mail-wr0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751288AbdH1O3X (ORCPT ); Mon, 28 Aug 2017 10:29:23 -0400 Received: by mail-wr0-f181.google.com with SMTP id j29so1308244wre.2 for ; Mon, 28 Aug 2017 07:29:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nY5vKq86mNqda4qj8Dd1b9Eoxv8nkED9wOV2EJqvD+Q=; b=ADrsH5hzRP/gPsqY1dUfBwQDT7VInkxe0j3Pr00C1KakaeKlKM5+fPf7LCq6nVHBiz g+H8uMahQqOhZkVw806zrEGFAQ9c+qbFO7zjHuWOaemMsIXFSmIU8N9us5NZg8Fpp8Ml pzAFlQmrlBEeeh7kNFnon5qjP921ENA99kTl2w8bQ62/jPqF5NqcbU0IhPVHOc0OBLGt A6UklAuwAPS014rjPYtaNoyQ34ZmqhptkqZnIHAbunx9RdfpHEogAni3pDt9rgnho4ok 2zJ7gBKMHw7N7fUCWetXOUn/wHijjvw8qqgTiFcs5hl755JmRbPEeJEh7xzPdfmF8ZAV symQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nY5vKq86mNqda4qj8Dd1b9Eoxv8nkED9wOV2EJqvD+Q=; b=GnJRB1/UvilKtF4re+SRJDGnF5EKE0CyWPtZPuyCQnvviJyXRmYjUJisTmujmQnWOm kV7LQ758kbyg5zfNOTn4p3q/a9ctFljKpZ+dTKTZnCP9Hbcee4p1Qxc0pmVpdPq/xjXN A90oTirQKRsrewK+tw4s1kEB3XUNooodYabOBbXIHWGcRk7Kh+joNeWvV2nmlLiW5rfb lfy6CwJwrs0VzMOcPPfunRZSqovUKRIR23bmVpytCitlC1gXHJ++EOi1MVh/8XZfkogH G/FKV3glbUMW5m0F0ctdCD4m6spvF/E+K/cbyKTFcLMuxbeqR1lymVUkoUOA4qUGkwE9 xqiw== X-Gm-Message-State: AHYfb5hSSudjvEd/cF61hcRMDbESxaTrMeRv/dtbdX3OnKqk1ZhI3uQT t6h1f9Tm1LQKC99r X-Received: by 10.223.138.239 with SMTP id z44mr509845wrz.85.1503930562305; Mon, 28 Aug 2017 07:29:22 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:21 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/13] mmc: meson-gx: rework set_ios function Date: Mon, 28 Aug 2017 16:29:05 +0200 Message-Id: <20170828142915.27020-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove conditional write of cfg register. Warn if set_clk fails for some reason. Consistently use host->dev instead of mixing with mmc_dev(mmc) Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 7d14d382cb1c..0d29f1f347eb 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -444,8 +444,8 @@ static void meson_mmc_set_tuning_params(struct mmc_host *mmc) static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); - u32 bus_width; - u32 val, orig; + u32 bus_width, val; + int err; /* * GPIO regulator, only controls switching between 1v8 and @@ -473,7 +473,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) int ret = regulator_enable(mmc->supply.vqmmc); if (ret < 0) - dev_err(mmc_dev(mmc), + dev_err(host->dev, "failed to enable vqmmc regulator\n"); else host->vqmmc_enabled = true; @@ -482,9 +482,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } - - meson_mmc_clk_set(host, ios->clock); - /* Bus width */ switch (ios->bus_width) { case MMC_BUS_WIDTH_1: @@ -503,8 +500,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } val = readl(host->regs + SD_EMMC_CFG); - orig = val; - val &= ~CFG_BUS_WIDTH_MASK; val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); @@ -518,11 +513,12 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (ios->timing == MMC_TIMING_MMC_HS400) val |= CFG_CHK_DS; - if (val != orig) { - writel(val, host->regs + SD_EMMC_CFG); - dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", - __func__, orig, val); - } + err = meson_mmc_clk_set(host, ios->clock); + if (err) + dev_err(host->dev, "Failed to set clock: %d\n,", err); + + writel(val, host->regs + SD_EMMC_CFG); + dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); } static void meson_mmc_request_done(struct mmc_host *mmc, From patchwork Mon Aug 28 14:29:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111169 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4921659qge; Mon, 28 Aug 2017 07:31:40 -0700 (PDT) X-Received: by 10.98.158.215 with SMTP id f84mr763855pfk.246.1503930700366; Mon, 28 Aug 2017 07:31:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930700; cv=none; d=google.com; s=arc-20160816; b=OwfThjWPFCMRN9SoODWykoCQncdV/uz3cc3QqUV6vA6llYLzox7za5+6uPERBzedgx bf5zBK3XvDEHXPXsrqj56jhYHLhUVMMvMGjpCjlq9iHN+c4yAxoV75kVeAlDQYyc0K7F 8g7Gso4c4ysY2hNZgA30C0tBBiL27ikWzl5CTOvYV+EI14RVs6y4RrjF6bxFWcheZvFK 7j0IW8QrKuLFofTvYam5MnhcQAJAL3IDU5CsYnXKeVmtlaCcVqeZrm4GW8pb7GF06UrD aQzXAX3C09VRt+F/2m2tTMRtKb7XuFdGFUr0+PX8NwfeDgHPXpO7CyqJuSpPSCoERuCA s8uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JubhEjdiy4vTDvuz6Ny9wsxGx4qGeVQtJJv/xR7LeOs=; b=w+SngQMCpkafV0DkUrs6hgtoT6g4FjC7rFJQJ8kHdvqVL3cEoN8M+UecJHNNFwRd0Y br2YIcKJIjQe2IwV6DIT19CvEtZvnv6fSY3BJyyQ8+/UoF7SZKTOxjawZC3lx+EP8wcD DAKo3Vw4FVniIAqKBEnbOKfrqEV+ajgMJJsfStcVxb/RxXLvuKXLZtblgOyjLQo3aNN0 dtMRCgfC+uAI4ukeT6pxwNfMF4XrRYHNf5WcuCnLlruUALtS49qaBzCZgCcUXr62oxlo WRigxSaIt160ovJYfesn+e5t5aE2oDSdBchwsgm8uqOru474pZNyLVNWHxlEWbSb/rpE yKSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=QlVTTZD2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q75si421485pfj.6.2017.08.28.07.31.39; Mon, 28 Aug 2017 07:31:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=QlVTTZD2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751727AbdH1Obg (ORCPT + 26 others); Mon, 28 Aug 2017 10:31:36 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:35349 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751326AbdH1O3Z (ORCPT ); Mon, 28 Aug 2017 10:29:25 -0400 Received: by mail-wr0-f169.google.com with SMTP id j29so1308549wre.2 for ; Mon, 28 Aug 2017 07:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JubhEjdiy4vTDvuz6Ny9wsxGx4qGeVQtJJv/xR7LeOs=; b=QlVTTZD2+rNVK9diOr9tmCX3Om6+CzRo8ksONeZm7+ML7lLWeK+JciZ0p0FN31eVSF 9hNShAABOGhxg9CkgQEG245NbP03/hYLcYy2MiSyfANB4L6pIKFhYkVkkp7Izb/sa8Vu hL4ugG1TVfgcFjHM3hp/ivLUSZGUsa8ox1Fe7D3KxUZrlOTWBuSsPR32DOQvANx76mcN KOChM6mxx8VoZKGPGcM5undgihonyJxr1XRb92/gAlEdu4P4Zs/cwzE2FQZIr8vuVS9x +/M0RcjWU+aNidORnCTRBgg1PYPZ8ur/aILdJoeMgPZVctroKamPMzasxfJeahd79W9U 2Q2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JubhEjdiy4vTDvuz6Ny9wsxGx4qGeVQtJJv/xR7LeOs=; b=FGoC8DZ+XVu6B2nxHEP+kznM/xWuOGufDsfmhU6A/viNSVyJUEHx9fYPwIHCZfSfXf OHSd6zEX7OWuw5khzTJGb3UvrTTCWyYBFDTFcuZOW+2NE7dPLBsr9dTydvHhLeQG+1hV j0dOMXLxhwARWgLVpFvs4Z6/vK80mDeLLcfHYAiLVgKCPkGKwIub/ng5JNFBGjM0veIE 9J7ztXAhlMl+I0QNszxZeR68N3tj5qlcYtV1waNLkHmyso0i6B0dn2RTOPyT6sLzxvYF /hCM6QZZ97N8nKHz4Ay/fSGX7PHni/RTrYnD6MjPvVsr10Bp/oy0ZS5VuTwqkVoyGzT8 Fctg== X-Gm-Message-State: AHYfb5jMyS7LicAIWcYA3Q9nASNe6jIlTh+72PEk6KE91y0n6pZD3WBm cXLxmgkZvk9RUc7M X-Received: by 10.223.158.72 with SMTP id v8mr482857wre.273.1503930564394; Mon, 28 Aug 2017 07:29:24 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:23 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/13] mmc: meson-gx: rework clock init function Date: Mon, 28 Aug 2017 16:29:07 +0200 Message-Id: <20170828142915.27020-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks to devm, carrying the clock structure around after init is not necessary. Rework the function to remove these from the controller host data. Finally, set initial mmc clock rate before enabling it, simplifying the exit condition. Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 94 ++++++++++++++++++++--------------------- 1 file changed, 46 insertions(+), 48 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index cd5964aa4f58..7800a7ace2de 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -42,10 +42,7 @@ #define SD_EMMC_CLOCK 0x0 #define CLK_DIV_MASK GENMASK(5, 0) -#define CLK_DIV_MAX 63 #define CLK_SRC_MASK GENMASK(7, 6) -#define CLK_SRC_XTAL 0 /* external crystal */ -#define CLK_SRC_PLL 1 /* FCLK_DIV2 */ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) @@ -137,13 +134,9 @@ struct meson_host { spinlock_t lock; void __iomem *regs; struct clk *core_clk; - struct clk_mux mux; - struct clk *mux_clk; + struct clk *mmc_clk; unsigned long req_rate; - struct clk_divider cfg_div; - struct clk *cfg_div_clk; - unsigned int bounce_buf_size; void *bounce_buf; dma_addr_t bounce_dma_addr; @@ -291,7 +284,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) return 0; } - ret = clk_set_rate(host->cfg_div_clk, clk_rate); + ret = clk_set_rate(host->mmc_clk, clk_rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", clk_rate, ret); @@ -299,7 +292,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) } host->req_rate = clk_rate; - mmc->actual_clock = clk_get_rate(host->cfg_div_clk); + mmc->actual_clock = clk_get_rate(host->mmc_clk); dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); if (clk_rate != mmc->actual_clock) @@ -321,10 +314,13 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) static int meson_mmc_clk_init(struct meson_host *host) { struct clk_init_data init; + struct clk_mux *mux; + struct clk_divider *div; + struct clk *clk; char clk_name[32]; int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; - const char *clk_div_parents[1]; + const char *clk_parent[1]; u32 clk_reg; /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ @@ -353,55 +349,57 @@ static int meson_mmc_clk_init(struct meson_host *host) } /* create the mux */ + mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); init.name = clk_name; init.ops = &clk_mux_ops; init.flags = 0; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS; - host->mux.reg = host->regs + SD_EMMC_CLOCK; - host->mux.shift = __bf_shf(CLK_SRC_MASK); - host->mux.mask = CLK_SRC_MASK >> host->mux.shift; - host->mux.flags = 0; - host->mux.table = NULL; - host->mux.hw.init = &init; - host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); - if (WARN_ON(IS_ERR(host->mux_clk))) - return PTR_ERR(host->mux_clk); + mux->reg = host->regs + SD_EMMC_CLOCK; + mux->shift = __bf_shf(CLK_SRC_MASK); + mux->mask = CLK_SRC_MASK >> mux->shift; + mux->hw.init = &init; + + clk = devm_clk_register(host->dev, &mux->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); /* create the divider */ + div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); init.name = clk_name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; - clk_div_parents[0] = __clk_get_name(host->mux_clk); - init.parent_names = clk_div_parents; - init.num_parents = ARRAY_SIZE(clk_div_parents); - - host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; - host->cfg_div.shift = __bf_shf(CLK_DIV_MASK); - host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK); - host->cfg_div.hw.init = &init; - host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ROUND_CLOSEST; - - host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) - return PTR_ERR(host->cfg_div_clk); - - ret = clk_prepare_enable(host->cfg_div_clk); - if (ret) - return ret; + clk_parent[0] = __clk_get_name(clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + div->reg = host->regs + SD_EMMC_CLOCK; + div->shift = __bf_shf(CLK_DIV_MASK); + div->width = __builtin_popcountl(CLK_DIV_MASK); + div->hw.init = &init; + div->flags = (CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ROUND_CLOSEST); - /* Get the nearest minimum clock to 400KHz */ - host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); + host->mmc_clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) + return PTR_ERR(host->mmc_clk); - ret = meson_mmc_clk_set(host, host->mmc->f_min); + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); + ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) - clk_disable_unprepare(host->cfg_div_clk); + return ret; - return ret; + return clk_prepare_enable(host->mmc_clk); } static void meson_mmc_set_tuning_params(struct mmc_host *mmc) @@ -949,7 +947,7 @@ static int meson_mmc_probe(struct platform_device *pdev) meson_mmc_irq_thread, IRQF_SHARED, NULL, host); if (ret) - goto err_div_clk; + goto err_init_clk; mmc->caps |= MMC_CAP_CMD23; mmc->max_blk_count = CMD_CFG_LENGTH_MASK; @@ -965,7 +963,7 @@ static int meson_mmc_probe(struct platform_device *pdev) if (host->bounce_buf == NULL) { dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); ret = -ENOMEM; - goto err_div_clk; + goto err_init_clk; } host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, @@ -984,8 +982,8 @@ static int meson_mmc_probe(struct platform_device *pdev) err_bounce_buf: dma_free_coherent(host->dev, host->bounce_buf_size, host->bounce_buf, host->bounce_dma_addr); -err_div_clk: - clk_disable_unprepare(host->cfg_div_clk); +err_init_clk: + clk_disable_unprepare(host->mmc_clk); err_core_clk: clk_disable_unprepare(host->core_clk); free_host: @@ -1007,7 +1005,7 @@ static int meson_mmc_remove(struct platform_device *pdev) dma_free_coherent(host->dev, host->bounce_buf_size, host->bounce_buf, host->bounce_dma_addr); - clk_disable_unprepare(host->cfg_div_clk); + clk_disable_unprepare(host->mmc_clk); clk_disable_unprepare(host->core_clk); mmc_free_host(host->mmc); From patchwork Mon Aug 28 14:29:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111168 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4921076qge; Mon, 28 Aug 2017 07:31:20 -0700 (PDT) X-Received: by 10.98.200.154 with SMTP id i26mr760357pfk.256.1503930679913; Mon, 28 Aug 2017 07:31:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930679; cv=none; d=google.com; s=arc-20160816; b=achgqouI2agWtrUD9ma+Q7UJYKGTetSA3aNZtbS3zbW0iBfFbQbVWHY5siuAIiCZus 11AnBURiQOtZx1aaYZ52EVJezPm7pxZCu9YxfBZVJq5WHN6oE9b66oWwNXMDN2CWb3kY v4BFdiZrV5WzHdvu5z95n26aB7x+nkbKIAEhvzk9c2DztELAY2vtssUJpNeGn3/GsszE CBpucwnnvHud0lxabwLUjxiR/+Mk6etW2pjfRfl50P5RUMKlCqulWfOmcgZVsrh281Oi 7CHKcfbylwhSseq3UTHtZiK3Jg+hDElxzJ5N2K9255YwrVSQV5aP7alLzJ51AK+tiV0f C/8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=m2LavEGYkE6hveXQ402i8QyHI3Jw0kp2lrkRgTHjUds=; b=OTDMb5UhP9eG3ENlHeovXqbJs9Sv8ZQwEQJWy/n9qSa4G9osczZqSEnfuBoKWGaUKC MPlCqd77Caqp2NZFthQVcp5f+j4qcJKkPErZSlutkLeZFWzGnFy5skryMZ2C3C23kwK4 RAXNaOfsLA3INxEGb6H/A4RAdWYvyw95Xj6gzoaclnY6rYbxqH7sScdom5XjHcEP2dFs rBULjCyc7lmd9VXUCu5xtkeJJGzi2TQUsBIj4JmEtaN6sjoFMJny7OH0JVR9LhESIhNS vxeSTFjc970Kq0HnRG9C7c4q45uXxYpRcwcxq73OYVD2IoqTqDLR3bj8yL4+baO4C/BA GSyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=HcSlH7pM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t6si369329pgt.643.2017.08.28.07.31.19; Mon, 28 Aug 2017 07:31:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=HcSlH7pM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751866AbdH1ObR (ORCPT + 26 others); Mon, 28 Aug 2017 10:31:17 -0400 Received: from mail-wr0-f177.google.com ([209.85.128.177]:35352 "EHLO mail-wr0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbdH1O30 (ORCPT ); Mon, 28 Aug 2017 10:29:26 -0400 Received: by mail-wr0-f177.google.com with SMTP id j29so1308681wre.2 for ; Mon, 28 Aug 2017 07:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m2LavEGYkE6hveXQ402i8QyHI3Jw0kp2lrkRgTHjUds=; b=HcSlH7pM5y4Gn4msX+qV1eK2qjHFWI/qpmULfVsCtKVXdgpA0prvxmrCao26Momj5m QLJfRo+1OklEjZoNvq9ycy9Ag5yXyJcUaT2fCeWsdMx79Pa0ib/iyXMBt7F4DCoLm6D2 dEdyQwB8MMl/zxvgJbeuLfZkK4mTE9Hm+JRIfLfXVLy+JT0S1conHgoEhGMR0vuGRZ9f gq+rol9tcKw4hWS904omi9+xviFabfzj3AKtaon6zYY8y9e6Dcl23qlLBn7pKP8eb0w4 QvcHmbugHSjukNIEdx3/jmJQz4OyM/v+4/jaTQ00kR2tZ5Z1aCHHAR3u1o95A+p+x9hy D30A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m2LavEGYkE6hveXQ402i8QyHI3Jw0kp2lrkRgTHjUds=; b=ZHJhmQfRVmE19Diel7r8ShmUv2BKdOG6y+VaXJ33OEOQDidK7+emD78XzdqxjEFl3l +dSwpYAOtIIi//mNczgs8xT6qLxXk0p9I/du3l9+kiD/WvaKqtVr89u50KL6nIgf6r4E BhS0V0XFyjkTyRZ7D0xQfs2e8FRm2LBtJpdIZRWRj0x76M4FZNhz//IJX9YUP34DBuhU Y7RZ1P6qjGDDyCtngXIlKATMCwCy9oeg4ITgCF7psL70DI6ZHJll/4Y3KZTdWQigE0XX x0KSBsxEa2vElr15hqyyPkI5hE5eAESej4IuWSbYsugtbcKIR7g/WDLqLWxrb7nU14Pz xutg== X-Gm-Message-State: AHYfb5hlxHCHV+4/CqvIj3fyYjLtODKL5LUPlR1gwTmAAuBm75kVkIn8 WwfGWiUyJ+Ir1obVTJA= X-Received: by 10.223.130.111 with SMTP id 102mr499604wrb.211.1503930565285; Mon, 28 Aug 2017 07:29:25 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:24 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/13] mmc: meson-gx: fix dual data rate mode frequencies Date: Mon, 28 Aug 2017 16:29:08 +0200 Message-Id: <20170828142915.27020-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 7800a7ace2de..341e5a1b32cc 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -262,14 +262,29 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, mmc_get_dma_dir(data)); } -static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) +static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) +{ + if (ios->timing == MMC_TIMING_MMC_DDR52 || + ios->timing == MMC_TIMING_UHS_DDR50 || + ios->timing == MMC_TIMING_MMC_HS400) + return true; + + return false; +} + +static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) { struct mmc_host *mmc = host->mmc; + unsigned long rate = ios->clock; int ret; u32 cfg; + /* DDR modes require higher module clock */ + if (meson_mmc_timing_is_ddr(ios)) + rate <<= 1; + /* Same request - bail-out */ - if (host->req_rate == clk_rate) + if (host->req_rate == rate) return 0; /* stop clock */ @@ -278,25 +293,29 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) writel(cfg, host->regs + SD_EMMC_CFG); host->req_rate = 0; - if (!clk_rate) { + if (!rate) { mmc->actual_clock = 0; /* return with clock being stopped */ return 0; } - ret = clk_set_rate(host->mmc_clk, clk_rate); + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", - clk_rate, ret); + rate, ret); return ret; } - host->req_rate = clk_rate; + host->req_rate = rate; mmc->actual_clock = clk_get_rate(host->mmc_clk); + /* We should report the real output frequency of the controller */ + if (meson_mmc_timing_is_ddr(ios)) + mmc->actual_clock >>= 1; + dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); - if (clk_rate != mmc->actual_clock) - dev_dbg(host->dev, "requested rate was %lu\n", clk_rate); + if (ios->clock != mmc->actual_clock) + dev_dbg(host->dev, "requested rate was %u\n", ios->clock); /* (re)start clock */ cfg = readl(host->regs + SD_EMMC_CFG); @@ -490,16 +509,14 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); val &= ~CFG_DDR; - if (ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_DDR52 || - ios->timing == MMC_TIMING_MMC_HS400) + if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; val &= ~CFG_CHK_DS; if (ios->timing == MMC_TIMING_MMC_HS400) val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios->clock); + err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); From patchwork Mon Aug 28 14:29:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111164 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4918971qge; Mon, 28 Aug 2017 07:30:01 -0700 (PDT) X-Received: by 10.99.2.141 with SMTP id 135mr795976pgc.208.1503930601817; Mon, 28 Aug 2017 07:30:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930601; cv=none; d=google.com; s=arc-20160816; b=0OD4O5s+p7kZSsbhPpDXLAuGKqCT06OL4gFNVdOAxDeZ86oxNHQ87Pbfs36j5Aa7Al zHhaD9KZyEbt3aGd7qVRsbk+e3OreH2AWAVi6v756L3Q5tarrNxrH+pPNjd71N79x7/C 6iOwBZTpKc6ZiNQF3IHxPbygziFIXQLNNS60QqlmmsHiYOc8w8gf8089rpnq4pvs7VvU J32C40w903rD4q2neGEw46W79ZV6mljFHZVZ3Cz8k4ZbXNKyELpkADgk+qZXJZHznHbM VxNC12pFo/nkQnMKhPbhPIEuwSqUBl/XS7OgoSNRTD0p/IWZMuWfRG4LMaHkA4EyZ95B GjJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1jT9wGDnUBouhfMeoEutvwVzMwo6xYQd8a+2ocB0s5I=; b=bW+7DTNHej+rMh2r8zy9ZI+92WOFoC0kdWKQdO8Yq5AtViXeWy1kT7ZVw5ceFKD342 jtjlFI4BqO4tQ8mO9mjkWwXltgCnb8P9uPrr7jg2ze0NlkhndH+xJZsZYRZwsaqRblgk sCtLgeak3lX+HztKJXuMONWl46m0mwuy/yxnhsv6yNlv0tMGVCoPHg+k2Lyr6bJ/fQ60 4HhYoOzQx+1bG94pxeQwTjmTFs9ISb8LPh9XS6r8JOBghoqhl1Vm54znURsRgPqNC6E4 FOMEPdji+1CDck4cd1QmsOxnxyREDiuNr04o3XRhSimwGZqQzFJVs2YfDKRsR6cLJqZ9 FE9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=IUjf4gXY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q2si442313plh.318.2017.08.28.07.30.01; Mon, 28 Aug 2017 07:30:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=IUjf4gXY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751610AbdH1O3e (ORCPT + 26 others); Mon, 28 Aug 2017 10:29:34 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:35358 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751391AbdH1O31 (ORCPT ); Mon, 28 Aug 2017 10:29:27 -0400 Received: by mail-wr0-f169.google.com with SMTP id j29so1308854wre.2 for ; Mon, 28 Aug 2017 07:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1jT9wGDnUBouhfMeoEutvwVzMwo6xYQd8a+2ocB0s5I=; b=IUjf4gXY6yXOWKt28v5nU/gtjROa6P9ofBSuNmBKzXdf5VO+jK4spLzK87JMiOna+N tjf/IMsqT9Tj9SVuigRXBNQIldGoUNbAmy333i1ML7OjSs4NS/GgJGeiagAJ3Jvjkb+r 4fCTPbuCaDTWZ+rqGTMwb6kS/+n5nR+LhR7NPEOzhdHuiePnZXeWRC0T4YLNLBBK0UPV Lb0kPkmv7NHGJZOO9JE1F3+b0WWNew09Fcohx+65cPfXsI60/HSW+9GhtBVu5IcEL4Fx KfS/Gs2ScxpCa03jbrSB34BmVt3z5ubz3waqr/oL2cortZy+D2iTcJCH1c9s2qT1nbAp XSxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1jT9wGDnUBouhfMeoEutvwVzMwo6xYQd8a+2ocB0s5I=; b=J1KTKXLgL3ZTppnvRHJpEYh0d4Aehm6787Kra/OsXkQlVJm4G+nqagGucXsi1EE//p N9nY3RjU+ktNZyJjA5/v6s2oEM4gInmw6JIVvw007lu5O5FHPkTJfN0sqjMuDjU8GGgJ W/66YPyVWB11tdM7KvoWcClsZjkQpDfM9fGRSShRq1TJy7ym96v0cwgRRZvHDd72UTMM iMU9x7RCGNU58qaflVR3yEOjrTd9UmWvCoY3G8BCPEavVa4Y2w99zuKrEZewSbP46SeY QtKDiFJgBvthIl5eW60hhyGcw2nhNvU6IBbf6xphnofkMZIpRELS6aSQ1I3vJk4njeH/ JEAQ== X-Gm-Message-State: AHYfb5gv/hhe40OnXcRKg/M6d+U8ixSUgc1UCGuqwGbGcyfDD7XfcRFu sbLHeee2gescTrKw X-Received: by 10.223.195.140 with SMTP id p12mr577628wrf.299.1503930566356; Mon, 28 Aug 2017 07:29:26 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:25 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/13] mmc: meson-gx: work around clk-stop issue Date: Mon, 28 Aug 2017 16:29:09 +0200 Message-Id: <20170828142915.27020-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It seems that the mmc clock is also used and required, somehow, by the controller itself. It is shown during init, when writing to CFG while the divider is set to 0 will crash the SoC. During a voltage switch, the controller may crash and the card may then fail to exit busy state if the clock is stopped. To avoid this, it is best to keep the clock running for the controller, except during rate change. However, we still need to be able to gate the clock out of the SoC. Let's use the pinmux for this, and fallback to gpio mode (pulled-down) when we need to gate the clock Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 74 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 6 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 341e5a1b32cc..43aabb793121 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -137,6 +137,10 @@ struct meson_host { struct clk *mmc_clk; unsigned long req_rate; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_clk_gate; + unsigned int bounce_buf_size; void *bounce_buf; dma_addr_t bounce_dma_addr; @@ -272,6 +276,42 @@ static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) return false; } +/* + * Gating the clock on this controller is tricky. It seems the mmc clock + * is also used by the controller. It may crash during some operation if the + * clock is stopped. The safest thing to do, whenever possible, is to keep + * clock running at stop it at the pad using the pinmux. + */ +static void meson_mmc_clk_gate(struct meson_host *host) +{ + u32 cfg; + + if (host->pins_clk_gate) { + pinctrl_select_state(host->pinctrl, host->pins_clk_gate); + } else { + /* + * If the pinmux is not provided - default to the classic and + * unsafe method + */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg |= CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); + } +} + +static void meson_mmc_clk_ungate(struct meson_host *host) +{ + u32 cfg; + + if (host->pins_clk_gate) + pinctrl_select_state(host->pinctrl, host->pins_default); + + /* Make sure the clock is not stopped in the controller */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg &= ~CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); +} + static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) { struct mmc_host *mmc = host->mmc; @@ -288,9 +328,7 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; /* stop clock */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg |= CFG_STOP_CLOCK; - writel(cfg, host->regs + SD_EMMC_CFG); + meson_mmc_clk_gate(host); host->req_rate = 0; if (!rate) { @@ -299,6 +337,11 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } + /* Stop the clock during rate change to avoid glitches */ + cfg = readl(host->regs + SD_EMMC_CFG); + cfg |= CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", @@ -318,9 +361,7 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) dev_dbg(host->dev, "requested rate was %u\n", ios->clock); /* (re)start clock */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg &= ~CFG_STOP_CLOCK; - writel(cfg, host->regs + SD_EMMC_CFG); + meson_mmc_clk_ungate(host); return 0; } @@ -931,6 +972,27 @@ static int meson_mmc_probe(struct platform_device *pdev) goto free_host; } + host->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(host->pinctrl)) { + ret = PTR_ERR(host->pinctrl); + goto free_host; + } + + host->pins_default = pinctrl_lookup_state(host->pinctrl, + PINCTRL_STATE_DEFAULT); + if (IS_ERR(host->pins_default)) { + ret = PTR_ERR(host->pins_default); + goto free_host; + } + + host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, + "clk-gate"); + if (IS_ERR(host->pins_clk_gate)) { + dev_warn(&pdev->dev, + "can't get clk-gate pinctrl, using clk_stop bit\n"); + host->pins_clk_gate = NULL; + } + host->core_clk = devm_clk_get(&pdev->dev, "core"); if (IS_ERR(host->core_clk)) { ret = PTR_ERR(host->core_clk); From patchwork Mon Aug 28 14:29:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111162 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4918418qge; Mon, 28 Aug 2017 07:29:38 -0700 (PDT) X-Received: by 10.84.217.6 with SMTP id o6mr962715pli.147.1503930578880; Mon, 28 Aug 2017 07:29:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930578; cv=none; d=google.com; s=arc-20160816; b=CKXt8jDBW5us0PqAwXI09XNDHsiyz4Tp20Ivouj+1CRl346XZS1pxCx0PmQpgRSAp9 aTCn8LaJSFWHuKWYPsSVc3mBIDbWlfwdCXPhQ0/14ZWh0gCocsEoY2eA9GVSeKWwE6Vk Ehh0YxidsBycc9IKXqYAcIoCQtXKtR61Wpwqg2uGo3401P2HApqweFGw5kcVM3OdyaRq nQQ21f0m9jgVLYtYRbREGzGbBGtm1vgMwn9lRWHE1J5Uh/2XR/eT0UKWgYFP8Z0aAEPf OlfX/2PgT2jHVima/a/uWT1DMFRWAyPSeRg0QdHHwa20/YOiybLAkQjqS6rBrpKP9BGm Hg0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b8v8ooREBElbOhWT16ulVZsQ/J87vqZwz24LvUYHGC8=; b=A1anj0WBDBmw9FGJzd6Hp2/4A49STVBz2/wq8eFyW+NJI3PF7vRJ7iM8f2IZB8ZBmH wK8Xy0GSQbTD1WH4/y+j3yUwHL1LzBlN3BUu89Igqd5UzyVcwabIozbvb8M6RDDx3LWS AvJdikhkWC5bb48KccdHFOvt+c/PioULlBbT7H1KHssuzheoR/2cdl4LSSnaCX2bCtRa qVm1zaHqlsKwk+e7eNdfUrHLjRXT/RY/1cL+WOvuIaAaatYEpzsPDMEP5v3sDX0P+vkn VYGdcaPhCphIaGikgb28oH2f44O3mveM+eRUu2fkQ3pIxE1zVTyUOK/bntACI8eBjnhY Ae6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=tGkyulfC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 75si368120pfk.355.2017.08.28.07.29.38; Mon, 28 Aug 2017 07:29:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=tGkyulfC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751663AbdH1O3f (ORCPT + 26 others); Mon, 28 Aug 2017 10:29:35 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:38254 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751399AbdH1O33 (ORCPT ); Mon, 28 Aug 2017 10:29:29 -0400 Received: by mail-wr0-f171.google.com with SMTP id 40so1692074wrv.5 for ; Mon, 28 Aug 2017 07:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b8v8ooREBElbOhWT16ulVZsQ/J87vqZwz24LvUYHGC8=; b=tGkyulfCIO+kRvqTF0jKpnOWSEfON6MaRNiLkphlxW0mSEQ/wgr+4R7s6Llteh8OBn iUR26aUKP91HNas5urMWtg+OMdr6reGjRRuJ9II0oQ2JG9qxfqUGZ7gggNEL70Bnzcm6 kQMyoqfPCzThKJR621pFOEePUhRgbWyhiytyBc7ztfuQlfJOvWYX2CCWOLo7AKVWJ+Iy CXciWMkBPfr01jxu1fL/P3EtPihsmpI+iZZ4i4nu29zFxBaLxloO8fBcg1wkmIBD8Qo5 JVFiMJ8+9/N1Nv0PHSixGgzDStEk74F+xdFBtCqkn+7m5xBvj8MFsNB39iuyhywTS7+L e9Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b8v8ooREBElbOhWT16ulVZsQ/J87vqZwz24LvUYHGC8=; b=jdSo3juRRT9mz1fagR/iVC838FEEBfwTxNyX4NM9P7O90L/Q1mDgVZF2n2VhmD8f5m ZiOrFEoBCmt3+M51Tzel3v6hqEUC505WdSBOImiE/lhCbcUs7A+Ro3FqqnY150oP9oGW 6fBQxtrXbIc/ETISIJapjNF/JNJKnSp9VKoD/GNvppjug5xFR0o+4v0dLDesM3qnjVEA iHVC63Brc78zBkCYZ+fVEbe+JgekKgkfVkriZm5qb9t6cuxpvDmCgeVT4c/wKnewA+8F PTCOWESssjnUm4fl2EZJGQ/K5h6LokDvlP08Sn351qe6ZtJoGVYTDL4CLKRaSbiF25Du 8giA== X-Gm-Message-State: AHYfb5jcVwvpQbWG5sUfP9GXDRCbsXf0ioHguLeBIgVOf77MM7+XhPic X/5SClvS5t0w+Glb X-Received: by 10.223.152.72 with SMTP id v66mr554556wrb.52.1503930568034; Mon, 28 Aug 2017 07:29:28 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:27 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/13] mmc: meson-gx: implement card_busy callback Date: Mon, 28 Aug 2017 16:29:11 +0200 Message-Id: <20170828142915.27020-10-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement the card_busy callback to be able to verify that the card is done dealing with voltage switch, when the support is added later on. Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3914c3a82cc4..40fa7ae64c72 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -76,6 +76,7 @@ #define SD_EMMC_STATUS 0x48 #define STATUS_BUSY BIT(31) +#define STATUS_DATI GENMASK(23, 16) #define SD_EMMC_IRQ_EN 0x4c #define IRQ_RXD_ERR_MASK GENMASK(7, 0) @@ -902,6 +903,17 @@ static void meson_mmc_cfg_init(struct meson_host *host) writel(cfg, host->regs + SD_EMMC_CFG); } +static int meson_mmc_card_busy(struct mmc_host *mmc) +{ + struct meson_host *host = mmc_priv(mmc); + u32 regval; + + regval = readl(host->regs + SD_EMMC_STATUS); + + /* We are only interrested in lines 0 to 3, so mask the other ones */ + return !(FIELD_GET(STATUS_DATI, regval) & 0xf); +} + static const struct mmc_host_ops meson_mmc_ops = { .request = meson_mmc_request, .set_ios = meson_mmc_set_ios, @@ -909,6 +921,7 @@ static const struct mmc_host_ops meson_mmc_ops = { .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, .execute_tuning = meson_mmc_execute_tuning, + .card_busy = meson_mmc_card_busy, }; static int meson_mmc_probe(struct platform_device *pdev) From patchwork Mon Aug 28 14:29:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111167 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4920647qge; Mon, 28 Aug 2017 07:31:04 -0700 (PDT) X-Received: by 10.84.210.72 with SMTP id z66mr966680plh.139.1503930664089; Mon, 28 Aug 2017 07:31:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930664; cv=none; d=google.com; s=arc-20160816; b=tu0SVVUpzmlbzlYo2lZ7P+o8jhVatux7sUmjc63szxdCkljQ9PQFiHKHDiWnCMOMy8 SqcM11GcW8066ahhGRh4Pwo+9u7AzPqBNx0NrJ1KJFLn8x5tHudD4vJLpdK6Ts8WO9ZS YbYFMJBZ91KeDxUkT5CNnzcrItr4GF8ROcPuVTF4S1lszQ10cuXr3Rx9aWp5ZaT7C6lA TireCKfsJctuobvAbK+VOpwPjtrtVEmgO7Or1Gi4zeelOJGbrDX5eRgGImxygRnem7ir zJrnPKpYqZLrLn5Bhked2Lqq6v/3ARJiUg4tjW1ywFjVP1jGtFCBHh54H41YCLpu+1Y+ mysg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+0TkBM/ti26Xx5P8b1OzWpSIVfb3nVye+W9JkYLE8QI=; b=tigt9uZm4ZNg1y8laTVIz5loG+uazMH+EJwNlX89TawycqAUkLG7zWlWvqDYTUXooI BaFbPYdMB4FST9au/vmawthNARj0YsYmh00LYz31aIOO2ONu6zcMD+gl8UNruo2dUa0s /m7H+1Dp8bJgSKk7VsPp1mhxerTkbOvcoycJzVtWuieKMyLlof6mzEtXGlrx8HPGjGZc kg3PlNLJURthF7FdKNyywIzvReOZNDWxEFTryd2glKHr8Iy7AUqXwpUT+PO5v0tuuZKu NE62ueejgV6I3p9MeUAmztt/Oj54DaWBVMTanF4ohIQH9H3lDU4jztKBaG6B5NgaYxAA iOxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=eOfV3LP1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m3si373727pfm.375.2017.08.28.07.31.03; Mon, 28 Aug 2017 07:31:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=eOfV3LP1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751862AbdH1Oa7 (ORCPT + 26 others); Mon, 28 Aug 2017 10:30:59 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:35944 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751408AbdH1O3a (ORCPT ); Mon, 28 Aug 2017 10:29:30 -0400 Received: by mail-wr0-f175.google.com with SMTP id p14so2202654wrg.3 for ; Mon, 28 Aug 2017 07:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+0TkBM/ti26Xx5P8b1OzWpSIVfb3nVye+W9JkYLE8QI=; b=eOfV3LP19n3fpOdLshuPhgosIe4b74Ujh0ycS0y2YF+gq0v7OMS94NxMQsULCUPUGS 1l2rYcnD/puVHCK/ZlbqWvMJWXYNYwvHi2aTqWU4CXaIGB7CF36PtqDtOLnereeMoTkz UgHkT0a4+N+IFYWTVTKE9wqjNAE7U5pI2HcCAggO02dLcRclnUQB2PdmW/ayDD6cjcgk 8ExXQXUcziumN9G1g+YYlTDVxKAT2i+5XLbeZylnAesXfDxk8BGkEqx7WIrcVzFT7VDw fUK8CEjrCVaIQzxaf6kaTqnWIsRXjJLSYMcucYyWkVPwv8PdQfyMALaYFDPu1L+bdTtx 0bMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+0TkBM/ti26Xx5P8b1OzWpSIVfb3nVye+W9JkYLE8QI=; b=nIWE32JRhg0w6ffmEBeM8PNArKM0RObnU9Uv2QEVWx4MHDyOS4ARPO+sySGBlkW/Gm sz4fNCVnZl62ty04/y7uxL7w97USPXTOlVCQuZ5vLtvIcRii2a2b98HFSSbEPXfmxDNB zpnxF2OlHhkA2c+OE++HmN9G6DICFTgUxssoPOFSm/8nLhcu5X5bT7PLgnYXiQFU944N 9BmhNLsDUx/KYN8fcww7FlT6H1GalnZiIBmU4GcoIpohGGnog2S9eH0pabKr0WG9+UXR fJuylunaRG+U3KXCWdJVuxFsImjy/qjLifk1+nwJvD7xrjiRFlQ5vM7wvKtvAUXvfj16 6QSA== X-Gm-Message-State: AHYfb5jRYVR88febceHQDiqsRf1LaiM1Egd9I2/Je2VXlYtSrAYKkfeu LkFlus1cE+VKTlw5 X-Received: by 10.223.196.152 with SMTP id m24mr518103wrf.185.1503930569269; Mon, 28 Aug 2017 07:29:29 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:28 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/13] mmc: meson-gx: use CCF to handle the clock phases Date: Mon, 28 Aug 2017 16:29:12 +0200 Message-Id: <20170828142915.27020-11-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Several phases can be controlled on the meson-gx controller, the core, tx and rx clock phase. The tx and rx uses delays to allow more fine grained setting of the phase. To properly compute the phase using delays, accessing the clock rate is necessary. Instead of ad-hoc functions, use the common clock framework to set the clock phases (and access the clock rate while doing it). Acked-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 217 ++++++++++++++++++++++++++++++++-------- 1 file changed, 176 insertions(+), 41 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 40fa7ae64c72..2fa18faa7f0f 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -46,10 +46,9 @@ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) -#define CLK_PHASE_0 0 -#define CLK_PHASE_90 1 -#define CLK_PHASE_180 2 -#define CLK_PHASE_270 3 +#define CLK_TX_DELAY_MASK GENMASK(19, 16) +#define CLK_RX_DELAY_MASK GENMASK(23, 20) +#define CLK_DELAY_STEP_PS 200 #define CLK_ALWAYS_ON BIT(24) #define SD_EMMC_DELAY 0x4 @@ -121,9 +120,9 @@ #define MUX_CLK_NUM_PARENTS 2 struct meson_tuning_params { - u8 core_phase; - u8 tx_phase; - u8 rx_phase; + unsigned int core_phase; + unsigned int tx_phase; + unsigned int rx_phase; }; struct sd_emmc_desc { @@ -142,6 +141,8 @@ struct meson_host { void __iomem *regs; struct clk *core_clk; struct clk *mmc_clk; + struct clk *rx_clk; + struct clk *tx_clk; unsigned long req_rate; struct pinctrl *pinctrl; @@ -181,6 +182,90 @@ struct meson_host { #define CMD_RESP_MASK GENMASK(31, 1) #define CMD_RESP_SRAM BIT(0) +struct meson_mmc_phase { + struct clk_hw hw; + void __iomem *reg; + unsigned long phase_mask; + unsigned long delay_mask; + unsigned int delay_step_ps; +}; + +#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) + +static int meson_mmc_clk_get_phase(struct clk_hw *hw) +{ + struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); + unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); + unsigned long period_ps, p, d; + int degrees; + u32 val; + + val = readl(mmc->reg); + p = (val & mmc->phase_mask) >> __bf_shf(mmc->phase_mask); + degrees = p * 360 / phase_num; + + if (mmc->delay_mask) { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + d = (val & mmc->delay_mask) >> __bf_shf(mmc->delay_mask); + degrees += d * mmc->delay_step_ps * 360 / period_ps; + degrees %= 360; + } + + return degrees; +} + +static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, + unsigned int phase, + unsigned int delay) +{ + u32 val; + + val = readl(mmc->reg); + val &= ~mmc->phase_mask; + val |= phase << __bf_shf(mmc->phase_mask); + + if (mmc->delay_mask) { + val &= ~mmc->delay_mask; + val |= delay << __bf_shf(mmc->delay_mask); + } + + writel(val, mmc->reg); +} + +static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) +{ + struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); + unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); + unsigned long period_ps, d = 0, r; + uint64_t p; + + p = degrees % 360; + + if (!mmc->delay_mask) { + p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); + } else { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + + /* First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(p, 360 / phase_num); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * mmc->delay_step_ps); + d = min(d, mmc->delay_mask >> __bf_shf(mmc->delay_mask)); + } + + meson_mmc_apply_phase_delay(mmc, p, d); + return 0; +} + +static const struct clk_ops meson_mmc_clk_phase_ops = { + .get_phase = meson_mmc_clk_get_phase, + .set_phase = meson_mmc_clk_set_phase, +}; + static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) { unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; @@ -373,6 +458,13 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } +static void meson_mmc_set_phase_params(struct meson_host *host) +{ + clk_set_phase(host->mmc_clk, host->tp.core_phase); + clk_set_phase(host->tx_clk, host->tp.tx_phase); + clk_set_phase(host->rx_clk, host->tp.rx_phase); +} + /* * The SD/eMMC IP block has an internal mux and divider used for * generating the MMC clock. Use the clock framework to create and @@ -383,6 +475,7 @@ static int meson_mmc_clk_init(struct meson_host *host) struct clk_init_data init; struct clk_mux *mux; struct clk_divider *div; + struct meson_mmc_phase *core, *tx, *rx; struct clk *clk; char clk_name[32]; int i, ret = 0; @@ -394,9 +487,6 @@ static int meson_mmc_clk_init(struct meson_host *host) clk_reg = 0; clk_reg |= CLK_ALWAYS_ON; clk_reg |= CLK_DIV_MASK; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); writel(clk_reg, host->regs + SD_EMMC_CLOCK); /* get the mux parents */ @@ -456,10 +546,80 @@ static int meson_mmc_clk_init(struct meson_host *host) div->flags = (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST); - host->mmc_clk = devm_clk_register(host->dev, &div->hw); + clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + /* create the mmc core clock */ + core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); + if (!core) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = CLK_SET_RATE_PARENT; + clk_parent[0] = __clk_get_name(clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + core->reg = host->regs + SD_EMMC_CLOCK; + core->phase_mask = CLK_CORE_PHASE_MASK; + core->hw.init = &init; + + host->mmc_clk = devm_clk_register(host->dev, &core->hw); if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) return PTR_ERR(host->mmc_clk); + /* create the mmc tx clock */ + tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); + if (!tx) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = 0; + clk_parent[0] = __clk_get_name(host->mmc_clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + tx->reg = host->regs + SD_EMMC_CLOCK; + tx->phase_mask = CLK_TX_PHASE_MASK; + tx->delay_mask = CLK_TX_DELAY_MASK; + tx->delay_step_ps = CLK_DELAY_STEP_PS; + tx->hw.init = &init; + + host->tx_clk = devm_clk_register(host->dev, &tx->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) + return PTR_ERR(host->tx_clk); + + /* create the mmc rx clock */ + rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); + if (!rx) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = 0; + clk_parent[0] = __clk_get_name(host->mmc_clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + rx->reg = host->regs + SD_EMMC_CLOCK; + rx->phase_mask = CLK_RX_PHASE_MASK; + rx->delay_mask = CLK_RX_DELAY_MASK; + rx->delay_step_ps = CLK_DELAY_STEP_PS; + rx->hw.init = &init; + + host->rx_clk = devm_clk_register(host->dev, &rx->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) + return PTR_ERR(host->rx_clk); + + /* Set the initial phase parameters */ + meson_mmc_set_phase_params(host); + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); @@ -469,31 +629,6 @@ static int meson_mmc_clk_init(struct meson_host *host) return clk_prepare_enable(host->mmc_clk); } -static void meson_mmc_set_tuning_params(struct mmc_host *mmc) -{ - struct meson_host *host = mmc_priv(mmc); - u32 regval; - - /* stop clock */ - regval = readl(host->regs + SD_EMMC_CFG); - regval |= CFG_STOP_CLOCK; - writel(regval, host->regs + SD_EMMC_CFG); - - regval = readl(host->regs + SD_EMMC_CLOCK); - regval &= ~CLK_CORE_PHASE_MASK; - regval |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - regval &= ~CLK_TX_PHASE_MASK; - regval |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - regval &= ~CLK_RX_PHASE_MASK; - regval |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - writel(regval, host->regs + SD_EMMC_CLOCK); - - /* start clock */ - regval = readl(host->regs + SD_EMMC_CFG); - regval &= ~CFG_STOP_CLOCK; - writel(regval, host->regs + SD_EMMC_CFG); -} - static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -862,13 +997,13 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) dev_info(mmc_dev(mmc), "(re)tuning...\n"); - for (i = CLK_PHASE_0; i <= CLK_PHASE_270; i++) { + for (i = 0; i < 360; i += 90) { host->tp.rx_phase = i; /* exclude the active parameter set if retuning */ if (!memcmp(&tp_old, &host->tp, sizeof(tp_old)) && mmc->doing_retune) continue; - meson_mmc_set_tuning_params(mmc); + meson_mmc_set_phase_params(host); ret = mmc_send_tuning(mmc, opcode, &cmd_error); if (!ret) break; @@ -999,9 +1134,9 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; - host->tp.core_phase = CLK_PHASE_180; - host->tp.tx_phase = CLK_PHASE_0; - host->tp.rx_phase = CLK_PHASE_0; + host->tp.core_phase = 180; + host->tp.tx_phase = 0; + host->tp.rx_phase = 0; ret = meson_mmc_clk_init(host); if (ret) From patchwork Mon Aug 28 14:29:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 111163 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4918453qge; Mon, 28 Aug 2017 07:29:40 -0700 (PDT) X-Received: by 10.98.86.2 with SMTP id k2mr668536pfb.289.1503930580658; Mon, 28 Aug 2017 07:29:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503930580; cv=none; d=google.com; s=arc-20160816; b=HGdOstPgGXZ776cuc1h+N75rXTBFpAEnt/slupHgkumClNDXjOqqu/R5iQbJbOiraz dE2X8psrHPWp/DmOa9bpnV1K9u0djR3W4qE0Q9ax8z/dnNOi2H7XAfjoVgRFq6EZnbqZ XjZyj07DIb01IE7nqGTVZ6PmffxsfT6ly61hPo+ynZvQBIoE3s8QzCKaqtp0H3NU7Hyz 9jeP3MQHkMzHP/jSB5A4ALLI0PWueokKsCx6SVCQbDGdjj/LwVB/EP9lwlNcdbI3CeOW aDVGwzivlrocWqILBIelmAbKdCjUcrQENt/WoOan6o8hgZoZtgwRtMDGrHDxdH2EDf1r ch3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6/p7RNjyKOVhaAY7O3Thr4HF79bMnzRn5Kab+yXzW7I=; b=VYgoaz94zv8uDKUkrqSrRb4RaHK1HIvcPkVIyr4aQ3GaN6JKcKEmoB/VBr2Mh+xJgz 96OZmQAlX+mayNS4ebgEicqPnM+cirM0zEO0eCBkfguh5V+WqMUU30CelMHHcsdPAQBp SmN5Gh0Y3b4XDiRkmOaqWFkzXfJ3nxuOSH0kT7Rl086e0oZEcX19YLLfvH7JQMi9jtCH J7JbykUSeVskeYlXOjYcn08txENALHG1MiItm/tp4cma97MkyrSmEH3goQ3gq7k1r61z oB0xTrP2gT+NBi4pYZJmeg00ryEwTIrZRn7YmuU+2tOeSUKbeAfZISWVQ5/tGDdQdgZE xqIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=qdBuZoLi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q2si442313plh.318.2017.08.28.07.29.40; Mon, 28 Aug 2017 07:29:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=qdBuZoLi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751707AbdH1O3g (ORCPT + 26 others); Mon, 28 Aug 2017 10:29:36 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:34575 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdH1O3e (ORCPT ); Mon, 28 Aug 2017 10:29:34 -0400 Received: by mail-wm0-f48.google.com with SMTP id f13so13392323wme.1 for ; Mon, 28 Aug 2017 07:29:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6/p7RNjyKOVhaAY7O3Thr4HF79bMnzRn5Kab+yXzW7I=; b=qdBuZoLi06F4BdZ6RpRhkcxDDJgbp7U9cxUIhwpWuMPPj/qz+YBPVXupJZ86MsJCTU uuFP4kxjI7WUWZTvTKhMqB+1RLGbl/p68rsdrXcnppSkaNb0RPpP4BSmFn4Gbn5qCjvo PIabLZNkE1wI7oxZDZ5OFxN9HC+AWVwNbOzTdp3X+T6wDi9bymZtYBR+CeytOwOVsM0F A5C9Uoj3bKRKhTkpQHHt4IR2WJSk/26C3KvVK1v1gZfwLs2CjF3H2rjIDA9Y8mvv1GnY DmS2gvM3qxEldcf2aXAHzKoNgzrnuObcn3FJwUjpmE8PCydjTzrVYqg9KuGDDKEBzlBD ZxRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6/p7RNjyKOVhaAY7O3Thr4HF79bMnzRn5Kab+yXzW7I=; b=JrXCe7rmBxZXqKxbNdoOndgkrsOyOOx904q1xm5BptWTQRJgAZ+Q7fr5V06M/ogbfo 9UKZS3ThMYWfSBqkvgOv/VW019dIB1xPPvrl6g5AND1HAeOvzwOXvGGydLR6gwk1t62v sengTO5tK/O2yr0r5kucLPSOYePFsZZCsIZxN+QM+Du5T4cy/M3pWoOaFI06JVT/kShN myMT22CJGYkByaEAhEeLvQNzn19c5wFDBkqwZUa7IEhqo76pxhEwGEGsetdmOeapDGke a92hm4rC2j5dfM1FSymC4peVyFIKIyp4M2LANvhM8BULMyAinHEDE5KJDYyTz7Y/SYIn EqZQ== X-Gm-Message-State: AHYfb5i5PlfTeFzx6042htMnRxDwzHM4BT25ipE2icuFcQPynlosgvcc Hh2grDG0eVudBzYx X-Received: by 10.28.13.130 with SMTP id 124mr486495wmn.13.1503930572535; Mon, 28 Aug 2017 07:29:32 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:31 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/13] mmc: meson-gx: rework tuning function Date: Mon, 28 Aug 2017 16:29:15 +0200 Message-Id: <20170828142915.27020-14-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework tuning function of the rx phase. Now that the phase can be more precisely set using CCF, test more phase setting and find the largest working window. Then the tuning selected is the one at the center of the window. This rework allows to use new modes, such as UHS SDR50 Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 161 +++++++++++++++++++++++++++------------- 1 file changed, 111 insertions(+), 50 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index efffd36c8d77..987bae98c61f 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_TX_DELAY_MASK GENMASK(19, 16) #define CLK_RX_DELAY_MASK GENMASK(23, 20) #define CLK_DELAY_STEP_PS 200 +#define CLK_PHASE_STEP 30 +#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) #define CLK_ALWAYS_ON BIT(24) #define SD_EMMC_DELAY 0x4 @@ -119,12 +121,6 @@ #define MUX_CLK_NUM_PARENTS 2 -struct meson_tuning_params { - unsigned int core_phase; - unsigned int tx_phase; - unsigned int rx_phase; -}; - struct sd_emmc_desc { u32 cmd_cfg; u32 cmd_arg; @@ -155,7 +151,6 @@ struct meson_host { struct sd_emmc_desc *descs; dma_addr_t descs_dma_addr; - struct meson_tuning_params tp; bool vqmmc_enabled; }; @@ -458,13 +453,6 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } -static void meson_mmc_set_phase_params(struct meson_host *host) -{ - clk_set_phase(host->mmc_clk, host->tp.core_phase); - clk_set_phase(host->tx_clk, host->tp.tx_phase); - clk_set_phase(host->rx_clk, host->tp.rx_phase); -} - /* * The SD/eMMC IP block has an internal mux and divider used for * generating the MMC clock. Use the clock framework to create and @@ -617,18 +605,122 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) return PTR_ERR(host->rx_clk); - /* Set the initial phase parameters */ - meson_mmc_set_phase_params(host); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) return ret; + /* + * Set phases : These values are mostly the datasheet recommended ones + * except for the Tx phase. Datasheet recommends 180 but some cards + * fail at initialisation with it. 270 works just fine, it fixes these + * initialisation issues and enable eMMC DDR52 mode. + */ + clk_set_phase(host->mmc_clk, 180); + clk_set_phase(host->tx_clk, 270); + clk_set_phase(host->rx_clk, 0); + return clk_prepare_enable(host->mmc_clk); } +static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) +{ + DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); + DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); + + /* + * shift the bitmap right and reintroduce the dropped bits on the left + * of the bitmap + */ + bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); + bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, + CLK_PHASE_POINT_NUM); + bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); +} + +static void meson_mmc_find_next_region(unsigned long *map, + unsigned long *start, + unsigned long *stop) +{ + *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); + *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); +} + +static int meson_mmc_find_tuning_point(unsigned long *test) +{ + unsigned long shift, stop, offset = 0, start = 0, size = 0; + + /* Get the all good/all bad situation out the way */ + if (bitmap_full(test, CLK_PHASE_POINT_NUM)) + return 0; /* All points are good so point 0 will do */ + else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) + return -EIO; /* No successful tuning point */ + + /* + * Now we know there is a least one region find. Make sure it does + * not wrap by the shifting the bitmap if necessary + */ + shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); + if (shift != 0) + meson_mmc_shift_map(test, shift); + + while (start < CLK_PHASE_POINT_NUM) { + meson_mmc_find_next_region(test, &start, &stop); + + if ((stop - start) > size) { + offset = start; + size = stop - start; + } + + start = stop; + } + + /* Get the center point of the region */ + offset += (size / 2); + + /* Shift the result back */ + offset = (offset + shift) % CLK_PHASE_POINT_NUM; + + return offset; +} + +static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, + struct clk *clk) +{ + int point, ret; + DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); + + dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", + __clk_get_name(clk)); + bitmap_zero(test, CLK_PHASE_POINT_NUM); + + /* Explore tuning points */ + for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { + clk_set_phase(clk, point * CLK_PHASE_STEP); + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) + set_bit(point, test); + } + + /* Find the optimal tuning point and apply it */ + point = meson_mmc_find_tuning_point(test); + if (point < 0) + return point; /* tuning failed */ + + clk_set_phase(clk, point * CLK_PHASE_STEP); + dev_dbg(mmc_dev(mmc), "success with phase: %d\n", + clk_get_phase(clk)); + return 0; +} + +static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct meson_host *host = mmc_priv(mmc); + + return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -667,6 +759,8 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) host->vqmmc_enabled = true; } + /* Reset rx phase */ + clk_set_phase(host->rx_clk, 0); break; } @@ -989,29 +1083,6 @@ static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) return IRQ_HANDLED; } -static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) -{ - struct meson_host *host = mmc_priv(mmc); - struct meson_tuning_params tp_old = host->tp; - int ret = -EINVAL, i, cmd_error; - - dev_info(mmc_dev(mmc), "(re)tuning...\n"); - - for (i = 0; i < 360; i += 90) { - host->tp.rx_phase = i; - /* exclude the active parameter set if retuning */ - if (!memcmp(&tp_old, &host->tp, sizeof(tp_old)) && - mmc->doing_retune) - continue; - meson_mmc_set_phase_params(host); - ret = mmc_send_tuning(mmc, opcode, &cmd_error); - if (!ret) - break; - } - - return ret; -} - /* * NOTE: we only need this until the GPIO/pinctrl driver can handle * interrupts. For now, the MMC core will use this for polling. @@ -1156,16 +1227,6 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; - /* - * Set phases : These values are mostly the datasheet recommended ones - * except for the Tx phase. Datasheet recommends 180 but some cards - * fail at initialisation with it. 270 works just fine, it fixes these - * initialisation issues and enable eMMC DDR52 mode. - */ - host->tp.core_phase = 180; - host->tp.tx_phase = 270; - host->tp.rx_phase = 0; - ret = meson_mmc_clk_init(host); if (ret) goto err_core_clk;