From patchwork Mon Aug 28 10:53:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 111138 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4661072qge; Mon, 28 Aug 2017 03:54:01 -0700 (PDT) X-Received: by 10.84.129.100 with SMTP id 91mr231309plb.154.1503917641795; Mon, 28 Aug 2017 03:54:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503917641; cv=none; d=google.com; s=arc-20160816; b=WR5Oo7rd2fDSfvtOqSYza7iPOFPIBDHgRU/iI3XzaCfW2ivid6FsQgr3zci98q9Z3k u/fS4oOMi0O9YbrxgtWd6xr8qtgJhOudxKONTVK85e1mxydM8RFjaWhZC+AHF6gBaWNp xXch4W9MgkoVIHklabQzX2b617maE+sQ6WsBf9l8W3vcuJNSYBAy53JDTPAMB0izW997 nDK0+8r1q60C3MXieNVdN+K0H4rN8qsEepe3QbJ0fvAYiuCj5gTi8A8pxMdcJ5DqEV3r a0Xufpa0RWrt4I9lIRUrsKZtdjtikOGvPcWQSpa0m+E3g2n3AgADAJQSwjUaocYHqUpi zCNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=nmVcZ8q9F0uC6v41whaCDEJOe4hxNQejHvizQsNzW7A=; b=hObcJzzgA0JaStwDrJBa+angf1nrnh7B2pSA3QM7tUf3BY+UVChekUHUYa2s0VJAUK gLR/cRjdos9Mswqpx6bx2rczwtsS4Wb1NxYLd+kcjCUtH/yDzYA2OKN1bSJqvEkTbi43 g6gnEn343kMADovf/DRCcVK9Q3jFp1vM/mDZiBjiEJRAqssqJUWLhKej9fovfuy7v+hs PLmf74Py9SU7aJeNl/yNfs/+biI0ezDufHCkqhxkXrisWuxaBnKdG+TNu2wvIMLiGa1Z mkQ/8xX8gu+fTbpvoSvGvSuqa/lRS8i1/pHvxd4Ky3jtaTBJoNB4UFb53AE2cSKb47FT oJxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d15si60753pfj.436.2017.08.28.03.54.01; Mon, 28 Aug 2017 03:54:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751357AbdH1Kx6 (ORCPT + 26 others); Mon, 28 Aug 2017 06:53:58 -0400 Received: from mx2.suse.de ([195.135.220.15]:35079 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751157AbdH1Kx4 (ORCPT ); Mon, 28 Aug 2017 06:53:56 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 6E716AB9D; Mon, 28 Aug 2017 10:53:54 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: interrupt-controller: Add Realtek RTD1295 Date: Mon, 28 Aug 2017 12:53:42 +0200 Message-Id: <20170828105344.8338-2-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170828105344.8338-1-afaerber@suse.de> References: <20170828105344.8338-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for Realtek RTD1295 IRQ mux. Signed-off-by: Andreas Färber --- v1 -> v2: * Dropped reference to common interrupt.txt bindings (Rob) .../interrupt-controller/realtek,rtd119x-mux.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd119x-mux.txt -- 2.12.3 diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd119x-mux.txt b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd119x-mux.txt new file mode 100644 index 000000000000..952e5c54a5fa --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd119x-mux.txt @@ -0,0 +1,23 @@ +Realtek RTD119x/129x IRQ Mux Controller +======================================= + +Required properties: + +- compatible : Should be one of the following: + - "realtek,rtd1295-irq-mux" + - "realtek,rtd1295-iso-irq-mux" +- reg : Specifies base physical address and size of the registers. +- interrupts : Specifies the interrupt line which is mux'ed. +- interrupt-controller : Presence indicates the node as interrupt controller. +- #interrupt-cells : Shall be 1. See common bindings in interrupt.txt. + + +Example: + + interrupt-controller@98007000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x98007000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; From patchwork Mon Aug 28 10:53:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 111140 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp4661897qge; Mon, 28 Aug 2017 03:54:55 -0700 (PDT) X-Received: by 10.84.218.8 with SMTP id q8mr189695pli.115.1503917695425; Mon, 28 Aug 2017 03:54:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503917695; cv=none; d=google.com; s=arc-20160816; b=pDOJTPKG4C+zO/60qKXDl/EuLVrNeMuBcwoX8rUFzKk7ZylBjQ4yCT6KPBrOMPNuQg KwXWaaoAQ7zufvcCUrYfv5V8Cs6+I257CzoSMN/LMHr5YcjTC+BjJ044I0IpQHAkDUG9 RaeffMLqKDe31ud3iOHMHkY/CS52X/fJ9mP4jmUJCOZODjyMd1IZIiumXid5V8ngCyJq FQ6BqgitoxNmFgrF2DRQu5GvyxtpqOAPevSibru45jguBbrrIgbd+tEGgdKf4oMB5IfD xPz2xaRSRgpHUhGSoFQEicEO1Btev791HQ8p0mt0BDravvDs2xpjMf1Pc0vMnnhh+FAR cBIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=PG5UTyKf5BfA8duKQQ16yRgiYYLri7+2UmCZVLrtbxU=; b=gZGaKEWoLE702hIoAjKviLKtMh+m+xuPNHIldKO7piFkS7DCSe+UwHGtSzkXcKxzc6 NOpIZMneRsNaXBhG+W4Z8z6yzem/BzXWNbvWngAVL0n7LB6qUUs454x/OpSCHL3NYASJ CxRkwtygLkN05HR0Yek09vEhKd1CsVGZcaGu6seX4HJgvxBfyDgMrfckKYpuiQTO2vH4 FDlOuBbba0WLmWSslJ1dMsJ0oqJzKDnnWs9ABmU+PaKj6xdeJZZr3gP/4NtUnrmcnrXJ 00GW1hZ561r689lZjnZFKjgSXVYNvle2yDM7sdH1qwP9gWPzVFgJR6EG3a/AtHVFiWUQ /IAg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m65si59341pgm.716.2017.08.28.03.54.54; Mon, 28 Aug 2017 03:54:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751436AbdH1Kyv (ORCPT + 26 others); Mon, 28 Aug 2017 06:54:51 -0400 Received: from mx2.suse.de ([195.135.220.15]:35095 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751170AbdH1Kx4 (ORCPT ); Mon, 28 Aug 2017 06:53:56 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 110CBABFC; Mon, 28 Aug 2017 10:53:55 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH v2 2/3] irqchip: Add Realtek RTD1295 mux driver Date: Mon, 28 Aug 2017 12:53:43 +0200 Message-Id: <20170828105344.8338-3-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170828105344.8338-1-afaerber@suse.de> References: <20170828105344.8338-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This irq mux driver is derived from the RTD1295 vendor DT and assumes a linear mapping between intr_en and intr_status registers. Code for RTD119x indicates this may not always be the case (i2c_3). Based in part on QNAP's arch/arm/mach-rtk119x/rtk_irq_mux.c code. Signed-off-by: Andreas Färber --- v1 -> v2: * Renamed struct fields to avoid ambiguity (Marc) * Refactored offset lookup to avoid per-compatible init functions * Inserted white lines to clarify balanced locking (Marc) * Dropped forwarding of set_affinity to GIC (Marc) * Added spinlocks for consistency (Marc) * Limited initialization quirk to iso mux * Fixed spinlock initialization (Andrew) drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rtd119x-mux.c | 204 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 205 insertions(+) create mode 100644 drivers/irqchip/irq-rtd119x-mux.c -- 2.12.3 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e88d856cc09c..46202a0b7d96 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd119x-mux.o diff --git a/drivers/irqchip/irq-rtd119x-mux.c b/drivers/irqchip/irq-rtd119x-mux.c new file mode 100644 index 000000000000..65d22e163bef --- /dev/null +++ b/drivers/irqchip/irq-rtd119x-mux.c @@ -0,0 +1,204 @@ +/* + * Realtek RTD129x IRQ mux + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct rtd119x_irq_mux_info { + unsigned intr_status_offset; + unsigned intr_en_offset; +}; + +struct rtd119x_irq_mux_data { + void __iomem *intr_status; + void __iomem *intr_en; + int irq; + struct irq_domain *domain; + spinlock_t lock; +}; + +static void rtd119x_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd119x_irq_mux_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 intr_en, intr_status, status; + int ret; + + chained_irq_enter(chip, desc); + + spin_lock(&data->lock); + intr_en = readl(data->intr_en); + intr_status = readl(data->intr_status); + spin_unlock(&data->lock); + + status = intr_status & intr_en; + if (status != 0) { + unsigned irq = __ffs(status); + ret = generic_handle_irq(irq_find_mapping(data->domain, irq)); + if (ret == 0) { + spin_lock(&data->lock); + + intr_status = readl(data->intr_status); + intr_status |= BIT(irq - 1); + writel(intr_status, data->intr_status); + + spin_unlock(&data->lock); + } + } + + chained_irq_exit(chip, desc); +} + +static void rtd119x_mux_mask_irq(struct irq_data *data) +{ + struct rtd119x_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + u32 intr_status; + + spin_lock(&mux_data->lock); + + intr_status = readl(mux_data->intr_status); + intr_status |= BIT(data->hwirq); + writel(intr_status, mux_data->intr_status); + + spin_unlock(&mux_data->lock); +} + +static void rtd119x_mux_unmask_irq(struct irq_data *data) +{ + struct rtd119x_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + u32 intr_en; + + spin_lock(&mux_data->lock); + + intr_en = readl(mux_data->intr_en); + intr_en |= BIT(data->hwirq); + writel(intr_en, mux_data->intr_en); + + spin_unlock(&mux_data->lock); +} + +static int rtd119x_mux_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + /* Forwarding the affinity to the parent would affect all 32 interrupts. */ + return -EINVAL; +} + +static struct irq_chip rtd119x_mux_irq_chip = { + .name = "rtd119x-mux", + .irq_mask = rtd119x_mux_mask_irq, + .irq_unmask = rtd119x_mux_unmask_irq, + .irq_set_affinity = rtd119x_mux_set_affinity, +}; + +static int rtd119x_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd119x_irq_mux_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &rtd119x_mux_irq_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_probe(irq); + + return 0; +} + +static struct irq_domain_ops rtd119x_mux_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = rtd119x_mux_irq_domain_map, +}; + +static const struct rtd119x_irq_mux_info rtd1295_iso_irq_mux_info = { + .intr_status_offset = 0x0, + .intr_en_offset = 0x40, +}; + +static const struct rtd119x_irq_mux_info rtd1295_irq_mux_info = { + .intr_status_offset = 0xc, + .intr_en_offset = 0x80, +}; + +static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1295-iso-irq-mux", + .data = &rtd1295_iso_irq_mux_info, + }, { + .compatible = "realtek,rtd1295-irq-mux", + .data = &rtd1295_irq_mux_info, + }, { + } +}; + +static int __init rtd119x_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + struct rtd119x_irq_mux_data *data; + const struct of_device_id *match; + const struct rtd119x_irq_mux_info *info; + void __iomem *base; + u32 val; + + match = of_match_node(rtd1295_irq_mux_dt_matches, node); + if (!match) + return -EINVAL; + + info = match->data; + if (!info) + return -EINVAL; + + base = of_iomap(node, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->intr_status = base + info->intr_status_offset; + data->intr_en = base + info->intr_en_offset; + + data->irq = irq_of_parse_and_map(node, 0); + if (data->irq <= 0) { + kfree(data); + return -EINVAL; + } + + spin_lock_init(&data->lock); + + data->domain = irq_domain_add_linear(node, 32, + &rtd119x_mux_irq_domain_ops, data); + if (!data->domain) { + kfree(data); + return -ENOMEM; + } + + if (of_device_is_compatible(node, "realtek,rtd1295-iso-irq-mux")) { + const int uart0_irq = 2; + + spin_lock(&data->lock); + + val = readl(data->intr_en); + val &= ~BIT(uart0_irq); + writel(val, data->intr_en); + + writel(BIT(uart0_irq), data->intr_status); + + spin_unlock(&data->lock); + } + + irq_set_chained_handler_and_data(data->irq, rtd119x_mux_irq_handle, data); + + return 0; +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd119x_irq_mux_init); +IRQCHIP_DECLARE(rtd1295_mux, "realtek,rtd1295-irq-mux", rtd119x_irq_mux_init);