From patchwork Fri Jan 3 08:18:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 206226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71A21C32771 for ; Fri, 3 Jan 2020 08:18:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 497C722314 for ; Fri, 3 Jan 2020 08:18:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="TMVO19DT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727447AbgACISX (ORCPT ); Fri, 3 Jan 2020 03:18:23 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17279 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726054AbgACISW (ORCPT ); Fri, 3 Jan 2020 03:18:22 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:17:38 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:22 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:22 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:21 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:21 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Jan 2020 00:18:20 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 1/5] phy: tegra: xusb: Protect Tegra186 soc with config Date: Fri, 3 Jan 2020 16:18:10 +0800 Message-ID: <20200103081814.9848-2-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039458; bh=jtzhgmOSyLlj7voWgVZkhzmevHlkmril+TYqeYqIUAw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=TMVO19DT564EdqdoqBGJfRsE12O2RpJgoAXKOYjwWpjLSM56xjVFXPo6mzcowRGif UoHGSvWygjFgGmKugqYSzPlEUOXwNlrgkKOFehk1GCzquqVXbQnC/+AUCNBaInqDid ukwONRHGhD+Y49e/WYD9oV0f1YnEz5/ftBHnVoNgnfc2GeHapohr54nLZ/yvDW/z71 Vvw4gjXAysMUuUNn807fnDEnsfo/fdS3rZH+wNb+A1gr3PJZWHKpSzpSS0PP4eYXOW wTP6vCplSLSe2sgLfwEPEUpa/ORstOJ6hO72Pj2g7DGAXGYRmX/ia8dVJcv/qTPv9G xH9xwe9vnaqKw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As xusb-tegra186.c will be reused for Tegra194, it would be good to protect Tegra186 soc data with CONFIG_ARCH_TEGRA_186_SOC. This commit also reshuffles Tegra186 soc data single CONFIG_ARCH_TEGRA_186_SOC will be sufficient. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- Changes in v5: none Changes in v4: none Changes in v3: none Changes in v2: - new patch to protect Tegra186 soc data with config drivers/phy/tegra/xusb-tegra186.c | 70 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 84c27394c181..01f7d979c9a8 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -503,19 +503,6 @@ static const char * const tegra186_usb2_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { - TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), - TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), - TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { - .name = "usb2", - .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), - .lanes = tegra186_usb2_lanes, - .ops = &tegra186_usb2_pad_ops, -}; - static int tegra186_usb2_port_enable(struct tegra_xusb_port *port) { return 0; @@ -765,27 +752,6 @@ static const char * const tegra186_usb3_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { - TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), - TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), - TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { - .name = "usb3", - .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), - .lanes = tegra186_usb3_lanes, - .ops = &tegra186_usb3_pad_ops, -}; - -static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { - &tegra186_usb2_pad, - &tegra186_usb3_pad, -#if 0 /* TODO implement */ - &tegra186_hsic_pad, -#endif -}; - static int tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) { @@ -885,6 +851,7 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .vbus_override = tegra186_xusb_padctl_vbus_override, }; +#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) static const char * const tegra186_xusb_padctl_supply_names[] = { "avdd-pll-erefeut", "avdd-usb", @@ -892,6 +859,40 @@ static const char * const tegra186_xusb_padctl_supply_names[] = { "vddio-hsic", }; +static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { + TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { + .name = "usb2", + .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), + .lanes = tegra186_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { + TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { + .name = "usb3", + .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), + .lanes = tegra186_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { + &tegra186_usb2_pad, + &tegra186_usb3_pad, +#if 0 /* TODO implement */ + &tegra186_hsic_pad, +#endif +}; + const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_pads = ARRAY_SIZE(tegra186_pads), .pads = tegra186_pads, @@ -916,6 +917,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), }; EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); +#endif MODULE_AUTHOR("JC Kuo "); MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); From patchwork Fri Jan 3 08:18:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 206227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81B0CC32767 for ; Fri, 3 Jan 2020 08:18:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53F5D22B48 for ; Fri, 3 Jan 2020 08:18:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="c7rQivYZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727488AbgACISh (ORCPT ); Fri, 3 Jan 2020 03:18:37 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17291 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726295AbgACISb (ORCPT ); Fri, 3 Jan 2020 03:18:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 00:17:47 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 00:18:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 00:18:30 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 08:18:30 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 08:18:30 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.108.118]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Jan 2020 00:18:29 -0800 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v5 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board Date: Fri, 3 Jan 2020 16:18:14 +0800 Message-ID: <20200103081814.9848-6-jckuo@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200103081814.9848-1-jckuo@nvidia.com> References: <20200103081814.9848-1-jckuo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578039467; bh=HFCFVfUkHlCBFcm+mlAAgYHn7YBPtjgDr4lQB1CTZcw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=c7rQivYZa+VBoaZTJTfKUIU5r4NIWxXDCZ1jzkLX4H7tz0eLb3toVyTcTPKa/bll0 wBXAFEtQp/O2S7UjylZ7HDfx0lLcmLk/du5V+aGFjXOiDU6j/kqBFJBRtRWpuhloOx odULfqHugoVkI3LFm9+1Tz4s4mNDb8OhbsMLElOcjsUOhqOPPg5h2qFj/7Ja9pxzSV 2+fFsgg/7GEuisXGKEPWwllLftyGWv0/gn4CZtwUa0k7izYoByDb1Fm4hriPpoE1Z1 nCeIc9Amg30z4C+GNXhYHIPKyV4JYoAFrriCYiGZ8SI5HNZ6KU9RwKJBJ8mD/UoBxU PwbIcciaHh2hQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board. Signed-off-by: JC Kuo --- Changes in v5: none Changes in v4: none Changes in v3: none Changes in v2: - use capitalization of regulator names - fix gpio property of VDD_5V_SATA regulator .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 63 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c7f2a20e6b02..014e18b2d52a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -67,6 +67,29 @@ vmmc-supply = <&vdd_emmc_3v3>; }; + padctl@3520000 { + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + ports { + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -230,7 +253,7 @@ regulator-max-microvolt = <3300000>; }; - ldo5 { + vdd_usb_3v3: ldo5 { regulator-name = "VDD_USB_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -313,5 +336,16 @@ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; regulator-boot-on; }; + + vdd_5v_sata: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + + regulator-name = "VDD_5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 353a6a22196d..2cbcae39d1b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -37,6 +37,69 @@ status = "okay"; }; + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-1 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-3 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-1 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + usb3-3 { + nvidia,usb2-companion = <3>; + nvidia,disable-gen2; + status = "okay"; + }; + }; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; + phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3"; + }; + pwm@c340000 { status = "okay"; };