From patchwork Sun Jan 5 10:45:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75082C3F68F for ; Sun, 5 Jan 2020 10:46:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C6DF24650 for ; Sun, 5 Jan 2020 10:46:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Ww6JLIeo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726494AbgAEKqk (ORCPT ); Sun, 5 Jan 2020 05:46:40 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:2590 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726360AbgAEKqi (ORCPT ); Sun, 5 Jan 2020 05:46:38 -0500 X-UUID: 5338576dd763456d810138b6743bd429-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WZ/umlXOyPHUYCRi2U9EvlX0wVfU8S8+Ftnq58VNe5M=; b=Ww6JLIeodifH780mh1kn6g0ShhkKaZ9N7wOg/1n6rCumMsiSmbUd3ApICeVbbTevMGEg28fnWlszyfZ26PZmDx/2p4VFJHoUk5xpKsicHNgXB9Pm9CZiTtHHqeotjqAdqQIgXvF7Qr2jWjChlCJoZeIgUJs860ClYWI448JGoWs=; X-UUID: 5338576dd763456d810138b6743bd429-20200105 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 866995537; Sun, 05 Jan 2020 18:46:31 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:05 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:01 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 02/19] iommu/mediatek: Add m4u1_mask to distinguish m4u_id Date: Sun, 5 Jan 2020 18:45:06 +0800 Message-ID: <20200105104523.31006-3-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For some platforms(ex: later mt6779), it maybe have two IOMMUs, so we can add m4u_mask variable to distinguish it by different smi_larb id Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 3 +++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 5 insertions(+) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 6fc1f5ecf91e..09192edef1f7 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -678,6 +678,9 @@ static int mtk_iommu_probe(struct platform_device *pdev) } data->larb_imu[id].dev = &plarbdev->dev; + if (data->plat_data->m4u1_mask == (1 << id)) + data->m4u_id = 1; + component_match_add_release(dev, &match, release_of, compare_of, larbnode); } diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index ea949a324e33..b4bd76548615 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -42,6 +42,7 @@ struct mtk_iommu_plat_data { bool has_bclk; bool has_vld_pa_rng; bool reset_axi; + u32 m4u1_mask; unsigned char larbid_remap[MTK_LARB_NR_MAX]; }; @@ -59,6 +60,7 @@ struct mtk_iommu_data { bool enable_4GB; spinlock_t tlb_lock; /* lock for tlb range flush */ + u32 m4u_id; struct iommu_device iommu; const struct mtk_iommu_plat_data *plat_data; From patchwork Sun Jan 5 10:45:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F5A8C33C8C for ; Sun, 5 Jan 2020 10:46:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E6BC6207FD for ; Sun, 5 Jan 2020 10:46:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VgznuY2l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726376AbgAEKqg (ORCPT ); Sun, 5 Jan 2020 05:46:36 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:42482 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725897AbgAEKqg (ORCPT ); Sun, 5 Jan 2020 05:46:36 -0500 X-UUID: 203e6e9241554a088f4db1757d32f1b7-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5wwx9zI1tNRihK2T3I1D2qJUFCK1MtGL2mDXTtoZpp8=; b=VgznuY2lEDk/TQh0Moc4gZ6TFqXdF9AB69olMhdi0x8V5gILcVQIxenSJOSV/W/Jw1GoivQ25cIO57D/fiGTynCFP4SK0HidvqtAncp9auIfGpeZSefLTl6bSZQpTRQSail3nNVhNFodftubJR+GpsQawUXYBIknsxopjSzfpZA=; X-UUID: 203e6e9241554a088f4db1757d32f1b7-20200105 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 387808072; Sun, 05 Jan 2020 18:46:33 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:06 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:03 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 03/19] iommu/mediatek: Extend larb_remap to larb_remap[2] Date: Sun, 5 Jan 2020 18:45:07 +0800 Message-ID: <20200105104523.31006-4-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For more than one IOMMUs, they are corresponding to different smi_larb id, so we need to extend larb_remap to larb_remap[2] to distinguish it by index. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 8 ++++---- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 09192edef1f7..f2d953fc09df 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -245,7 +245,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_larb = F_MMU_INT_ID_LARB_ID(regval); fault_port = F_MMU_INT_ID_PORT_ID(regval); - fault_larb = data->plat_data->larbid_remap[fault_larb]; + fault_larb = data->plat_data->larbid_remap[data->m4u_id][fault_larb]; if (report_iommu_fault(&dom->domain, data->dev, fault_iova, write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { @@ -782,7 +782,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .has_4gb_mode = true, .has_bclk = true, .has_vld_pa_rng = true, - .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, + .larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, }; static const struct mtk_iommu_plat_data mt8173_data = { @@ -790,13 +790,13 @@ static const struct mtk_iommu_plat_data mt8173_data = { .has_4gb_mode = true, .has_bclk = true, .reset_axi = true, - .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ + .larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ }; static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, .reset_axi = true, - .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, + .larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1}, }; static const struct of_device_id mtk_iommu_of_ids[] = { diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index b4bd76548615..c585811a957c 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -43,7 +43,7 @@ struct mtk_iommu_plat_data { bool has_vld_pa_rng; bool reset_axi; u32 m4u1_mask; - unsigned char larbid_remap[MTK_LARB_NR_MAX]; + unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; }; struct mtk_iommu_domain; From patchwork Sun Jan 5 10:45:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12CFBC33C99 for ; Sun, 5 Jan 2020 10:46:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DDEE92465E for ; Sun, 5 Jan 2020 10:46:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="pFdgz2uZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726773AbgAEKqx (ORCPT ); Sun, 5 Jan 2020 05:46:53 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:24609 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726702AbgAEKqv (ORCPT ); Sun, 5 Jan 2020 05:46:51 -0500 X-UUID: e2bc8ee6dc254265b5b1e3f3b70a7945-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DGmQNidlzNQc5LwY8YiBP+cNsBp8IGVfEGVlTvoknPc=; b=pFdgz2uZ7V1zo4Yv/x7kvKtd2o4M60g9bGE8U5fdzYIpObJ/yx9XExN8aKYXv8aL5WOiGI/eKPVswIAOKYqTKaiDaWgKYUsIG6HGZ/j9eYSTzngXFzg+aOU7pq6FdEX038OEPLwM15tbgreK731chEcqvWTtwqe4HVTUiP3lWbg=; X-UUID: e2bc8ee6dc254265b5b1e3f3b70a7945-20200105 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 103566578; Sun, 05 Jan 2020 18:46:47 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:22 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:17 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779 Date: Sun, 5 Jan 2020 18:45:11 +0800 Message-ID: <20200105104523.31006-8-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When some platforms(ex:later mt6779) define has_wr_len variable, we need to set REG_MMU_WR_LEN to improve performance. So we add REG_MMU_WR_LEN register define in this patch. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 11 +++++++++++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 13 insertions(+) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5de13ab1094e..ad5690350d6a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -44,6 +44,8 @@ #define REG_MMU_MISC_CTRL 0x048 #define REG_MMU_DCM_DIS 0x050 +#define REG_MMU_WR_LEN 0x054 +#define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21)) #define REG_MMU_CTRL_REG 0x110 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) @@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); + if (data->plat_data->has_wr_len) { + /* write command throttling mode */ + regval = readl_relaxed(data->base + REG_MMU_WR_LEN); + regval &= ~F_MMU_WR_THROT_DIS; + writel_relaxed(regval, data->base + REG_MMU_WR_LEN); + } + if (data->plat_data->reset_axi) writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); @@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) struct mtk_iommu_suspend_reg *reg = &data->reg; void __iomem *base = data->base; + reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN); reg->standard_axi_mode = readl_relaxed(base + REG_MMU_MISC_CTRL); reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); @@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); return ret; } + writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN); writel_relaxed(reg->standard_axi_mode, base + REG_MMU_MISC_CTRL); writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index d4495230c6e7..0623f199e96f 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg { u32 int_main_control; u32 ivrp_paddr; u32 vld_pa_rng; + u32 wr_len; }; enum mtk_iommu_plat { @@ -43,6 +44,7 @@ struct mtk_iommu_plat_data { bool has_sub_comm[2]; bool has_vld_pa_rng; bool reset_axi; + bool has_wr_len; u32 m4u1_mask; u32 inv_sel_reg; unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; From patchwork Sun Jan 5 10:45:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 868E1C33C8C for ; Sun, 5 Jan 2020 10:47:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 53CAC24670 for ; Sun, 5 Jan 2020 10:47:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="TApoU0iC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726825AbgAEKrA (ORCPT ); Sun, 5 Jan 2020 05:47:00 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:45267 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726702AbgAEKrA (ORCPT ); Sun, 5 Jan 2020 05:47:00 -0500 X-UUID: 6eaec5b78ff743c7a5739bf46bdbf14d-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=i7uLllswA+30E+RlRxklVQ9qjW8u1U7i80NDkyo2BmA=; b=TApoU0iCwDPxxO2bBTwOI46pa/3ERznmGwWAXFONM8AR1U4R3mFh0OX4JHiWguVH8LfO1NA1sF3Bi9HFVa6n9ANHVJcZiKewPhVQv1B8KrjMvh+zBwXsAnf4mL7OwHfQBHS+MVNnByPV6wSfQfKvMmBOt1uta7Fgterx2AF31tk=; X-UUID: 6eaec5b78ff743c7a5739bf46bdbf14d-20200105 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 508016898; Sun, 05 Jan 2020 18:46:55 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:28 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:20 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 08/19] iommu/mediatek: Add mt6779 basic support Date: Sun, 5 Jan 2020 18:45:12 +0800 Message-ID: <20200105104523.31006-9-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1. Add mt6779_data define to support mt6779 IOMMU HW init. 2. For mt6779, there are two IOMMUs, one is MM_IOMMU, the other is VPU_IOMMU. MM_IOMMU is connected smi_larb to support multimedia engine to access DRAM, and VPU_IOMMU is connected to APU_bus to support VPU,MDLA,EDMA to access DRAM. MM_IOMMU and VPU_IOMMU use the same page table to simplify design by "mtk_iommu_get_m4u_data". 3. For smi_larb6, it doesn't use MM_IOMMU, so we can distinguish VPU_IOMMU by it when excutes iommu_probe. 4. For mt6779 APU_IOMMU fault id is irregular, so it was treated specially. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 46 ++++++++++++++++++++++++++++++++++----- drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 42 insertions(+), 6 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index ad5690350d6a..7829d1fd08dd 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -43,7 +43,10 @@ #define F_INVLD_EN1 BIT(1) #define REG_MMU_MISC_CTRL 0x048 +#define REG_MMU_STANDARD_AXI_MODE_MT6779 (BIT(3) | BIT(19)) + #define REG_MMU_DCM_DIS 0x050 + #define REG_MMU_WR_LEN 0x054 #define F_MMU_WR_THROT_DIS (BIT(5) | BIT(21)) @@ -95,8 +98,10 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define F_MMU_INT_ID_COMM_APU_ID(a) ((a) & 0x3) +#define F_MMU_INT_ID_SUB_APU_ID(a) (((a) >> 2) & 0x3) -#define MTK_PROTECT_PA_ALIGN 128 +#define MTK_PROTECT_PA_ALIGN 256 /* * Get the local arbiter ID and the portid within the larb arbiter @@ -249,8 +254,15 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; fault_port = F_MMU_INT_ID_PORT_ID(regval); if (data->plat_data->has_sub_comm[data->m4u_id]) { - fault_larb = F_MMU_INT_ID_COMM_ID(regval); - sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); + /* m4u1 is VPU in mt6779.*/ + if (data->m4u_id && data->plat_data->m4u_plat == M4U_MT6779) { + fault_larb = F_MMU_INT_ID_COMM_APU_ID(regval); + sub_comm = F_MMU_INT_ID_SUB_APU_ID(regval); + fault_port = 0; /* for mt6779 APU ID is irregular */ + } else { + fault_larb = F_MMU_INT_ID_COMM_ID(regval); + sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); + } } else { fault_larb = F_MMU_INT_ID_LARB_ID(regval); } @@ -556,11 +568,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) return ret; } + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); if (data->plat_data->m4u_plat == M4U_MT8173) - regval = F_MMU_PREFETCH_RT_REPLACE_MOD | + regval |= F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; else - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval = F_L2_MULIT_HIT_EN | @@ -604,8 +617,16 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) writel_relaxed(regval, data->base + REG_MMU_WR_LEN); } - if (data->plat_data->reset_axi) + if (data->plat_data->has_misc_ctrl[data->m4u_id]) { + /* special settings for mmu0 (multimedia iommu) */ + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); + /* non-standard AXI mode */ + regval &= ~REG_MMU_STANDARD_AXI_MODE_MT6779; + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); + } else if (data->plat_data->reset_axi) { + /*disable standard axi when it is REG_MMU_STANDARD_AXI_MODE */ writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); + } if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, dev_name(data->dev), (void *)data)) { @@ -806,6 +827,18 @@ static const struct mtk_iommu_plat_data mt2712_data = { .inv_sel_reg = REG_MMU_INV_SEL, }; +static const struct mtk_iommu_plat_data mt6779_data = { + .m4u_plat = M4U_MT6779, + .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, + /* vp6a, vp6b, mdla/core2, mdla/edmc*/ + .larbid_remap[1] = {2, 0, 3, 1}, + .has_sub_comm = {true, true}, + .has_wr_len = true, + .has_misc_ctrl = {true, false}, + .inv_sel_reg = REG_MMU_INV_SEL_MT6779, + .m4u1_mask = BIT(6), +}; + static const struct mtk_iommu_plat_data mt8173_data = { .m4u_plat = M4U_MT8173, .has_4gb_mode = true, @@ -824,6 +857,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, + { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, {} diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 0623f199e96f..2b207dcadd06 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg { enum mtk_iommu_plat { M4U_MT2701, M4U_MT2712, + M4U_MT6779, M4U_MT8173, M4U_MT8183, }; @@ -45,6 +46,7 @@ struct mtk_iommu_plat_data { bool has_vld_pa_rng; bool reset_axi; bool has_wr_len; + bool has_misc_ctrl[2]; u32 m4u1_mask; u32 inv_sel_reg; unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; From patchwork Sun Jan 5 10:45:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 094F9C33C8C for ; Sun, 5 Jan 2020 10:47:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA6C620866 for ; Sun, 5 Jan 2020 10:47:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qLOUeExA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726912AbgAEKrF (ORCPT ); Sun, 5 Jan 2020 05:47:05 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:50601 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726820AbgAEKrE (ORCPT ); Sun, 5 Jan 2020 05:47:04 -0500 X-UUID: 956b424299534f9d9808071009038d3d-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RY4rn8CmqW4ONHcTdtNSN9a7ZN574snyp8h6PCSTtUE=; b=qLOUeExAXd+yK9T1kacJqisI5jLs+u3zP3Xsf+M2opY8PucXx9hMvgO26ts5OlpX9umQfVcYT3NPCaFr7OQvaoxbzgdmVYlWfxJPEt4HHSLGPQLmgKh/l/QAcgw00eHi88mOmytnQekujfHGlFyRp7lAwCSbE1ck0FzT3dl6Z+c=; X-UUID: 956b424299534f9d9808071009038d3d-20200105 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1787353791; Sun, 05 Jan 2020 18:46:57 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:32 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:27 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 09/19] iommu/mediatek: Add mtk_iommu_pgtable structure Date: Sun, 5 Jan 2020 18:45:13 +0800 Message-ID: <20200105104523.31006-10-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Start with this patch, we will change the SW architecture to support multiple domains. SW architecture will has a big change, so we need to modify a little bit by more than one patch. The new SW overall architecture is as below: iommu0 iommu1 | | ----------- | mtk_iommu_pgtable | ------------------------------------------ | | | mtk_iommu_domain1 mtk_iommu_domain2 mtk_iommu_domain3 | | | iommu_group1 iommu_group2 iommu_group3 | | | iommu_domain1 iommu_domain2 iommu_domain3 | | | iova region1(normal) iova region2(CCU) iova region3(VPU) For current structure, no matter how many iommus there are, they use the same page table to simplify the usage of module. In order to make the software architecture more explicit, this patch will create a global mtk_iommu_pgtable structure to describe page table and all the iommus use it. The diagram is as below: mtk_iommu_data1(MM) mtk_iommu_data2(APU) | | | | ------mtk_iommu_pgtable----- We need to create global mtk_iommu_pgtable to include all the iova regions firstly and special iova regions by divided based on it, so the information of pgtable needs to be created in device_group. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 84 +++++++++++++++++++++++++++++++++++++++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 85 insertions(+) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7829d1fd08dd..50c6a01eb517 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -117,6 +117,12 @@ struct mtk_iommu_domain { struct iommu_domain domain; }; +struct mtk_iommu_pgtable { + struct io_pgtable_cfg cfg; + struct io_pgtable_ops *iop; +}; + +static struct mtk_iommu_pgtable *share_pgtable; static const struct iommu_ops mtk_iommu_ops; /* @@ -164,6 +170,11 @@ static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) return NULL; } +static struct mtk_iommu_pgtable *mtk_iommu_get_pgtable(void) +{ + return share_pgtable; +} + static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) { return container_of(dom, struct mtk_iommu_domain, domain); @@ -316,6 +327,13 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) { struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + if (data->pgtable) { + dom->cfg = data->pgtable->cfg; + dom->iop = data->pgtable->iop; + dom->domain.pgsize_bitmap = data->pgtable->cfg.pgsize_bitmap; + return 0; + } + dom->cfg = (struct io_pgtable_cfg) { .quirks = IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_PERMS | @@ -339,6 +357,61 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) return 0; } +static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data) +{ + struct mtk_iommu_pgtable *pgtable; + + pgtable = kzalloc(sizeof(*pgtable), GFP_KERNEL); + if (!pgtable) + return ERR_PTR(-ENOMEM); + + pgtable->cfg = (struct io_pgtable_cfg) { + .quirks = IO_PGTABLE_QUIRK_ARM_NS | + IO_PGTABLE_QUIRK_NO_PERMS | + IO_PGTABLE_QUIRK_TLBI_ON_MAP | + IO_PGTABLE_QUIRK_ARM_MTK_EXT, + .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, + .ias = 32, + .oas = 34, + .tlb = &mtk_iommu_flush_ops, + .iommu_dev = data->dev, + }; + + pgtable->iop = alloc_io_pgtable_ops(ARM_V7S, &pgtable->cfg, data); + if (!pgtable->iop) { + dev_err(data->dev, "Failed to alloc io pgtable\n"); + return ERR_PTR(-EINVAL); + } + + dev_info(data->dev, "%s create pgtable done\n", __func__); + + return pgtable; +} + +static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data, + struct device *dev) +{ + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); + + /* create share pgtable */ + if (!pgtable) { + pgtable = create_pgtable(data); + if (IS_ERR(pgtable)) { + dev_err(data->dev, "Failed to create pgtable\n"); + return -ENOMEM; + } + + share_pgtable = pgtable; + } + + /* binding to pgtable */ + data->pgtable = pgtable; + + dev_info(data->dev, "m4u%d attach_pgtable done!\n", data->m4u_id); + + return 0; +} + static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) { struct mtk_iommu_domain *dom; @@ -502,10 +575,21 @@ static void mtk_iommu_remove_device(struct device *dev) static struct iommu_group *mtk_iommu_device_group(struct device *dev) { struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_pgtable *pgtable; + int ret = 0; if (!data) return ERR_PTR(-ENODEV); + pgtable = data->pgtable; + if (!pgtable) { + ret = mtk_iommu_attach_pgtable(data, dev); + if (ret) { + dev_err(data->dev, "Failed to device_group\n"); + return NULL; + } + } + /* All the client devices are in the same m4u iommu-group */ if (!data->m4u_group) { data->m4u_group = iommu_group_alloc(); diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 2b207dcadd06..a3c598f99ed5 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -61,6 +61,7 @@ struct mtk_iommu_data { struct clk *bclk; phys_addr_t protect_base; /* protect memory base */ struct mtk_iommu_suspend_reg reg; + struct mtk_iommu_pgtable *pgtable; struct mtk_iommu_domain *m4u_dom; struct iommu_group *m4u_group; bool enable_4GB; From patchwork Sun Jan 5 10:45:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6061BC33C8C for ; Sun, 5 Jan 2020 10:47:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3571E21775 for ; Sun, 5 Jan 2020 10:47:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Hmv/NN7D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726955AbgAEKrH (ORCPT ); Sun, 5 Jan 2020 05:47:07 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:32062 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726702AbgAEKrG (ORCPT ); Sun, 5 Jan 2020 05:47:06 -0500 X-UUID: 07f00fd078c34ac68ce2c55ac1e2529d-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TnjVeJwcbvQSB0jZ1PBholvwkjk3w09NdGN4BC3AJAw=; b=Hmv/NN7D8PjriN6jrcKvYf4YXOEUgjQVL0MWl4qoKl6IbktWbKdTKkGtm+DI2TVBy6oCfTHnqCYJVzKEiM38srAddUQjSCWcRJvpUYea7RN/GDC4xvQeM4Gbf9LBmkZ5IHhbKor92s0ExxtCoKKaA11diISLH4djY4rKl3tvfl8=; X-UUID: 07f00fd078c34ac68ce2c55ac1e2529d-20200105 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1400420485; Sun, 05 Jan 2020 18:47:00 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:35 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:30 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 10/19] iommu/mediatek: Remove mtk_iommu_domain_finalise Date: Sun, 5 Jan 2020 18:45:14 +0800 Message-ID: <20200105104523.31006-11-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We already have global mtk_iommu_pgtable structure to describe page table and create it in group_device, "mtk_iommu_domain_finalise" is as the same as that, so so we will remove mtk_iommu_domain_finalise. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 48 ++++++++------------------------------- 1 file changed, 10 insertions(+), 38 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 50c6a01eb517..cfefdd638f1a 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -323,40 +323,6 @@ static void mtk_iommu_config(struct mtk_iommu_data *data, } } -static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) -{ - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); - - if (data->pgtable) { - dom->cfg = data->pgtable->cfg; - dom->iop = data->pgtable->iop; - dom->domain.pgsize_bitmap = data->pgtable->cfg.pgsize_bitmap; - return 0; - } - - dom->cfg = (struct io_pgtable_cfg) { - .quirks = IO_PGTABLE_QUIRK_ARM_NS | - IO_PGTABLE_QUIRK_NO_PERMS | - IO_PGTABLE_QUIRK_TLBI_ON_MAP | - IO_PGTABLE_QUIRK_ARM_MTK_EXT, - .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, - .ias = 32, - .oas = 34, - .tlb = &mtk_iommu_flush_ops, - .iommu_dev = data->dev, - }; - - dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); - if (!dom->iop) { - dev_err(data->dev, "Failed to alloc io pgtable\n"); - return -EINVAL; - } - - /* Update our support page sizes bitmap */ - dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; - return 0; -} - static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data) { struct mtk_iommu_pgtable *pgtable; @@ -414,11 +380,17 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data, static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) { + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); struct mtk_iommu_domain *dom; if (type != IOMMU_DOMAIN_DMA) return NULL; + if (!pgtable) { + pr_err("%s, pgtable is not ready\n", __func__); + return NULL; + } + dom = kzalloc(sizeof(*dom), GFP_KERNEL); if (!dom) return NULL; @@ -426,8 +398,10 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) if (iommu_get_dma_cookie(&dom->domain)) goto free_dom; - if (mtk_iommu_domain_finalise(dom)) - goto put_dma_cookie; + dom->cfg = pgtable->cfg; + dom->iop = pgtable->iop; + /* Update our support page sizes bitmap */ + dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap; dom->domain.geometry.aperture_start = 0; dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); @@ -435,8 +409,6 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) return &dom->domain; -put_dma_cookie: - iommu_put_dma_cookie(&dom->domain); free_dom: kfree(dom); return NULL; From patchwork Sun Jan 5 10:45:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BC64C33C8C for ; Sun, 5 Jan 2020 10:47:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C96F920866 for ; Sun, 5 Jan 2020 10:47:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YGljSC8q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727200AbgAEKrj (ORCPT ); Sun, 5 Jan 2020 05:47:39 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:23490 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726376AbgAEKrI (ORCPT ); Sun, 5 Jan 2020 05:47:08 -0500 X-UUID: ed6921aaaf3e44569e2117d59d61f7c9-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wzv+DS2QU8JGS/oClDBJUbQzay4lYYCHyz03iNL5uvs=; b=YGljSC8q8V0BRi4imizn3RnSB2cTy4/hf4KslC+BzSMYe9Bq3Dm7MT9BxXOJsIOMDSEgOTCRcASbPKJiJby67h+sBectUDNtxlxaRxWxJ3FrNS653qkxaWlt9BM1pcPclGg++ZQEDIyC/0Vwxu+NwiDqkVZAi9Ofnh9PK8bj5/c=; X-UUID: ed6921aaaf3e44569e2117d59d61f7c9-20200105 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1008748616; Sun, 05 Jan 2020 18:47:02 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:35 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:32 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 11/19] iommu/mediatek: Remove pgtable info in mtk_iommu_domain Date: Sun, 5 Jan 2020 18:45:15 +0800 Message-ID: <20200105104523.31006-12-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch will use mtk_iommu_pgtable to replace the part of pgtable in mtk_iommu_domain, so we can remove the information of pgtable in mtk_iommu_domain. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index cfefdd638f1a..b34bd3abccf8 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -111,9 +111,6 @@ #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) struct mtk_iommu_domain { - struct io_pgtable_cfg cfg; - struct io_pgtable_ops *iop; - struct iommu_domain domain; }; @@ -373,6 +370,10 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data, /* binding to pgtable */ data->pgtable = pgtable; + /* update HW settings */ + writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, + data->base + REG_MMU_PT_BASE_ADDR); + dev_info(data->dev, "m4u%d attach_pgtable done!\n", data->m4u_id); return 0; @@ -398,8 +399,6 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) if (iommu_get_dma_cookie(&dom->domain)) goto free_dom; - dom->cfg = pgtable->cfg; - dom->iop = pgtable->iop; /* Update our support page sizes bitmap */ dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap; @@ -416,11 +415,12 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) static void mtk_iommu_domain_free(struct iommu_domain *domain) { - struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); - free_io_pgtable_ops(dom->iop); iommu_put_dma_cookie(domain); kfree(to_mtk_domain(domain)); + free_io_pgtable_ops(pgtable->iop); + kfree(pgtable); } static int mtk_iommu_attach_device(struct iommu_domain *domain, @@ -433,11 +433,8 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, return -ENODEV; /* Update the pgtable base address register of the M4U HW */ - if (!data->m4u_dom) { + if (!data->m4u_dom) data->m4u_dom = dom; - writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, - data->base + REG_MMU_PT_BASE_ADDR); - } mtk_iommu_config(data, dev, true); return 0; @@ -457,7 +454,7 @@ static void mtk_iommu_detach_device(struct iommu_domain *domain, static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot, gfp_t gfp) { - struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ @@ -465,16 +462,16 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, paddr |= BIT_ULL(32); /* Synchronize with the tlb_lock */ - return dom->iop->map(dom->iop, iova, paddr, size, prot); + return pgtable->iop->map(pgtable->iop, iova, paddr, size, prot); } static size_t mtk_iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size, struct iommu_iotlb_gather *gather) { - struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); - return dom->iop->unmap(dom->iop, iova, size, gather); + return pgtable->iop->unmap(pgtable->iop, iova, size, gather); } static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) @@ -498,11 +495,11 @@ static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { - struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); phys_addr_t pa; - pa = dom->iop->iova_to_phys(dom->iop, iova); + pa = pgtable->iop->iova_to_phys(pgtable->iop, iova); if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) pa &= ~BIT_ULL(32); @@ -845,8 +842,8 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev) static int __maybe_unused mtk_iommu_resume(struct device *dev) { struct mtk_iommu_data *data = dev_get_drvdata(dev); + struct mtk_iommu_pgtable *pgtable = data->pgtable; struct mtk_iommu_suspend_reg *reg = &data->reg; - struct mtk_iommu_domain *m4u_dom = data->m4u_dom; void __iomem *base = data->base; int ret; @@ -864,8 +861,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); - if (m4u_dom) - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, + if (pgtable) + writel(pgtable->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); return 0; } From patchwork Sun Jan 5 10:45:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC482C33C9B for ; Sun, 5 Jan 2020 10:47:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B3EF721775 for ; Sun, 5 Jan 2020 10:47:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MqMWF4yq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727103AbgAEKrO (ORCPT ); Sun, 5 Jan 2020 05:47:14 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:12685 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727025AbgAEKrO (ORCPT ); Sun, 5 Jan 2020 05:47:14 -0500 X-UUID: 5bf3b63f330444bfa9e261eede22e1b7-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BU3FHHq8lyI4GErrRVuqeiEhzwtLbu5dCFfMXEQDW1k=; b=MqMWF4yqiWhgMsbK53C3+P3W1eBxvElV/CXXkEw03l+esiqkv78SUOxUtGSxx1c0RViWO/gGPSAYam1uJPrfxgplbmxWpcPe07/O5JBfuGlaqZFrk3LU5PD/ViMpYAMQkeIdFIQZeCFyBOy6769EvpwkIQSfG3AJTfsKGdtDlcU=; X-UUID: 5bf3b63f330444bfa9e261eede22e1b7-20200105 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1428780349; Sun, 05 Jan 2020 18:47:10 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:44 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:40 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 14/19] iommu/mediatek: Add mtk_domain_data structure Date: Sun, 5 Jan 2020 18:45:18 +0800 Message-ID: <20200105104523.31006-15-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mtk_domain_data structure to describe how many iova regions there are and the relevant the start and end address of each iova region. The number of iova region is equal to the number of mtk_iommu_domain. So we will use mtk_domain_data to initialize the start and end iova of mtk_iommu_domain. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++++-- drivers/iommu/mtk_iommu.h | 17 +++++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index f2137033ec59..b1ce0a2df583 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -122,6 +122,12 @@ struct mtk_iommu_pgtable { struct io_pgtable_ops *iop; struct device *init_dev; struct list_head m4u_dom_v2; + const struct mtk_domain_data *dom_region; +}; + +const struct mtk_domain_data single_dom = { + .min_iova = 0x0, + .max_iova = DMA_BIT_MASK(32) }; static struct mtk_iommu_pgtable *share_pgtable; @@ -400,6 +406,7 @@ static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data) dev_err(data->dev, "Failed to alloc io pgtable\n"); return ERR_PTR(-EINVAL); } + pgtable->dom_region = data->plat_data->dom_data; dev_info(data->dev, "%s create pgtable done\n", __func__); @@ -470,8 +477,10 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) /* Update our support page sizes bitmap */ dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap; - dom->domain.geometry.aperture_start = 0; - dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); + dom->domain.geometry.aperture_start = + pgtable->dom_region->min_iova; + dom->domain.geometry.aperture_end = + pgtable->dom_region->max_iova; dom->domain.geometry.force_aperture = true; list_add_tail(&dom->list, &pgtable->m4u_dom_v2); @@ -953,6 +962,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .has_bclk = true, .has_vld_pa_rng = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, .inv_sel_reg = REG_MMU_INV_SEL, }; @@ -960,6 +970,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, /* vp6a, vp6b, mdla/core2, mdla/edmc*/ .larbid_remap[1] = {2, 0, 3, 1}, @@ -976,6 +987,7 @@ static const struct mtk_iommu_plat_data mt8173_data = { .has_bclk = true, .reset_axi = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ .inv_sel_reg = REG_MMU_INV_SEL, }; @@ -984,6 +996,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, .reset_axi = true, .dom_cnt = 1, + .dom_data = &single_dom, .larbid_remap[0] = {0, 4, 5, 6, 7, 2, 3, 1}, .inv_sel_reg = REG_MMU_INV_SEL, }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 3a1c79222d09..a38b26018abe 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -36,6 +36,22 @@ enum mtk_iommu_plat { M4U_MT8183, }; +/* + * reserved IOVA Domain for IOMMU users of HW limitation. + */ + +/* + * struct mtk_domain_data: domain configuration + * @min_iova: Start address of iova + * @max_iova: End address of iova + * Note: one user can only belong to one domain + */ + +struct mtk_domain_data { + dma_addr_t min_iova; + dma_addr_t max_iova; +}; + struct mtk_iommu_plat_data { enum mtk_iommu_plat m4u_plat; bool has_4gb_mode; @@ -51,6 +67,7 @@ struct mtk_iommu_plat_data { u32 m4u1_mask; u32 inv_sel_reg; unsigned char larbid_remap[2][MTK_LARB_NR_MAX]; + const struct mtk_domain_data *dom_data; }; struct mtk_iommu_domain; From patchwork Sun Jan 5 10:45:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D173C33C8C for ; Sun, 5 Jan 2020 10:47:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 66737207FD for ; Sun, 5 Jan 2020 10:47:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Nav1LSOT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727170AbgAEKrW (ORCPT ); Sun, 5 Jan 2020 05:47:22 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:21552 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727025AbgAEKrV (ORCPT ); Sun, 5 Jan 2020 05:47:21 -0500 X-UUID: e07b8a8354b04b3db47f5fefc81ef96e-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/GRQoslk/LSHOdzw5eAs8KczvypmvSkfZUU+7BeTfag=; b=Nav1LSOT1U4hOZPHRAQOPwpEEN0ETiJqv12EqqTUB0fJjj3Z75xw1B/wWtBy/znYrmYLZPQg7NZKd7iBaDMepbdhhZSbDtHvsTn0idoI0rpiywdhIgX73fFO1lPdlqnBT7GAtdULoefecz1D3cPnyu19nY0aipfIO0CfPxDooSc=; X-UUID: e07b8a8354b04b3db47f5fefc81ef96e-20200105 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 304849129; Sun, 05 Jan 2020 18:47:14 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:49 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:45 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 16/19] iommu/mediatek: Remove mtk_iommu_get_m4u_data api Date: Sun, 5 Jan 2020 18:45:20 +0800 Message-ID: <20200105104523.31006-17-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Based on previous modifications in the patchset, A mtk_iommu_data structure represent a iommu, we will add mtk_iommu_data to mtk_iommu_domain to show the iommu which mtk_iommu_domain belongs to, so we can get mtk_iommu_data by mtk_iommu_domain, don't use to "mtk_iommu_get_m4u_data" any more. Besides, there is a small SW adjustment, we will move alloc iommu_group into "create_iommu_group" Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 74 +++++++++++++++++++-------------------- 1 file changed, 37 insertions(+), 37 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index bfb1831afae9..9a7f2a388e3e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -115,6 +115,7 @@ struct mtk_iommu_domain { u32 id; struct iommu_domain domain; struct iommu_group *group; + struct mtk_iommu_data *data; struct list_head list; }; @@ -162,23 +163,6 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */ #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) -/* - * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain - * for the performance. - * - * Here always return the mtk_iommu_data of the first probed M4U where the - * iommu domain information is recorded. - */ -static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) -{ - struct mtk_iommu_data *data; - - for_each_m4u(data) - return data; - - return NULL; -} - static u32 get_domain_id(struct mtk_iommu_data *data, u32 portid) { u32 dom_id = 0; @@ -397,6 +381,27 @@ static void mtk_iommu_config(struct mtk_iommu_data *data, } } +static struct iommu_group *create_iommu_group(struct mtk_iommu_data *data, + struct device *dev) +{ + struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); + + /* Prepare for allocate mtk_iommu_domain */ + data->m4u_group = mtk_iommu_get_group(dev); + if (!data->m4u_group) { + data->m4u_group = iommu_group_alloc(); + if (IS_ERR(data->m4u_group)) + dev_err(dev, "Failed to allocate M4U IOMMU group\n"); + } else { + iommu_group_ref_get(data->m4u_group); + } + + /* save the latest init device */ + pgtable->init_dev = dev; + + return data->m4u_group; +} + static struct mtk_iommu_pgtable *create_pgtable(struct mtk_iommu_data *data) { struct mtk_iommu_pgtable *pgtable; @@ -462,7 +467,7 @@ static int mtk_iommu_attach_pgtable(struct mtk_iommu_data *data, static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) { struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_data *data; struct mtk_iommu_domain *dom; struct device *dev; @@ -471,6 +476,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) if (pgtable) { dev = pgtable->init_dev; + data = dev_iommu_fwspec_get(dev)->iommu_priv; if (!data->m4u_group) { pr_err("%s, find m4u_group failed\n", __func__); return NULL; @@ -491,6 +497,7 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) if (dom->id >= data->plat_data->dom_cnt) goto put_dma_cookie; + dom->data = data; dom->group = data->m4u_group; /* Update our support page sizes bitmap */ dom->domain.pgsize_bitmap = pgtable->cfg.pgsize_bitmap; @@ -548,7 +555,8 @@ static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t paddr, size_t size, int prot, gfp_t gfp) { struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_data *data = dom->data; /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ if (data->enable_4GB) @@ -569,27 +577,30 @@ static size_t mtk_iommu_unmap(struct iommu_domain *domain, static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) { - mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data()); + struct mtk_iommu_domain *dom = to_mtk_domain(domain); + + mtk_iommu_tlb_flush_all(dom->data); } static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, struct iommu_iotlb_gather *gather) { - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_domain *dom = to_mtk_domain(domain); size_t length = gather->end - gather->start; if (gather->start == ULONG_MAX) return; mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, - data); + dom->data); } static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { struct mtk_iommu_pgtable *pgtable = mtk_iommu_get_pgtable(); - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_domain *dom = to_mtk_domain(domain); + struct mtk_iommu_data *data = dom->data; phys_addr_t pa; pa = pgtable->iop->iova_to_phys(pgtable->iop, iova); @@ -636,7 +647,7 @@ static void mtk_iommu_remove_device(struct device *dev) static struct iommu_group *mtk_iommu_device_group(struct device *dev) { - struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); + struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; struct mtk_iommu_pgtable *pgtable; int ret = 0; @@ -652,20 +663,9 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev) } } - /* All the client devices are in the same m4u iommu-group */ - data->m4u_group = mtk_iommu_get_group(dev); - if (!data->m4u_group) { - data->m4u_group = iommu_group_alloc(); - if (IS_ERR(data->m4u_group)) - dev_err(dev, "Failed to allocate M4U IOMMU group\n"); - } else { - iommu_group_ref_get(data->m4u_group); - } + dev_info(data->dev, "%s, init data:%d\n", __func__, data->m4u_id); - /* save the latest init device */ - pgtable->init_dev = dev; - - return data->m4u_group; + return create_iommu_group(data, dev); } static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) From patchwork Sun Jan 5 10:45:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Hao X-Patchwork-Id: 206168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E92C33C99 for ; Sun, 5 Jan 2020 10:47:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A67FE207FD for ; Sun, 5 Jan 2020 10:47:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Wt5c9fV2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727218AbgAEKr1 (ORCPT ); Sun, 5 Jan 2020 05:47:27 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:61073 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727200AbgAEKr0 (ORCPT ); Sun, 5 Jan 2020 05:47:26 -0500 X-UUID: 6aa44d3c98c74eeb9f0c1e78ab4293ac-20200105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3mbq9FpjSxSDLEY2w5X2s9Gfj1UKMBPHT8u/FwCDfyk=; b=Wt5c9fV25mF/KFJFOc5ImE3zvuehaP/tlV0EzygatHO1BspQwiF2nPZbJLb6Fkf8yLHOT/A4f7ZL8m7Fc2SmEaFcli4OgBqE+G4dSPduxiVx99Hhvmcs6SLNoJhbKdtMiR339KQwiphmQWMBq5J7E3YWZKscjL8LllIn+4aqU2c=; X-UUID: 6aa44d3c98c74eeb9f0c1e78ab4293ac-20200105 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1127711607; Sun, 05 Jan 2020 18:47:22 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 5 Jan 2020 18:46:54 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 5 Jan 2020 18:45:52 +0800 From: Chao Hao To: Joerg Roedel , Rob Herring , Matthias Brugger CC: , , , , , , Chao Hao , Jun Yan , Cui Zhang , Yong Wu , Anan Sun Subject: [PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779 Date: Sun, 5 Jan 2020 18:45:23 +0800 Message-ID: <20200105104523.31006-20-chao.hao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200105104523.31006-1-chao.hao@mediatek.com> References: <20200105104523.31006-1-chao.hao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For mt6779, it need to support three mtk_iommu_domains, every mtk_iommu_domain's iova space is different. Three mtk_iommu_domains is as below: 1. Normal mtk_iommu_domain exclude 0x4000_0000~0x47ff_ffff and 0x7da0_0000~7fbf_ffff. 2. CCU mtk_iommu_domain include 0x4000_0000~0x47ff_ffff. 3. VPU mtk_iommu_domain 0x7da0_0000~0x7fbf_ffff. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 45 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index ab09f435d437..d56254883541 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -134,6 +134,30 @@ const struct mtk_domain_data single_dom = { .max_iova = DMA_BIT_MASK(32) }; +/* + * related file: mt6779-larb-port.h + */ +const struct mtk_domain_data mt6779_multi_dom[] = { + /* normal domain */ + { + .min_iova = 0x0, + .max_iova = DMA_BIT_MASK(32), + }, + /* ccu domain */ + { + .min_iova = 0x40000000, + .max_iova = 0x48000000 - 1, + .port_mask = {MTK_M4U_ID(9, 21), MTK_M4U_ID(9, 22), + MTK_M4U_ID(12, 0), MTK_M4U_ID(12, 1)} + }, + /* vpu domain */ + { + .min_iova = 0x7da00000, + .max_iova = 0x7fc00000 - 1, + .port_mask = {MTK_M4U_ID(13, 0)} + } +}; + static struct mtk_iommu_pgtable *share_pgtable; static const struct iommu_ops mtk_iommu_ops; @@ -1050,6 +1074,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) }; +static const struct mtk_iommu_resv_iova_region mt6779_iommu_rsv_list[] = { + { + .dom_id = 0, + .iova_base = 0x40000000, /* CCU */ + .iova_size = 0x8000000, + .type = IOMMU_RESV_RESERVED, + }, + { + .dom_id = 0, + .iova_base = 0x7da00000, /* VPU/MDLA */ + .iova_size = 0x2700000, + .type = IOMMU_RESV_RESERVED, + }, +}; + static const struct mtk_iommu_plat_data mt2712_data = { .m4u_plat = M4U_MT2712, .has_4gb_mode = true, @@ -1063,8 +1102,10 @@ static const struct mtk_iommu_plat_data mt2712_data = { static const struct mtk_iommu_plat_data mt6779_data = { .m4u_plat = M4U_MT6779, - .dom_cnt = 1, - .dom_data = &single_dom, + .resv_cnt = ARRAY_SIZE(mt6779_iommu_rsv_list), + .resv_region = mt6779_iommu_rsv_list, + .dom_cnt = ARRAY_SIZE(mt6779_multi_dom), + .dom_data = mt6779_multi_dom, .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9}, /* vp6a, vp6b, mdla/core2, mdla/edmc*/ .larbid_remap[1] = {2, 0, 3, 1},