From patchwork Wed Jan 8 04:20:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 206034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8571AC33C9B for ; Wed, 8 Jan 2020 04:20:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 58C342072B for ; Wed, 8 Jan 2020 04:20:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="joSnIdyk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726594AbgAHEUs (ORCPT ); Tue, 7 Jan 2020 23:20:48 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:41883 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726210AbgAHEUs (ORCPT ); Tue, 7 Jan 2020 23:20:48 -0500 Received: by mail-pg1-f193.google.com with SMTP id x8so899299pgk.8 for ; Tue, 07 Jan 2020 20:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a9CbtpSeP2FndDuoSPtr7TkepCmjH+G9q6KhtPvuICk=; b=joSnIdykr9M65iSmT897djm+dYgRXOxKaLDa39hQjDBsRFT8cgHHS1HqfrC+8njn0S GmKpAfbIz9tI08oB05Mskl3Yrnlr1vqfYvN6GgvGWvX3FoY2D6jbqe2n4AiirNQdshck YcSK7KyOEEdgcfT1MDpDMqSH6+KBFM/JsK2panWK+6cq9d4i+8VHPl3LBwb3TRlt9GKC HWWP9v7YK8P8Gq1dR6DESgYndv5C65NUgUlKbRcPs16burh5GxlVTZ2qyyHDh2E6urd/ xOk5klU4x4BpUSEAZqvVBMOap07jbZTKpxI8KR4tyg/7ZBcjNuYba9rroCATi6io/1NX eQ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a9CbtpSeP2FndDuoSPtr7TkepCmjH+G9q6KhtPvuICk=; b=ozOsEdkVf4S7CdgZGg+e+kt2V709gc5UxOtPCQh76/w4Ady8BQszJr79h8g4VCt8B0 7a2lYl92nM2eo2OfaMkkEjL4Rizp5X6yy4ArwV6Qg0UTdYbUhpMN3xV9NhEwvqIsy8hJ OvIhXUAAKSNjXwybohW8/FjdyhGo627i+ngim+Z7wiGUBwECehJw1THrCzg3Hi1lPoFZ Y//80rqyUtcFZXTyqnHSJ3yhaOBusRQUXwfrdHA50L4/KLvJb1Jb7nGHgewgFR2NjGAM K/v4ARe0E9d4KlYqWIYPlBOApCP2wuWH9cdWQtBV/maLAdEA6zQ46/oLhNWFZ+7mBKUh +Msg== X-Gm-Message-State: APjAAAVVKAnpdnacSl9CJEgqQG1PiOORqit9/LTFqQzRQUhyjpLSXT1A 3uzOynTNgHL41kpsFrxSsEQ= X-Google-Smtp-Source: APXvYqzdjVZCW2V6yoSf9haV6oUXng2MFLJ+MiXr/PXgpLd1X/Um2PrG+0b8+5nZBm4rNj/J3c9wNQ== X-Received: by 2002:a63:de03:: with SMTP id f3mr3268086pgg.141.1578457247965; Tue, 07 Jan 2020 20:20:47 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p12sm1133478pjo.5.2020.01.07.20.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2020 20:20:47 -0800 (PST) From: Vasily Khoruzhick To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v2 2/4] arm64: dts: allwinner: a64: add cooling maps and thermal tripping points Date: Tue, 7 Jan 2020 20:20:16 -0800 Message-Id: <20200108042018.571251-3-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200108042018.571251-1-anarsoul@gmail.com> References: <20200108042018.571251-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add cooling maps and thermal tripping points to prevent CPU overheating when running at the highest frequency. Tripping points are taken from A33 dts since A64 user manual doesn't mention when we should start throttling. Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 77b33087866d..54a741f3cd8c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -92,6 +92,7 @@ cpu0: cpu@0 { next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -102,6 +103,7 @@ cpu1: cpu@1 { next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -112,6 +114,7 @@ cpu2: cpu@2 { next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -122,6 +125,7 @@ cpu3: cpu@3 { next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; L2: l2-cache { @@ -226,6 +230,46 @@ cpu_thermal: cpu0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; gpu0_thermal: gpu0-thermal { From patchwork Wed Jan 8 04:20:18 2020 Content-Type: text/plain; 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[216.71.213.236]) by smtp.gmail.com with ESMTPSA id p12sm1133478pjo.5.2020.01.07.20.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2020 20:20:49 -0800 (PST) From: Vasily Khoruzhick To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v2 4/4] arm64: dts: allwinner: a64: enable DVFS Date: Tue, 7 Jan 2020 20:20:18 -0800 Message-Id: <20200108042018.571251-5-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200108042018.571251-1-anarsoul@gmail.com> References: <20200108042018.571251-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CPU regulator and operating points for all the A64-based boards that are currently supported to enable DVFS. Signed-off-by: Vasily Khoruzhick --- .../dts/allwinner/sun50i-a64-amarula-relic.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-orangepi-win.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pinebook.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-teres-i.dts | 17 +++++++++++++++++ 9 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index 5634245d11db..6ee7291293ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -65,6 +66,22 @@ wifi_pwrseq: wifi-pwrseq { }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &csi { status = "okay"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 208373efee49..9b80e06f40d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -108,6 +109,22 @@ &codec_analog { status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &dai { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index 9b9d9157128c..6b81b91da504 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -87,6 +88,22 @@ wifi_pwrseq: wifi_pwrseq { }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index 01a9a52edae4..fb45c32558c5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -87,6 +88,22 @@ wifi_pwrseq: wifi_pwrseq { }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index f54a415f2e3b..a510cf40a9fe 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -44,6 +44,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -123,6 +124,22 @@ &codec_analog { status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &dai { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 409523cb0950..7cb01886aa32 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -84,6 +85,22 @@ &codec_analog { status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &dai { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 78c82a665c84..74a8569c677f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include #include @@ -98,6 +99,22 @@ &codec_analog { status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &dai { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 9d20e13f0c02..e64f330ca420 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -44,6 +44,7 @@ */ #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include @@ -51,6 +52,22 @@ &codec_analog { cpvdd-supply = <®_eldo1>; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index 970415106dcf..0356608ce467 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" #include #include @@ -104,6 +105,22 @@ &de { status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + &ehci1 { status = "okay"; };