From patchwork Wed Jan 8 04:24:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BD8AC33C9B for ; Wed, 8 Jan 2020 04:26:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DDA02070E for ; Wed, 8 Jan 2020 04:26:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="cHYk+eN9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726784AbgAHEZY (ORCPT ); Tue, 7 Jan 2020 23:25:24 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12474 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbgAHEZX (ORCPT ); Tue, 7 Jan 2020 23:25:23 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jan 2020 20:25:05 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 07 Jan 2020 20:25:22 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:22 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:22 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:21 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 01/21] dt-bindings: clock: tegra: Change CLK_M_DIV to OSC_DIV clocks Date: Tue, 7 Jan 2020 20:24:55 -0800 Message-ID: <1578457515-3477-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457505; bh=fz0oIBleYHAc98+TeBIodQTdGZvMElQMohnHQMAvR/Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cHYk+eN96v+MDW+I0GCSkoag2k3iKax2YtmQR1KSpKcMiZ3SXd46tPLDKCHvFgOmP 6E9dMh13CTrSiJxRjXZihs4dPkdg7O2piaMwkx55YdBozLXY9B0pFyrD3bIdh1poPQ xUX4x3HNnoraYanaRDVDYk25l9Nir/iDTcgAWXayAheH+yhTV69GVicN6DpbaqWAuF WJhJtehlGmGNLp+lLDqAiXWaWv8nVKqJgG1fyt7bm24mFJqg0bkJqE5PfGHi+gs4gC LnMuYdMEhx71R/FrRtAULPzGhJl8m+1O/bwjO3wpKQObyRylxn6yhjx8gwOTZBbSKZ BwdK1NBLUQT8w== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads. This patch changes CLK_M_DIV2 and CLK_M_DIV4 clock ids to OSC_DIV2 and OSC_DIV4 clock ids for Tegra30 through Tegra210. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra114-car.h | 4 ++-- include/dt-bindings/clock/tegra124-car-common.h | 4 ++-- include/dt-bindings/clock/tegra210-car.h | 4 ++-- include/dt-bindings/clock/tegra30-car.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..f4880959b094 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -226,8 +226,8 @@ #define TEGRA114_CLK_FUSE_BURN 199 #define TEGRA114_CLK_CLK_32K 200 #define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_OSC_DIV2 202 +#define TEGRA114_CLK_OSC_DIV4 203 #define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..e7e601a88d3d 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -225,8 +225,8 @@ #define TEGRA124_CLK_FUSE_BURN 199 #define TEGRA124_CLK_CLK_32K 200 #define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_OSC_DIV2 202 +#define TEGRA124_CLK_OSC_DIV4 203 #define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C_OUT1 206 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..6f65c14bf013 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -260,8 +260,8 @@ #define TEGRA210_CLK_FUSE_BURN 231 #define TEGRA210_CLK_CLK_32K 232 #define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_OSC_DIV2 234 +#define TEGRA210_CLK_OSC_DIV4 235 #define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C_OUT1 238 diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..907a8a04c280 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -194,8 +194,8 @@ #define TEGRA30_CLK_TVO 169 #define TEGRA30_CLK_CLK_32K 170 #define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_OSC_DIV2 172 +#define TEGRA30_CLK_OSC_DIV4 173 #define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C_OUT1 176 From patchwork Wed Jan 8 04:24:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19AFCC00523 for ; Wed, 8 Jan 2020 04:25:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E2F0420705 for ; Wed, 8 Jan 2020 04:25:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ccXExT9i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726916AbgAHEZ1 (ORCPT ); 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Tue, 07 Jan 2020 20:25:24 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 03/21] dt-bindings: clock: tegra: Add DT id for OSC clock Date: Tue, 7 Jan 2020 20:24:57 -0800 Message-ID: <1578457515-3477-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457508; bh=1NvJ4YURq3GMhbv3Ehpy1wVvFQ3o290gPEqmiMK1NGc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ccXExT9iWvYiQ7/2ZwxShUnJ7tYErUgzxE0PIJXBB5pAY+x8rrvvzV8s4JkYy+Lj1 c6kwOrYy4WdsrAsamAy8Nkdi9RFJNQiXOlPUlogZR07T9zAyp72I8FAWolcZsdRn+5 q/8Gfko39Yuj2ebTvhOnXwjBWwY24BR+jJYQpahWHaYicGHOuj9nnqrPGwuvMJh6YQ rUySuX4rJpa9GJ+xZmMvcvBQd55+GLYwrB3flhN/5PODcjhlEAb2EpKswIPQU0kl/f +YYHANLziuVcbuxd5Qhmlk2e0d6UP8j+sQf6vJ7teG+uEXwkcJfdPazmgnhU4fxt1g Mmz/qw1LUBD0g== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org OSC is one of the parent for Tegra clocks clk_out_1, clk_out_2, and clk_out_3. This patch adds DT id for OSC clock to allow parent configuration through device tree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra114-car.h | 2 +- include/dt-bindings/clock/tegra124-car-common.h | 2 +- include/dt-bindings/clock/tegra210-car.h | 2 +- include/dt-bindings/clock/tegra30-car.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index f4880959b094..e3927cabccad 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -274,7 +274,7 @@ #define TEGRA114_CLK_CLK_OUT_2 246 #define TEGRA114_CLK_CLK_OUT_3 247 #define TEGRA114_CLK_BLINK 248 -/* 249 */ +#define TEGRA114_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA114_CLK_XUSB_HOST_SRC 252 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index e7e601a88d3d..45b2bada8ac0 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -273,7 +273,7 @@ #define TEGRA124_CLK_CLK_OUT_2 246 #define TEGRA124_CLK_CLK_OUT_3 247 #define TEGRA124_CLK_BLINK 248 -/* 249 */ +#define TEGRA124_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA124_CLK_XUSB_HOST_SRC 252 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 6f65c14bf013..383ee591ffa7 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -355,7 +355,7 @@ #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 /* 325 */ -/* 326 */ +#define TEGRA210_CLK_OSC 326 /* 327 */ /* 328 */ /* 329 */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 907a8a04c280..5d71f0c0a732 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -243,7 +243,7 @@ #define TEGRA30_CLK_HCLK 217 #define TEGRA30_CLK_PCLK 218 /* 219 */ -/* 220 */ +#define TEGRA30_CLK_OSC 220 /* 221 */ /* 222 */ /* 223 */ From patchwork Wed Jan 8 04:24:58 2020 Content-Type: text/plain; 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Tue, 07 Jan 2020 20:25:26 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 04/21] clk: tegra: Add Tegra OSC to clock lookup Date: Tue, 7 Jan 2020 20:24:58 -0800 Message-ID: <1578457515-3477-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457479; bh=GKPxhjaKJ2CxomnsrG8DSoIgQUhEXD4NQLXXH2lZWU8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=eCYVu+aJAUdfv6gqpE3eug68uDdb79remRyflDNqXe5skbj42tPqLSnY2Fny9AeTB QlVyNaRDx3zhFMa8TSByMpaapzj6IrzOp46tZGkGDPUtiV4yADhLfgnl+bbHc29tET 6y3F2x6QZ8virBV57QQRdPuemLhqXEjkpu9MeEss8WaHh/ou/dBIFyYXUpfXL2rJFO 1QaX4PzQeTR092BVMBlQlqpRBXtGEtw8a5+dvzVm+cprhlMQReWxCR0ASRqrReD/tf NkpO16mdk1b1nEJOOljbk1NDbi478rMWpO9NWThG01P1QlJX6BDLDP5qmYkbixTwaw b7OYuWORIxa9A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org OSC is one of the parent for Tegra clocks clk_out_1, clk_out_2, and clk_out_3. So, this patch adds Tegra OSC to clock lookup. Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-fixed.c | 5 +++++ drivers/clk/tegra/clk-tegra114.c | 2 ++ drivers/clk/tegra/clk-tegra124.c | 2 ++ drivers/clk/tegra/clk-tegra210.c | 2 ++ drivers/clk/tegra/clk-tegra30.c | 2 ++ 6 files changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 1bf21766d3e8..cf42e5995794 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -44,6 +44,7 @@ enum clk_id { tegra_clk_clk72Mhz, tegra_clk_clk72Mhz_8, tegra_clk_clk_m, + tegra_clk_osc, tegra_clk_osc_div2, tegra_clk_osc_div4, tegra_clk_clk_out_1, diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 8304f8cf9dd2..205d1a6d3e77 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -46,7 +46,12 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, return -EINVAL; } + dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks); + if (!dt_clk) + return 0; + osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq); + *dt_clk = osc; dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks); if (!dt_clk) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 9d2ca387114c..180ddc2abfd2 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -735,6 +735,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true }, + [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true }, @@ -815,6 +816,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, + { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C }, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 15f42718f4cb..7a16e50eb20f 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -860,6 +860,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, + [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, @@ -941,6 +942,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, + { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 5687fcda620e..45d54ead30bc 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2371,6 +2371,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, + [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, @@ -2497,6 +2498,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, + { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 1322188edb72..ddc5ab66d09e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -581,6 +581,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD }, { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC }, { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, + { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 }, { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 }, @@ -683,6 +684,7 @@ static struct tegra_devclk devclks[] __initdata = { static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, + [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true }, From patchwork Wed Jan 8 04:25:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 774BAC33C9B for ; Wed, 8 Jan 2020 04:26:44 +0000 (UTC) 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07 Jan 2020 20:25:30 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:30 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:29 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 06/21] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Date: Tue, 7 Jan 2020 20:25:00 -0800 Message-ID: <1578457515-3477-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457513; bh=5qz9Go6yPFIBRrCn+CnRnOXkFDondDCVPoc4RPQFkFU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=csstbNnJCyZ4wGIb6Tcsm9q2Hjb3dO208Yxa3YXwR+zE2nwn1A/hmVEG+JEVur+xG f3I/xobN9h858fYrKHSgivXo3vGGS8khh8xQWaMVMaRviBUIXY6xaRrYb0CdMiHiis 0yKB4mI3Ms6czgtSuzUnZJLlT4WS08MeAiUColyasyTSviTOTw9xCa1Vnq620DpwwP eojnuTB0XqXaM6Rx2SP+5j6OIf5GWRFXlhyymDpGCIrN58uWp7MMRgR8Cz4BBa6ZV0 XQ0VcxXYRTPAnaWCB27r/QkOgEVWwkC2h524bGV5WSfPIq3S39cQrA282sOt3HD6M+ ZfufqdpFVKhCQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch converts text based Tegra PMC bindings document to YAML schema for performing dt validation. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 ------------------ .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 340 +++++++++++++++++++++ 2 files changed, 340 insertions(+), 300 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index cb12f33a247f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null @@ -1,300 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -== Power Management Controller Node == - -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: -- name : Should be pmc -- compatible : Should contain one of the following: - For Tegra20 must contain "nvidia,tegra20-pmc". - For Tegra30 must contain "nvidia,tegra30-pmc". - For Tegra114 must contain "nvidia,tegra114-pmc" - For Tegra124 must contain "nvidia,tegra124-pmc" - For Tegra132 must contain "nvidia,tegra124-pmc" - For Tegra210 must contain "nvidia,tegra210-pmc" -- reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: -- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and then - fed into the ARM GIC. The PMC is not involved in the detection or - handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. - -Hardware-triggered thermal reset: -On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists, -hardware-triggered thermal reset will be enabled. - -Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are - described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the - Tegra K1 Technical Reference Manual. -- nvidia,bus-addr : Bus address of the PMU on the I2C bus -- nvidia,reg-addr : I2C register address to write poweroff command to -- nvidia,reg-data : Poweroff command to write to PMU - -Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'): -- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. - -Optional nodes: -- powergates : This node contains a hierarchy of power domain nodes, which - should match the powergates on the Tegra SoC. See "Powergate - Nodes" below. - -Example: - -/ SoC dts including file -pmc@7000f400 { - compatible = "nvidia,tegra20-pmc"; - reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - pmc@7000f400 { - i2c-thermtrip { - nvidia,i2c-controller-id = <4>; - nvidia,bus-addr = <0x40>; - nvidia,reg-addr = <0x36>; - nvidia,reg-data = <0x2>; - }; - }; - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... -}; - - -== Powergate Nodes == - -Each of the powergate nodes represents a power-domain on the Tegra SoC -that can be power-gated by the Tegra PMC. The name of the powergate node -should be one of the below. Note that not every powergate is applicable -to all Tegra devices and the following list shows which powergates are -applicable to which devices. Please refer to the Tegra TRM for more -details on the various powergates. - - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 - -Required properties: - - clocks: Must contain an entry for each clock required by the PMC for - controlling a power-gate. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each reset required by the PMC for - controlling a power-gate. See ../reset/reset.txt for details. - - #power-domain-cells: Must be 0. - -Example: - - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - }; - }; - - -== Powergate Clients == - -Hardware blocks belonging to a power domain should contain a "power-domains" -property that is a phandle pointing to the corresponding powergate node. - -Example: - - adma: adma@702e2000 { - ... - power-domains = <&pd_audio>; - ... - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -The pad configuration state nodes are placed under the pmc node and they -are referred to by the pinctrl client properties. For more information -see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. -The pad name should be used as the value of the pins property in pin -configuration nodes. - -The following pads are present on Tegra124 and Tegra132: -audio bb cam comp -csia csb cse dsi -dsib dsic dsid hdmi -hsic hv lvds mipi-bias -nand pex-bias pex-clk1 pex-clk2 -pex-cntrl sdmmc1 sdmmc3 sdmmc4 -sys_ddc uart usb0 usb1 -usb2 usb_bias - -The following pads are present on Tegra210: -audio audio-hv cam csia -csib csic csid csie -csif dbg debug-nonao dmic -dp dsi dsib dsic -dsid emmc emmc2 gpio -hdmi hsic lvds mipi-bias -pex-bias pex-clk1 pex-clk2 pex-cntrl -sdmmc1 sdmmc3 spi spi-hv -uart usb0 usb1 usb2 -usb3 usb-bias - -Required pin configuration properties: - - pins: Must contain name of the pad(s) to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 - or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the Tegra124 and - Tegra132 pads. None of the Tegra124 or Tegra132 pads support - signaling voltage switching. - -Note: All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported on - following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio, - pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = ; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@700b0000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - ... - sor@54540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml new file mode 100644 index 000000000000..3ff34b348141 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -0,0 +1,340 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra20-pmc + - nvidia,tegra20-pmc + - nvidia,tegra30-pmc + - nvidia,tegra114-pmc + - nvidia,tegra124-pmc + - nvidia,tegra210-pmc + + reg: + maxItems: 1 + description: + Offset and length of the register set for the device. + + clock-names: + items: + - const: pclk + - const: clk32k_in + description: + Must includes entries pclk and clk32k_in. + pclk is the Tegra clock of that name and clk32k_in is 32KHz clock + input to Tegra. + + clocks: + maxItems: 2 + description: + Must contain an entry for each entry in clock-names. + See ../clocks/clocks-bindings.txt for details. + + '#interrupt-cells': + const: 2 + description: + Specifies number of cells needed to encode an interrupt source. + The value must be 2. + + interrupt-controller: true + + nvidia,invert-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Inverts the PMU interrupt signal. + The PMU is an external Power Management Unit, whose interrupt output + signal is fed into the PMC. This signal is optionally inverted, and + then fed into the ARM GIC. The PMC is not involved in the detection + or handling of this interrupt signal, merely its inversion. + + nvidia,core-power-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: Core power request active-high. + + nvidia,sys-clock-req-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: System clock request active-high. + + nvidia,combined-power-req: + $ref: /schemas/types.yaml#/definitions/flag + description: combined power request for CPU and Core. + + nvidia,cpu-pwr-good-en: + $ref: /schemas/types.yaml#/definitions/flag + description: + CPU power good signal from external PMIC to PMC is enabled. + + nvidia,suspend-mode: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2] + description: + The suspend mode that the platform should use. + Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh + Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh + Mode 2 is for LP2, CPU voltage off + + nvidia,cpu-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power good time in uSec. + + nvidia,cpu-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: CPU power off time in uSec. + + nvidia,core-pwr-good-time: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + + Core power good time in uSec. + + nvidia,core-pwr-off-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Core power off time in uSec. + + nvidia,lp0-vec: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Starting address and length of LP0 vector. + The LP0 vector contains the warm boot code that is executed + by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and + always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed + from the deep sleep mode, the warm boot code will restore + some PLLs, clocks and then brings up CPU0 for resuming the + system. + + i2c-thermtrip: + type: object + description: + On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, + hardware-triggered thermal reset will be enabled. + + properties: + nvidia,i2c-controller-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 + "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference + Manual. + + nvidia,bus-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus address of the PMU on the I2C bus. + + nvidia,reg-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PMU I2C register address to issue poweroff command. + + nvidia,reg-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Poweroff command to write to PMU. + + nvidia,pinmux-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pinmux used by the hardware when issuing Poweroff command. + Defaults to 0. Valid values are described in section 12.5.2 + "Pinmux Support" of the Tegra4 Technical Reference Manual. + + required: + - nvidia,i2c-controller-id + - nvidia,bus-addr + - nvidia,reg-addr + - nvidia,reg-data + + additionalProperties: false + + powergates: + type: object + description: | + This node contains a hierarchy of power domain nodes, which should + match the powergates on the Tegra SoC. Each powergate node + represents a power-domain on the Tegra SoC that can be power-gated + by the Tegra PMC. + Hardware blocks belonging to a power domain should contain + "power-domains" property that is a phandle pointing to corresponding + powergate node. + The name of the powergate node should be one of the below. Note that + not every powergate is applicable to all Tegra devices and the following + list shows which powergates are applicable to which devices. + Please refer to Tegra TRM for mode details on the powergate nodes to + use for each power-gate block inside Tegra. + Name Description Devices Applicable + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 + + patternProperties: + "^[a-z0-9]+$": + type: object + + patternProperties: + clocks: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each clock required by the PMC + for controlling a power-gate. + See ../clocks/clock-bindings.txt document for more details. + + resets: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each reset required by the PMC + for controlling a power-gate. + See ../reset/reset.txt for more details. + + '#power-domain-cells': + const: 0 + description: Must be 0. + + required: + - clocks + - resets + - '#power-domain-cells' + + additionalProperties: false + +patternProperties: + "^[a-f0-9]+-[a-f0-9]+$": + type: object + description: + This is a Pad configuration node. On Tegra SOCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power state + and signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages + are supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and they + are referred to by the pinctrl client properties. For more information + see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132 + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, + hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. + + The following pads are present on Tegra210 + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, + hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. + The values are defined in + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. + Power state can be configured on all Tegra124 and Tegra132 + pads. None of the Tegra124 or Tegra132 pads support signaling + voltage switching. + All of the listed Tegra210 pads except pex-cntrl support power + state configuration. Signaling voltage switching is supported + on below Tegra210 pads. + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, and uart. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - clock-names + - clocks + +dependencies: + "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] + "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] + "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] + +examples: + - | + + #include + #include + + tegra_pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + }; + }; From patchwork Wed Jan 8 04:25:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B76BC33C9B for ; Wed, 8 Jan 2020 04:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A79D2072B for ; Wed, 8 Jan 2020 04:26:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="PTSL0KNN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726913AbgAHE0d (ORCPT ); Tue, 7 Jan 2020 23:26:33 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12494 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727137AbgAHEZi (ORCPT ); Tue, 7 Jan 2020 23:25:38 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jan 2020 20:25:19 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 07 Jan 2020 20:25:37 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 07 Jan 2020 20:25:37 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:36 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:36 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 10/21] soc: tegra: Add support for 32KHz blink clock Date: Tue, 7 Jan 2020 20:25:04 -0800 Message-ID: <1578457515-3477-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457519; bh=g4ZYQgDeHLyQ8G/Hp5+/9Puo3KLwSArI8ngb27wu8O8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=PTSL0KNN/DNyoBqtv69ZQST0sSH71PBDZXE8Yj8mpL4bqRMhma0WT/Ro+/o7TLMin cZ+g5vZq0N9SIt7blZqgwPR+5AHdPnDoJOk/3DAmLCIe6YKhrSf9kpHC5qgZ/GMZbs S09l6fwY88apNyg0oN551KMH+iqGjpYymWJj0qbaL3+p3WPKMBYqupKCJpfujJDBVi H+2ei54Vj5XE+kp6INsuuX3ATRrTvxc9STDLfiPJCVFgk15AFlGngrs0CstgF7R3+U 7HOoEStZROOQ8ohyJVxeG+XiEpTw/HWKp/qU5a3T1XdUcOQgw6hIBhRC7ZKkvKzSvQ VfmXB8nMQlxNg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra PMC has blink control to output 32 Khz clock out to Tegra blink pin. Blink pad DPD state and enable controls are part of Tegra PMC register space. Currently Tegra clock driver registers blink control by passing PMC address and register offset to clk_register_gate which performs direct PMC access during clk_ops and with this when PMC is in secure mode, any access from non-secure world does not go through. This patch adds blink control registration to the Tegra PMC driver using PMC specific clock gate operations that use tegra_pmc_readl and tegra_pmc_writel to support both secure mode and non-secure mode PMC register access. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2b1a709c3cb7..280f0c14e4ec 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -62,12 +62,15 @@ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) +#define PMC_CNTRL_BLINK_EN 7 #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_WAKE_MASK 0x0c #define PMC_WAKE_LEVEL 0x10 #define PMC_WAKE_STATUS 0x14 #define PMC_SW_WAKE_STATUS 0x18 +#define PMC_DPD_PADS_ORIDE 0x1c +#define PMC_DPD_PADS_ORIDE_BLINK 20 #define DPD_SAMPLE 0x020 #define DPD_SAMPLE_ENABLE BIT(0) @@ -80,6 +83,7 @@ #define PWRGATE_STATUS 0x38 +#define PMC_BLINK_TIMER 0x40 #define PMC_IMPL_E_33V_PWR 0x40 #define PMC_PWR_DET 0x48 @@ -171,6 +175,14 @@ struct pmc_clk { #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) +struct pmc_clk_gate { + struct clk_hw hw; + unsigned long offs; + u32 shift; +}; + +#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) + struct pmc_clk_init_data { char *name; const char *const *parents; @@ -321,6 +333,7 @@ struct tegra_pmc_soc { const struct pmc_clk_init_data *pmc_clks_data; unsigned int num_pmc_clks; + bool has_blink_output; }; static const char * const tegra186_reset_sources[] = { @@ -2334,6 +2347,60 @@ tegra_pmc_clk_out_register(struct tegra_pmc *pmc, return clk_register(NULL, &pmc_clk->hw); } +static int pmc_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); + + return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; +} + +static int pmc_clk_gate_enable(struct clk_hw *hw) +{ + struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); + + pmc_clk_set_state(gate->offs, gate->shift, 1); + + return 0; +} + +static void pmc_clk_gate_disable(struct clk_hw *hw) +{ + struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); + + pmc_clk_set_state(gate->offs, gate->shift, 0); +} + +static const struct clk_ops pmc_clk_gate_ops = { + .is_enabled = pmc_clk_gate_is_enabled, + .enable = pmc_clk_gate_enable, + .disable = pmc_clk_gate_disable, +}; + +static struct clk * +tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, + const char *parent_name, unsigned long offset, + u32 shift) +{ + struct clk_init_data init; + struct pmc_clk_gate *gate; + + gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &pmc_clk_gate_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + + gate->hw.init = &init; + gate->offs = offset; + gate->shift = shift; + + return clk_register(NULL, &gate->hw); +} + static void tegra_pmc_clock_register(struct tegra_pmc *pmc, struct device_node *np) { @@ -2343,6 +2410,8 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc, int i, err; num_clks = pmc->soc->num_pmc_clks; + if (pmc->soc->has_blink_output) + num_clks += 1; if (!num_clks) return; @@ -2384,6 +2453,40 @@ static void tegra_pmc_clock_register(struct tegra_pmc *pmc, clk_data->clks[data->clk_id] = clk; } + if (pmc->soc->has_blink_output) { + tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); + clk = tegra_pmc_clk_gate_register(pmc, "blink_override", + "clk_32k", + PMC_DPD_PADS_ORIDE, + PMC_DPD_PADS_ORIDE_BLINK); + if (IS_ERR(clk)) { + dev_warn(pmc->dev, + "unable to register blink_override: %d\n", + PTR_ERR_OR_ZERO(clk)); + return; + } + + clk = tegra_pmc_clk_gate_register(pmc, "blink", + "blink_override", + PMC_CNTRL, + PMC_CNTRL_BLINK_EN); + if (IS_ERR(clk)) { + dev_warn(pmc->dev, "unable to register blink: %d\n", + PTR_ERR_OR_ZERO(clk)); + return; + } + + err = clk_register_clkdev(clk, "blink", NULL); + if (err) { + dev_warn(pmc->dev, + "unable to register blink clock lookup: %d\n", + err); + return; + } + + clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; + } + err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); if (err) dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", @@ -2652,6 +2755,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .num_reset_levels = 0, .pmc_clks_data = NULL, .num_pmc_clks = 0, + .has_blink_output = true, }; static const char * const tegra30_powergates[] = { @@ -2701,6 +2805,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .num_reset_levels = 0, .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), + .has_blink_output = true, }; static const char * const tegra114_powergates[] = { @@ -2754,6 +2859,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .num_reset_levels = 0, .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), + .has_blink_output = true, }; static const char * const tegra124_powergates[] = { @@ -2867,6 +2973,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { .num_reset_levels = 0, .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), + .has_blink_output = true, }; static const char * const tegra210_powergates[] = { @@ -2983,6 +3090,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .wake_events = tegra210_wake_events, .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), + .has_blink_output = true, }; #define TEGRA186_IO_PAD_TABLE(_pad) \ @@ -3114,6 +3222,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .wake_events = tegra186_wake_events, .pmc_clks_data = NULL, .num_pmc_clks = 0, + .has_blink_output = false, }; static const struct tegra_io_pad_soc tegra194_io_pads[] = { @@ -3233,6 +3342,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .wake_events = tegra194_wake_events, .pmc_clks_data = NULL, .num_pmc_clks = 0, + .has_blink_output = false, }; static const struct of_device_id tegra_pmc_match[] = { From patchwork Wed Jan 8 04:25:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41BEBC33C9B for ; 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by hqpgpgate102.nvidia.com on Tue, 07 Jan 2020 20:25:39 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:38 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:38 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:38 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:37 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 11/21] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Date: Tue, 7 Jan 2020 20:25:05 -0800 Message-ID: <1578457515-3477-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457521; bh=IIKzLAIwRv7hz1NVeZfrWGWpINvFcOxl4tNERV11k9o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=gmEeOLnSvljFhuNOsXJesONh1g1lPVfB7JwjzNq8JOlDTObWmsYbkKUqlOI0+zvPJ NeAl3S0p5ntjyJmwWxBQdT7AtwP1t3iAqZHc36+7G2XJL4gAnOrnsZHfAKVnYIeU82 vkJn51AAYw3nSsPFFD/qPKwosDN7J0IXUCmfFjIB3Y9cCp/MbTLpwxKZvuXKSnWMqd hDtk2JI3AQJEARdFEQC9ckk6K3yTPPigFNsBjE0okvrX+KKPYFWG4wRX6UdtVHwgJQ 2LIukrUkUJgfuWkAf/Qgohh2TkqmEtrFAZRSQmIkCRSsvNamZX0g8y4LAlGBCWAvv2 QaObRqddWFKuA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/Makefile | 1 - drivers/clk/tegra/clk-id.h | 7 --- drivers/clk/tegra/clk-tegra-pmc.c | 122 -------------------------------------- drivers/clk/tegra/clk-tegra114.c | 17 +----- drivers/clk/tegra/clk-tegra124.c | 33 ++++------- drivers/clk/tegra/clk-tegra20.c | 4 -- drivers/clk/tegra/clk-tegra210.c | 17 +----- drivers/clk/tegra/clk-tegra30.c | 18 +----- drivers/clk/tegra/clk.h | 1 - 9 files changed, 19 insertions(+), 201 deletions(-) delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index df966ca06788..1f7c30f87ece 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o obj-y += clk-super.o obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o -obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index cf42e5995794..ff7da2d3e94d 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -32,7 +32,6 @@ enum clk_id { tegra_clk_audio4, tegra_clk_audio4_2x, tegra_clk_audio4_mux, - tegra_clk_blink, tegra_clk_bsea, tegra_clk_bsev, tegra_clk_cclk_g, @@ -47,12 +46,6 @@ enum clk_id { tegra_clk_osc, tegra_clk_osc_div2, tegra_clk_osc_div4, - tegra_clk_clk_out_1, - tegra_clk_clk_out_1_mux, - tegra_clk_clk_out_2, - tegra_clk_clk_out_2_mux, - tegra_clk_clk_out_3, - tegra_clk_clk_out_3_mux, tegra_clk_cml0, tegra_clk_cml1, tegra_clk_csi, diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c deleted file mode 100644 index 5e044ba1ae36..000000000000 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" -#include "clk-id.h" - -#define PMC_CLK_OUT_CNTRL 0x1a8 -#define PMC_DPD_PADS_ORIDE 0x1c -#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 -#define PMC_CTRL 0 -#define PMC_CTRL_BLINK_ENB 7 -#define PMC_BLINK_TIMER 0x40 - -struct pmc_clk_init_data { - char *mux_name; - char *gate_name; - const char **parents; - int num_parents; - int mux_id; - int gate_id; - char *dev_name; - u8 mux_shift; - u8 gate_shift; -}; - -#define PMC_CLK(_num, _mux_shift, _gate_shift)\ - {\ - .mux_name = "clk_out_" #_num "_mux",\ - .gate_name = "clk_out_" #_num,\ - .parents = clk_out ##_num ##_parents,\ - .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\ - .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\ - .gate_id = tegra_clk_clk_out_ ##_num,\ - .dev_name = "extern" #_num,\ - .mux_shift = _mux_shift,\ - .gate_shift = _gate_shift,\ - } - -static DEFINE_SPINLOCK(clk_out_lock); - -static const char *clk_out1_parents[] = { "osc", "osc_div2", - "osc_div4", "extern1", -}; - -static const char *clk_out2_parents[] = { "osc", "osc_div2", - "osc_div4", "extern2", -}; - -static const char *clk_out3_parents[] = { "osc", "osc_div2", - "osc_div4", "extern3", -}; - -static struct pmc_clk_init_data pmc_clks[] = { - PMC_CLK(1, 6, 2), - PMC_CLK(2, 14, 10), - PMC_CLK(3, 22, 18), -}; - -void __init tegra_pmc_clk_init(void __iomem *pmc_base, - struct tegra_clk *tegra_clks) -{ - struct clk *clk; - struct clk **dt_clk; - int i; - - for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) { - struct pmc_clk_init_data *data; - - data = pmc_clks + i; - - dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks); - if (!dt_clk) - continue; - - clk = clk_register_mux(NULL, data->mux_name, data->parents, - data->num_parents, - CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, - pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift, - 3, 0, &clk_out_lock); - *dt_clk = clk; - - - dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks); - if (!dt_clk) - continue; - - clk = clk_register_gate(NULL, data->gate_name, data->mux_name, - CLK_SET_RATE_PARENT, - pmc_base + PMC_CLK_OUT_CNTRL, - data->gate_shift, 0, &clk_out_lock); - *dt_clk = clk; - clk_register_clkdev(clk, data->dev_name, data->gate_name); - } - - /* blink */ - writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); - clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, - pmc_base + PMC_DPD_PADS_ORIDE, - PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); - - dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks); - if (!dt_clk) - return; - - clk = clk_register_gate(NULL, "blink", "blink_override", 0, - pmc_base + PMC_CTRL, - PMC_CTRL_BLINK_ENB, 0, NULL); - clk_register_clkdev(clk, "blink", NULL); - *dt_clk = clk; -} - diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 180ddc2abfd2..c138ef75480b 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -779,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true }, [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true }, [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true }, - [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true }, - [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true }, - [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true }, - [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true }, [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true }, [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true }, [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true }, @@ -804,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true }, [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true }, - [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true }, - [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true }, - [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true }, [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true }, [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true }, @@ -865,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X }, { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X }, { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X }, - { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 }, - { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 }, - { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 }, - { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK }, + { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 }, + { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 }, + { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 }, { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G }, { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP }, { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK }, @@ -1147,8 +1139,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 }, { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 }, { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 }, - { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 }, - { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 }, { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, @@ -1350,7 +1340,6 @@ static void __init tegra114_clock_init(struct device_node *np) tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, tegra114_audio_plls, ARRAY_SIZE(tegra114_audio_plls), 24000000); - tegra_pmc_clk_init(pmc_base, tegra114_clks); tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, &pll_x_params); diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 7a16e50eb20f..54cac77deaa3 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -903,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true }, [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true }, [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true }, - [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true }, - [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true }, - [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true }, - [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true }, [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true }, [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, @@ -932,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true }, [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, - [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, - [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, - [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, }; @@ -990,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X }, { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X }, { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X }, - { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 }, - { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 }, - { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 }, - { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK }, + { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 }, + { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 }, + { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 }, { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G }, { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP }, { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK }, @@ -1303,8 +1295,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 }, { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 }, { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 }, - { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 }, - { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 }, { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, @@ -1459,11 +1449,9 @@ static void __init tegra132_clock_apply_init_table(void) * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132 * @np: struct device_node * of the DT node for the SoC CAR IP block * - * Register most of the clocks controlled by the CAR IP block, along - * with a few clocks controlled by the PMC IP block. Everything in - * this function should be common to Tegra124 and Tegra132. XXX The - * PMC clock initialization should probably be moved to PMC-specific - * driver code. No return value. + * Register most of the clocks controlled by the CAR IP block. + * Everything in this function should be common to Tegra124 and Tegra132. + * No return value. */ static void __init tegra124_132_clock_init_pre(struct device_node *np) { @@ -1506,7 +1494,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, tegra124_audio_plls, ARRAY_SIZE(tegra124_audio_plls), 24576000); - tegra_pmc_clk_init(pmc_base, tegra124_clks); /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */ plld_base = readl(clk_base + PLLD_BASE); @@ -1518,11 +1505,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 * @np: struct device_node * of the DT node for the SoC CAR IP block * - * Register most of the along with a few clocks controlled by the PMC - * IP block. Everything in this function should be common to Tegra124 + * Register most of the clocks controlled by the CAR IP block. + * Everything in this function should be common to Tegra124 * and Tegra132. This function must be called after - * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will - * not be set. No return value. + * tegra124_132_clock_init_pre(), otherwise clk_base will not be set. + * No return value. */ static void __init tegra124_132_clock_init_post(struct device_node *np) { diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4d8222f5c638..fe536f1d770d 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, - { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK }, { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, @@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, - [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true }, [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, @@ -1034,7 +1032,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 }, { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 }, { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 }, - { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 }, { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 }, @@ -1148,7 +1145,6 @@ static void __init tegra20_clock_init(struct device_node *np) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); tegra20_periph_clk_init(); tegra20_audio_clk_init(); - tegra_pmc_clk_init(pmc_base, tegra20_clks); tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 45d54ead30bc..d2f1e9c0ed25 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2418,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, - [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true }, - [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true }, - [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true }, - [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true }, [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, @@ -2453,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, - [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true }, - [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true }, - [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true }, [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, @@ -2542,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, - { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 }, - { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 }, - { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 }, - { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK }, + { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 }, + { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 }, + { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 }, { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, @@ -3453,8 +3445,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 }, { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 }, { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 }, - { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 }, - { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 }, { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, @@ -3695,7 +3685,6 @@ static void __init tegra210_clock_init(struct device_node *np) tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, tegra210_audio_plls, ARRAY_SIZE(tegra210_audio_plls), 24576000); - tegra_pmc_clk_init(pmc_base, tegra210_clks); /* For Tegra210, PLLD is the only source for DSIA & DSIB */ value = readl(clk_base + PLLD_BASE); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index ddc5ab66d09e..5732fdbe20db 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X }, { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X }, { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X }, - { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 }, - { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 }, - { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 }, - { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK }, + { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 }, + { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 }, + { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 }, { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G }, { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP }, { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK }, @@ -713,13 +712,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true }, [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true }, [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true }, - [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true }, - [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true }, - [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true }, - [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true }, - [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true }, - [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true }, - [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true }, [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true }, [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true }, [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true }, @@ -1232,9 +1224,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 }, { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 }, { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 }, - { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 }, - { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, @@ -1366,7 +1355,6 @@ static void __init tegra30_clock_init(struct device_node *np) tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, tegra30_audio_plls, ARRAY_SIZE(tegra30_audio_plls), 24000000); - tegra_pmc_clk_init(pmc_base, tegra30_clks); tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 416a6b09f6a3..2c9a68302e02 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); -void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, unsigned long *input_freqs, unsigned int num, From patchwork Wed Jan 8 04:25:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A051C33CA1 for ; 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by hqpgpgate102.nvidia.com on Tue, 07 Jan 2020 20:25:41 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:41 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:41 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:40 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 13/21] ASoC: tegra: Use device managed resource APIs to get the clock Date: Tue, 7 Jan 2020 20:25:07 -0800 Message-ID: <1578457515-3477-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457493; bh=6IZliNKUHBe/cwPyc2eEYBkxnyDssTgAbIAybY0sjEU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nLo1bz1Rp6Zf2Swl7USAyC80dduJN1nwjhKVgYEjT8lXg/v6DPz2AF9DGUWuL3DZ9 tf40/6r1d7Rp4ET8JutRThJzlluPdV/kIN0yK4+c04V9lvbNS4lYw/t6ZGm7bB400M gF/bJD+12zV9Si4/nzuJLq7YFgSM3DVnuk0G2u3ep/LJSrjTGO9l+yX75Oo0ApzPix 9ESd49KMR2JFxBqQ1DZoWHM9Np5qf6JmczldveZJXJvDzIubH0/Gb4cwlreOLNQzU0 oVzjmVdZwhyJ4pF3cGiVqaO1Y4xodqgxm2G5TNphr+eYk0U8WV5aqVE6GVNT1jrErB yj/pDs+9tJbVg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org tegra_asoc_utils uses clk_get() and clk_put() to get the clock and to free them explicitly. This patch updates it to use device managed resource API devm_clk_get() so the clock will be automatically released and freed when the device is unbound and removes tegra_asoc_utils_fini() as its no longer needed. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- sound/soc/tegra/tegra_alc5632.c | 7 +------ sound/soc/tegra/tegra_asoc_utils.c | 34 +++++++--------------------------- sound/soc/tegra/tegra_asoc_utils.h | 1 - sound/soc/tegra/tegra_max98090.c | 22 ++++++---------------- sound/soc/tegra/tegra_rt5640.c | 22 ++++++---------------- sound/soc/tegra/tegra_rt5677.c | 7 +------ sound/soc/tegra/tegra_sgtl5000.c | 7 +------ sound/soc/tegra/tegra_wm8753.c | 22 ++++++---------------- sound/soc/tegra/tegra_wm8903.c | 22 ++++++---------------- sound/soc/tegra/tegra_wm9712.c | 8 ++------ sound/soc/tegra/trimslice.c | 18 ++++-------------- 11 files changed, 40 insertions(+), 130 deletions(-) diff --git a/sound/soc/tegra/tegra_alc5632.c b/sound/soc/tegra/tegra_alc5632.c index 9e8b1497efd3..50a6d2ff4442 100644 --- a/sound/soc/tegra/tegra_alc5632.c +++ b/sound/soc/tegra/tegra_alc5632.c @@ -205,13 +205,11 @@ static int tegra_alc5632_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + goto err_put_cpu_of_node; } return 0; -err_fini_utils: - tegra_asoc_utils_fini(&alc5632->util_data); err_put_cpu_of_node: of_node_put(tegra_alc5632_dai.cpus->of_node); tegra_alc5632_dai.cpus->of_node = NULL; @@ -226,12 +224,9 @@ static int tegra_alc5632_probe(struct platform_device *pdev) static int tegra_alc5632_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_alc5632 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - of_node_put(tegra_alc5632_dai.cpus->of_node); tegra_alc5632_dai.cpus->of_node = NULL; tegra_alc5632_dai.platforms->of_node = NULL; diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c index 536a578e9512..0d2271952555 100644 --- a/sound/soc/tegra/tegra_asoc_utils.c +++ b/sound/soc/tegra/tegra_asoc_utils.c @@ -175,52 +175,32 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, return -EINVAL; } - data->clk_pll_a = clk_get(dev, "pll_a"); + data->clk_pll_a = devm_clk_get(dev, "pll_a"); if (IS_ERR(data->clk_pll_a)) { dev_err(data->dev, "Can't retrieve clk pll_a\n"); - ret = PTR_ERR(data->clk_pll_a); - goto err; + return PTR_ERR(data->clk_pll_a); } - data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0"); + data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0"); if (IS_ERR(data->clk_pll_a_out0)) { dev_err(data->dev, "Can't retrieve clk pll_a_out0\n"); - ret = PTR_ERR(data->clk_pll_a_out0); - goto err_put_pll_a; + return PTR_ERR(data->clk_pll_a_out0); } - data->clk_cdev1 = clk_get(dev, "mclk"); + data->clk_cdev1 = devm_clk_get(dev, "mclk"); if (IS_ERR(data->clk_cdev1)) { dev_err(data->dev, "Can't retrieve clk cdev1\n"); - ret = PTR_ERR(data->clk_cdev1); - goto err_put_pll_a_out0; + return PTR_ERR(data->clk_cdev1); } ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100); if (ret) - goto err_put_cdev1; + return ret; return 0; - -err_put_cdev1: - clk_put(data->clk_cdev1); -err_put_pll_a_out0: - clk_put(data->clk_pll_a_out0); -err_put_pll_a: - clk_put(data->clk_pll_a); -err: - return ret; } EXPORT_SYMBOL_GPL(tegra_asoc_utils_init); -void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data) -{ - clk_put(data->clk_cdev1); - clk_put(data->clk_pll_a_out0); - clk_put(data->clk_pll_a); -} -EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini); - MODULE_AUTHOR("Stephen Warren "); MODULE_DESCRIPTION("Tegra ASoC utility code"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h index 0c13818dee75..a34439587d59 100644 --- a/sound/soc/tegra/tegra_asoc_utils.h +++ b/sound/soc/tegra/tegra_asoc_utils.h @@ -34,6 +34,5 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data); int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, struct device *dev); -void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data); #endif diff --git a/sound/soc/tegra/tegra_max98090.c b/sound/soc/tegra/tegra_max98090.c index 4954a33ff46b..f554a3d4571f 100644 --- a/sound/soc/tegra/tegra_max98090.c +++ b/sound/soc/tegra/tegra_max98090.c @@ -218,19 +218,18 @@ static int tegra_max98090_probe(struct platform_device *pdev) ret = snd_soc_of_parse_card_name(card, "nvidia,model"); if (ret) - goto err; + return ret; ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing"); if (ret) - goto err; + return ret; tegra_max98090_dai.codecs->of_node = of_parse_phandle(np, "nvidia,audio-codec", 0); if (!tegra_max98090_dai.codecs->of_node) { dev_err(&pdev->dev, "Property 'nvidia,audio-codec' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_max98090_dai.cpus->of_node = of_parse_phandle(np, @@ -238,40 +237,31 @@ static int tegra_max98090_probe(struct platform_device *pdev) if (!tegra_max98090_dai.cpus->of_node) { dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_max98090_dai.platforms->of_node = tegra_max98090_dai.cpus->of_node; ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); if (ret) - goto err; + return ret; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + return ret; } return 0; - -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); -err: - return ret; } static int tegra_max98090_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_max98090 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - return 0; } diff --git a/sound/soc/tegra/tegra_rt5640.c b/sound/soc/tegra/tegra_rt5640.c index d46915a3ec4c..5c695dfea009 100644 --- a/sound/soc/tegra/tegra_rt5640.c +++ b/sound/soc/tegra/tegra_rt5640.c @@ -164,19 +164,18 @@ static int tegra_rt5640_probe(struct platform_device *pdev) ret = snd_soc_of_parse_card_name(card, "nvidia,model"); if (ret) - goto err; + return ret; ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing"); if (ret) - goto err; + return ret; tegra_rt5640_dai.codecs->of_node = of_parse_phandle(np, "nvidia,audio-codec", 0); if (!tegra_rt5640_dai.codecs->of_node) { dev_err(&pdev->dev, "Property 'nvidia,audio-codec' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_rt5640_dai.cpus->of_node = of_parse_phandle(np, @@ -184,40 +183,31 @@ static int tegra_rt5640_probe(struct platform_device *pdev) if (!tegra_rt5640_dai.cpus->of_node) { dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_rt5640_dai.platforms->of_node = tegra_rt5640_dai.cpus->of_node; ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); if (ret) - goto err; + return ret; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + return ret; } return 0; - -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); -err: - return ret; } static int tegra_rt5640_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - return 0; } diff --git a/sound/soc/tegra/tegra_rt5677.c b/sound/soc/tegra/tegra_rt5677.c index 81cb6cc6236e..fb86f76728b3 100644 --- a/sound/soc/tegra/tegra_rt5677.c +++ b/sound/soc/tegra/tegra_rt5677.c @@ -270,13 +270,11 @@ static int tegra_rt5677_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + goto err_put_cpu_of_node; } return 0; -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); err_put_cpu_of_node: of_node_put(tegra_rt5677_dai.cpus->of_node); tegra_rt5677_dai.cpus->of_node = NULL; @@ -291,12 +289,9 @@ static int tegra_rt5677_probe(struct platform_device *pdev) static int tegra_rt5677_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - tegra_rt5677_dai.platforms->of_node = NULL; of_node_put(tegra_rt5677_dai.codecs->of_node); tegra_rt5677_dai.codecs->of_node = NULL; diff --git a/sound/soc/tegra/tegra_sgtl5000.c b/sound/soc/tegra/tegra_sgtl5000.c index e13b81d29cf3..586f56f435f4 100644 --- a/sound/soc/tegra/tegra_sgtl5000.c +++ b/sound/soc/tegra/tegra_sgtl5000.c @@ -156,13 +156,11 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + goto err_put_cpu_of_node; } return 0; -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); err_put_cpu_of_node: of_node_put(tegra_sgtl5000_dai.cpus->of_node); tegra_sgtl5000_dai.cpus->of_node = NULL; @@ -177,13 +175,10 @@ static int tegra_sgtl5000_driver_probe(struct platform_device *pdev) static int tegra_sgtl5000_driver_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_sgtl5000 *machine = snd_soc_card_get_drvdata(card); int ret; ret = snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - of_node_put(tegra_sgtl5000_dai.cpus->of_node); tegra_sgtl5000_dai.cpus->of_node = NULL; tegra_sgtl5000_dai.platforms->of_node = NULL; diff --git a/sound/soc/tegra/tegra_wm8753.c b/sound/soc/tegra/tegra_wm8753.c index f6dd790dad71..f76cfdc963ed 100644 --- a/sound/soc/tegra/tegra_wm8753.c +++ b/sound/soc/tegra/tegra_wm8753.c @@ -127,19 +127,18 @@ static int tegra_wm8753_driver_probe(struct platform_device *pdev) ret = snd_soc_of_parse_card_name(card, "nvidia,model"); if (ret) - goto err; + return ret; ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing"); if (ret) - goto err; + return ret; tegra_wm8753_dai.codecs->of_node = of_parse_phandle(np, "nvidia,audio-codec", 0); if (!tegra_wm8753_dai.codecs->of_node) { dev_err(&pdev->dev, "Property 'nvidia,audio-codec' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_wm8753_dai.cpus->of_node = of_parse_phandle(np, @@ -147,40 +146,31 @@ static int tegra_wm8753_driver_probe(struct platform_device *pdev) if (!tegra_wm8753_dai.cpus->of_node) { dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_wm8753_dai.platforms->of_node = tegra_wm8753_dai.cpus->of_node; ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); if (ret) - goto err; + return ret; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + return ret; } return 0; - -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); -err: - return ret; } static int tegra_wm8753_driver_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - return 0; } diff --git a/sound/soc/tegra/tegra_wm8903.c b/sound/soc/tegra/tegra_wm8903.c index f08d3489c3cf..f5f78c3512cd 100644 --- a/sound/soc/tegra/tegra_wm8903.c +++ b/sound/soc/tegra/tegra_wm8903.c @@ -301,19 +301,18 @@ static int tegra_wm8903_driver_probe(struct platform_device *pdev) ret = snd_soc_of_parse_card_name(card, "nvidia,model"); if (ret) - goto err; + return ret; ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing"); if (ret) - goto err; + return ret; tegra_wm8903_dai.codecs->of_node = of_parse_phandle(np, "nvidia,audio-codec", 0); if (!tegra_wm8903_dai.codecs->of_node) { dev_err(&pdev->dev, "Property 'nvidia,audio-codec' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_wm8903_dai.cpus->of_node = of_parse_phandle(np, @@ -321,40 +320,31 @@ static int tegra_wm8903_driver_probe(struct platform_device *pdev) if (!tegra_wm8903_dai.cpus->of_node) { dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } tegra_wm8903_dai.platforms->of_node = tegra_wm8903_dai.cpus->of_node; ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev); if (ret) - goto err; + return ret; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + return ret; } return 0; - -err_fini_utils: - tegra_asoc_utils_fini(&machine->util_data); -err: - return ret; } static int tegra_wm8903_driver_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_wm8903 *machine = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - return 0; } diff --git a/sound/soc/tegra/tegra_wm9712.c b/sound/soc/tegra/tegra_wm9712.c index b85bd9f89073..726edfa21a29 100644 --- a/sound/soc/tegra/tegra_wm9712.c +++ b/sound/soc/tegra/tegra_wm9712.c @@ -113,19 +113,17 @@ static int tegra_wm9712_driver_probe(struct platform_device *pdev) ret = tegra_asoc_utils_set_ac97_rate(&machine->util_data); if (ret) - goto asoc_utils_fini; + goto codec_unregister; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto asoc_utils_fini; + goto codec_unregister; } return 0; -asoc_utils_fini: - tegra_asoc_utils_fini(&machine->util_data); codec_unregister: platform_device_del(machine->codec); codec_put: @@ -140,8 +138,6 @@ static int tegra_wm9712_driver_remove(struct platform_device *pdev) snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&machine->util_data); - platform_device_unregister(machine->codec); return 0; diff --git a/sound/soc/tegra/trimslice.c b/sound/soc/tegra/trimslice.c index 3f67ddd13674..e51c67092c8f 100644 --- a/sound/soc/tegra/trimslice.c +++ b/sound/soc/tegra/trimslice.c @@ -125,8 +125,7 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev) if (!trimslice_tlv320aic23_dai.codecs->of_node) { dev_err(&pdev->dev, "Property 'nvidia,audio-codec' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } trimslice_tlv320aic23_dai.cpus->of_node = of_parse_phandle(np, @@ -134,8 +133,7 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev) if (!trimslice_tlv320aic23_dai.cpus->of_node) { dev_err(&pdev->dev, "Property 'nvidia,i2s-controller' missing or invalid\n"); - ret = -EINVAL; - goto err; + return -EINVAL; } trimslice_tlv320aic23_dai.platforms->of_node = @@ -143,32 +141,24 @@ static int tegra_snd_trimslice_probe(struct platform_device *pdev) ret = tegra_asoc_utils_init(&trimslice->util_data, &pdev->dev); if (ret) - goto err; + return ret; ret = snd_soc_register_card(card); if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto err_fini_utils; + return ret; } return 0; - -err_fini_utils: - tegra_asoc_utils_fini(&trimslice->util_data); -err: - return ret; } static int tegra_snd_trimslice_remove(struct platform_device *pdev) { struct snd_soc_card *card = platform_get_drvdata(pdev); - struct tegra_trimslice *trimslice = snd_soc_card_get_drvdata(card); snd_soc_unregister_card(card); - tegra_asoc_utils_fini(&trimslice->util_data); - return 0; } From patchwork Wed Jan 8 04:25:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4FBC33C9B for ; Wed, 8 Jan 2020 04:26:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0D68B2082E for ; Wed, 8 Jan 2020 04:26:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="pEvacgor" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727192AbgAHEZp (ORCPT ); Tue, 7 Jan 2020 23:25:45 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12513 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727160AbgAHEZp (ORCPT ); Tue, 7 Jan 2020 23:25:45 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jan 2020 20:25:25 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 07 Jan 2020 20:25:43 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 07 Jan 2020 20:25:43 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:42 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:42 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 14/21] ASoC: tegra: Add audio mclk configuration Date: Tue, 7 Jan 2020 20:25:08 -0800 Message-ID: <1578457515-3477-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457526; bh=m+gZRCVCHwwlD6DIxFUXm3S0ytbxXl7njrAzJGueztg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=pEvacgoruF44Y8IWLnz/FetBnrbBXtH54U50j60WKloBy3BzGB1amTUDiZRZcc74o fllUCOwN8i3lZjtGEFVSJf6aMavdF+gRy2BkTm5uMAucrVBFSBjImK3FXUHeR9BOyh xuIajlBlcQvrGnXWSEK3bKc1FB9/Bu5Tvek6A1vHGtBRMdqPEfqI5qp4FZUi5X4NLH +vh06EyEddYYh7HyEha0QVcty07rCzoABXx6RHvlPjQwyuiFW6BcFoBsjHXXPZcaOu ydYgsydUesxQ40gFcpinn9IHf/oX7IKRDVznH9cecsNRS8WlNAc6b9RoEDbqk+mX/V 1iN5sATYphD4Q== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 through Tegra210 and currently Tegra clock driver does the initial parent configuration for audio mclk and keeps it enabled by default. With the move of PMC clocks from clock driver into pmc driver, audio clocks parent configuration can be specified through the device tree using assigned-clock-parents property and audio mclk control should be taken care by the audio driver. This patch has implementation for parent configuration when default parent configuration is not specified in the device tree and controls audio mclk enable and disable during machine startup and shutdown. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- sound/soc/tegra/tegra_alc5632.c | 18 ++++++++ sound/soc/tegra/tegra_asoc_utils.c | 88 +++++++++++++++++++++++++------------- sound/soc/tegra/tegra_asoc_utils.h | 2 + sound/soc/tegra/tegra_max98090.c | 18 ++++++++ sound/soc/tegra/tegra_rt5640.c | 18 ++++++++ sound/soc/tegra/tegra_rt5677.c | 18 ++++++++ sound/soc/tegra/tegra_sgtl5000.c | 18 ++++++++ sound/soc/tegra/tegra_wm8753.c | 18 ++++++++ sound/soc/tegra/tegra_wm8903.c | 18 ++++++++ sound/soc/tegra/trimslice.c | 18 ++++++++ 10 files changed, 204 insertions(+), 30 deletions(-) diff --git a/sound/soc/tegra/tegra_alc5632.c b/sound/soc/tegra/tegra_alc5632.c index 50a6d2ff4442..5da7933f6a99 100644 --- a/sound/soc/tegra/tegra_alc5632.c +++ b/sound/soc/tegra/tegra_alc5632.c @@ -62,8 +62,26 @@ static int tegra_alc5632_asoc_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_alc5632_asoc_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_alc5632 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_alc5632_asoc_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_alc5632 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_alc5632_asoc_ops = { + .startup = tegra_alc5632_asoc_startup, .hw_params = tegra_alc5632_asoc_hw_params, + .shutdown = tegra_alc5632_asoc_shutdown, }; static struct snd_soc_jack tegra_alc5632_hs_jack; diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c index 0d2271952555..9cfebef74870 100644 --- a/sound/soc/tegra/tegra_asoc_utils.c +++ b/sound/soc/tegra/tegra_asoc_utils.c @@ -60,8 +60,6 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, data->set_mclk = 0; clk_disable_unprepare(data->clk_cdev1); - clk_disable_unprepare(data->clk_pll_a_out0); - clk_disable_unprepare(data->clk_pll_a); err = clk_set_rate(data->clk_pll_a, new_baseclock); if (err) { @@ -77,18 +75,6 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ - err = clk_prepare_enable(data->clk_pll_a); - if (err) { - dev_err(data->dev, "Can't enable pll_a: %d\n", err); - return err; - } - - err = clk_prepare_enable(data->clk_pll_a_out0); - if (err) { - dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); - return err; - } - err = clk_prepare_enable(data->clk_cdev1); if (err) { dev_err(data->dev, "Can't enable cdev1: %d\n", err); @@ -109,8 +95,6 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data) int err; clk_disable_unprepare(data->clk_cdev1); - clk_disable_unprepare(data->clk_pll_a_out0); - clk_disable_unprepare(data->clk_pll_a); /* * AC97 rate is fixed at 24.576MHz and is used for both the host @@ -130,17 +114,28 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data) /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */ - err = clk_prepare_enable(data->clk_pll_a); + err = clk_prepare_enable(data->clk_cdev1); if (err) { - dev_err(data->dev, "Can't enable pll_a: %d\n", err); + dev_err(data->dev, "Can't enable cdev1: %d\n", err); return err; } - err = clk_prepare_enable(data->clk_pll_a_out0); - if (err) { - dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err); - return err; - } + data->set_baseclock = pll_rate; + data->set_mclk = ac97_rate; + + return 0; +} +EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate); + +void tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data) +{ + clk_disable_unprepare(data->clk_cdev1); +} +EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_disable); + +int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data) +{ + int err; err = clk_prepare_enable(data->clk_cdev1); if (err) { @@ -148,16 +143,14 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data) return err; } - data->set_baseclock = pll_rate; - data->set_mclk = ac97_rate; - return 0; } -EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate); +EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_enable); int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, struct device *dev) { + struct clk *clk_out_1, *clk_extern1; int ret; data->dev = dev; @@ -193,9 +186,44 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, return PTR_ERR(data->clk_cdev1); } - ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100); - if (ret) - return ret; + /* + * If clock parents are not set in DT, configure here to use clk_out_1 + * as mclk and extern1 as parent for Tegra30 and higher. + */ + if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) && + data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) { + dev_warn(data->dev, + "Configuring clocks for a legacy device-tree\n"); + dev_warn(data->dev, + "Please update DT to use assigned-clock-parents\n"); + clk_extern1 = devm_clk_get(dev, "extern1"); + if (IS_ERR(clk_extern1)) { + dev_err(data->dev, "Can't retrieve clk extern1\n"); + return PTR_ERR(clk_extern1); + } + + ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0); + if (ret < 0) { + dev_err(data->dev, + "Set parent failed for clk extern1\n"); + return ret; + } + + clk_out_1 = devm_clk_get(dev, "clk_out_1"); + if (IS_ERR(clk_out_1)) { + dev_err(data->dev, "Can't retrieve clk clk_out_1\n"); + return PTR_ERR(clk_out_1); + } + + ret = clk_set_parent(clk_out_1, clk_extern1); + if (ret < 0) { + dev_err(data->dev, + "Set parent failed for clk_out_1\n"); + return ret; + } + + data->clk_cdev1 = clk_out_1; + } return 0; } diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h index a34439587d59..6db93009a317 100644 --- a/sound/soc/tegra/tegra_asoc_utils.h +++ b/sound/soc/tegra/tegra_asoc_utils.h @@ -34,5 +34,7 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate, int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data); int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data, struct device *dev); +int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data); +void tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data); #endif diff --git a/sound/soc/tegra/tegra_max98090.c b/sound/soc/tegra/tegra_max98090.c index f554a3d4571f..ec43b27ca3f7 100644 --- a/sound/soc/tegra/tegra_max98090.c +++ b/sound/soc/tegra/tegra_max98090.c @@ -82,8 +82,26 @@ static int tegra_max98090_asoc_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_max98090_asoc_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_max98090 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_max98090_asoc_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_max98090 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_max98090_ops = { + .startup = tegra_max98090_asoc_startup, .hw_params = tegra_max98090_asoc_hw_params, + .shutdown = tegra_max98090_asoc_shutdown, }; static struct snd_soc_jack tegra_max98090_hp_jack; diff --git a/sound/soc/tegra/tegra_rt5640.c b/sound/soc/tegra/tegra_rt5640.c index 5c695dfea009..2d63ab0987ea 100644 --- a/sound/soc/tegra/tegra_rt5640.c +++ b/sound/soc/tegra/tegra_rt5640.c @@ -65,8 +65,26 @@ static int tegra_rt5640_asoc_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_rt5640_asoc_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_rt5640_asoc_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_rt5640 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_rt5640_ops = { + .startup = tegra_rt5640_asoc_startup, .hw_params = tegra_rt5640_asoc_hw_params, + .shutdown = tegra_rt5640_asoc_shutdown, }; static struct snd_soc_jack tegra_rt5640_hp_jack; diff --git a/sound/soc/tegra/tegra_rt5677.c b/sound/soc/tegra/tegra_rt5677.c index fb86f76728b3..81485dbe4ec6 100644 --- a/sound/soc/tegra/tegra_rt5677.c +++ b/sound/soc/tegra/tegra_rt5677.c @@ -82,8 +82,26 @@ static int tegra_rt5677_event_hp(struct snd_soc_dapm_widget *w, return 0; } +static int tegra_rt5677_asoc_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_rt5677_asoc_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_rt5677 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_rt5677_ops = { + .startup = tegra_rt5677_asoc_startup, .hw_params = tegra_rt5677_asoc_hw_params, + .shutdown = tegra_rt5677_asoc_shutdown, }; static struct snd_soc_jack tegra_rt5677_hp_jack; diff --git a/sound/soc/tegra/tegra_sgtl5000.c b/sound/soc/tegra/tegra_sgtl5000.c index 586f56f435f4..8852a4bcafe7 100644 --- a/sound/soc/tegra/tegra_sgtl5000.c +++ b/sound/soc/tegra/tegra_sgtl5000.c @@ -71,8 +71,26 @@ static int tegra_sgtl5000_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_sgtl5000_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_sgtl5000 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_sgtl5000_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_sgtl5000 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_sgtl5000_ops = { + .startup = tegra_sgtl5000_startup, .hw_params = tegra_sgtl5000_hw_params, + .shutdown = tegra_sgtl5000_shutdown, }; static const struct snd_soc_dapm_widget tegra_sgtl5000_dapm_widgets[] = { diff --git a/sound/soc/tegra/tegra_wm8753.c b/sound/soc/tegra/tegra_wm8753.c index f76cfdc963ed..a4595d73df53 100644 --- a/sound/soc/tegra/tegra_wm8753.c +++ b/sound/soc/tegra/tegra_wm8753.c @@ -75,8 +75,26 @@ static int tegra_wm8753_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_wm8753_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_wm8753_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_wm8753_ops = { + .startup = tegra_wm8753_startup, .hw_params = tegra_wm8753_hw_params, + .shutdown = tegra_wm8753_shutdown, }; static const struct snd_soc_dapm_widget tegra_wm8753_dapm_widgets[] = { diff --git a/sound/soc/tegra/tegra_wm8903.c b/sound/soc/tegra/tegra_wm8903.c index f5f78c3512cd..9cd637385685 100644 --- a/sound/soc/tegra/tegra_wm8903.c +++ b/sound/soc/tegra/tegra_wm8903.c @@ -82,8 +82,26 @@ static int tegra_wm8903_hw_params(struct snd_pcm_substream *substream, return 0; } +static int tegra_wm8903_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_wm8903 *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void tegra_wm8903_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_wm8903 *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops tegra_wm8903_ops = { + .startup = tegra_wm8903_startup, .hw_params = tegra_wm8903_hw_params, + .shutdown = tegra_wm8903_shutdown, }; static struct snd_soc_jack tegra_wm8903_hp_jack; diff --git a/sound/soc/tegra/trimslice.c b/sound/soc/tegra/trimslice.c index e51c67092c8f..a78c2bc633bc 100644 --- a/sound/soc/tegra/trimslice.c +++ b/sound/soc/tegra/trimslice.c @@ -60,8 +60,26 @@ static int trimslice_asoc_hw_params(struct snd_pcm_substream *substream, return 0; } +static int trimslice_asoc_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_trimslice *machine = snd_soc_card_get_drvdata(rtd->card); + + return tegra_asoc_utils_clk_enable(&machine->util_data); +} + +static void trimslice_asoc_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct tegra_trimslice *machine = snd_soc_card_get_drvdata(rtd->card); + + tegra_asoc_utils_clk_disable(&machine->util_data); +} + static const struct snd_soc_ops trimslice_asoc_ops = { + .startup = trimslice_asoc_startup, .hw_params = trimslice_asoc_hw_params, + .shutdown = trimslice_asoc_shutdown, }; static const struct snd_soc_dapm_widget trimslice_dapm_widgets[] = { From patchwork Wed Jan 8 04:25:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E444C00523 for ; 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by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:50 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:49 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:49 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:48 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 18/21] arm64: tegra: Add clock-cells property to Tegra PMC node Date: Tue, 7 Jan 2020 20:25:12 -0800 Message-ID: <1578457515-3477-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457501; bh=gkcJtn8jnkfrlt7lseMCLMoUPqIVSBgfxdajsl9lga0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=XKz7IFlIsDGQi9ot4LNla9E9F1vGheBUVWgHSc4vGynokj2+9xNBWeT6t8uIPJDo3 igux7YAsiHaYRnAiDdOOEImMEYNN8tWse9TGcyf/fnkGXsV23dmBs7/Q+Y1dd7p+Lk pmviUOG3KNs8PRoxl+qwzFCb4IIST5i2kdyJgOCpW5grgIwiCjTTkVpooHN6Ng18bw 0nENrJyUJWfTh8ifrWhupFtEgq8t0aUiU/jlFQ8o82z/T8tLK59qkBVeRYmi3zNav2 OwCsABdPpHxkXMRVJfvhl3my5ivHNUhvzxZuirdku8vBMVvFVhTv1+W63CwbrjDJ51 xnKmE20afJk6A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of PMC. These clocks are moved from clock driver to pmc driver with pmc as a clock provider. Clock ids for these clocks are defined in pmc dt-bindings. This patch updated device tree to include pmc dt-binding and adds #clock-cells property with one clock specifier to pmc node. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 631a7f77c386..79b1e3b01096 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra132", "nvidia,tegra124"; @@ -577,11 +578,12 @@ clock-names = "rtc"; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c63256ba7f..3e73b76249f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra210"; @@ -770,16 +771,17 @@ compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pmc>; + interrupt-parent = <&tegra_pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; - pmc: pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; #interrupt-cells = <2>; interrupt-controller; From patchwork Wed Jan 8 04:25:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855FCC33CA1 for ; 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by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:51 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:51 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:50 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:50 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 19/21] ARM: tegra: Update sound node clocks in device tree Date: Tue, 7 Jan 2020 20:25:13 -0800 Message-ID: <1578457515-3477-20-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457503; bh=FN4ZiQi/2hJBTxgG+wfpARAjBcj3lxvrxBiMdHaXFdA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZpOz69AsJgnq7s/HoQUWo+8t25t1OKzUqbHmPScWgYPV0bXNyjzQ8xGS8MjzveX2A xkXWAIJjtaPFudNeee13C1RtrQlnJcwvTX5hClv9X3FIBO7iFZs1WYZ9ilw0OKvGMi NQUgQt3F0kmzWM/Kc/cvPhagFmhmaKlWvrsj9IumjOuob7SbFMmmNlVfEs1x+mZui0 wZfk4VtG9yBNmArcL73B2pLN7jF0oBJQhDCUT6lKnuhBu1ZnGfg9rQXpuMDG9UTgDt Da2j+vkMOa2ePHQ7+7QJ57bK5sfBnx4HCgzCfF7k6vaMwGK1fQeCiM7764gzTQ9fmg AvmoHmQw5kThQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block and are moved from clock driver to pmc driver with pmc as clock provider. clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210. This patch updates device tree sound node to use clk_out_1 from pmc provider as mclk and uses assigned-clock properties to specify clock parents for clk_out_1 and extern1. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- arch/arm/boot/dts/tegra114-dalmore.dts | 8 +++++++- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 8 +++++++- arch/arm/boot/dts/tegra124-apalis.dtsi | 8 +++++++- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +++++++- arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +++++++- arch/arm/boot/dts/tegra124-venice2.dts | 8 +++++++- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 8 +++++++- arch/arm/boot/dts/tegra30-apalis.dtsi | 8 +++++++- arch/arm/boot/dts/tegra30-beaver.dts | 8 +++++++- arch/arm/boot/dts/tegra30-cardhu.dtsi | 8 +++++++- arch/arm/boot/dts/tegra30-colibri.dtsi | 8 +++++++- 11 files changed, 77 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 97a5c3504bbe..d3e032e7d21a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1296,7 +1296,13 @@ clocks = <&tegra_car TEGRA114_CLK_PLL_A>, <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 0462ed2dd8b8..de499f736bda 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2009,8 +2009,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d1e8593ef0d9..d70a86da4ee4 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2001,8 +2001,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index d5fd642f8b77..aaf8f6a56ca8 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -2058,8 +2058,14 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 3b10f475037f..9b1af50cd4b8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -788,9 +788,15 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7309393bfced..8c2ee6e7d6f1 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1266,8 +1266,14 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 8b7a827d604d..387b17458e22 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1189,7 +1189,13 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index c18f6f61d764..6648506f3aa4 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1171,7 +1171,13 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..45ef6002b225 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2111,7 +2111,13 @@ clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 7ce61edd52f5..4b4f49a49394 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -619,8 +619,14 @@ clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 1f9198bb24ff..adba554381c7 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1030,8 +1030,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; From patchwork Wed Jan 8 04:25:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 206031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1D9DC00523 for ; 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by hqpgpgate102.nvidia.com on Tue, 07 Jan 2020 20:25:54 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:53 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:53 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jan 2020 20:25:53 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 21/21] ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc Date: Tue, 7 Jan 2020 20:25:15 -0800 Message-ID: <1578457515-3477-22-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457536; bh=pWNZAo13Br7GvFxHxRFIS/1sozX6HF632kX/lxY43iQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=NFkGm820zbY010IcHMC5idC6pN9XMW/B7u/1UVUjVw3kSpwdoCesS38MFXmORb1wD 0JKF+xvJOGoPt/2IYWIbPcejn9m1P5LGbR6h8sUa7Th8hp+i0sG2otGiz7D+HaR+6Y KoE6qNR6Z9KcgqTNmbx+3+o5ox9W75jU1brrdpDTSk4xTcOeCL7FrEN7XrHhjiUgPd X9YESHjIlC0Ef8wskMMZoyCjmu+szWoY/+RyUQpqeznr+BOGoo3gIMcrjQ+ECWbR5e 2Vfmv3x06GDumeVhCUBch7pl+jMn/1D+DDS14/ev0X2JYBAE6ib89+VWgmZTVP/lC0 +D3xtfmLHdJ2w== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra clk_out_1, clk_out_2, and clk_out_3 are part of PMC block and these clocks are moved from clock drvier to pmc driver with pmc as a provider for these clocks. Update bindings document to use pmc as clock provider for clk_out_2 and change id to pmc clock id. Reviewed-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/sound/nau8825.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt index d16d96839bcb..388a7bc60b1f 100644 --- a/Documentation/devicetree/bindings/sound/nau8825.txt +++ b/Documentation/devicetree/bindings/sound/nau8825.txt @@ -101,5 +101,5 @@ Example: nuvoton,crosstalk-enable; clock-names = "mclk"; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; };