From patchwork Fri Jan 10 11:54:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 205888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22E15C33CA2 for ; Fri, 10 Jan 2020 11:54:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 03AAD2072A for ; Fri, 10 Jan 2020 11:54:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728192AbgAJLyo (ORCPT ); Fri, 10 Jan 2020 06:54:44 -0500 Received: from foss.arm.com ([217.140.110.172]:43228 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728183AbgAJLyn (ORCPT ); Fri, 10 Jan 2020 06:54:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C452D1474; Fri, 10 Jan 2020 03:54:42 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48F7D3F534; Fri, 10 Jan 2020 03:54:41 -0800 (PST) From: Andre Przywara To: "David S . Miller" , Radhey Shyam Pandey Cc: Michal Simek , Robert Hancock , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 14/14] net: axienet: Update devicetree binding documentation Date: Fri, 10 Jan 2020 11:54:15 +0000 Message-Id: <20200110115415.75683-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200110115415.75683-1-andre.przywara@arm.com> References: <20200110115415.75683-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds documentation about the newly introduced, optional "xlnx,addrwidth" property to the binding documentation. While at it, clarify the wording on some properties, replace obsolete .txt file references with their new .yaml counterparts, and add a more modern example, using the axistream-connected property. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Andre Przywara --- .../bindings/net/xilinx_axienet.txt | 57 ++++++++++++++++--- 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt index 7360617cdedb..78c278c5200f 100644 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt @@ -12,7 +12,8 @@ sent and received through means of an AXI DMA controller. This driver includes the DMA driver code, so this driver is incompatible with AXI DMA driver. -For more details about mdio please refer phy.txt file in the same directory. +For more details about mdio please refer to the ethernet-phy.yaml file in +the same directory. Required properties: - compatible : Must be one of "xlnx,axi-ethernet-1.00.a", @@ -27,14 +28,14 @@ Required properties: instead, and only the Ethernet core interrupt is optionally specified here. - phy-handle : Should point to the external phy device. - See ethernet.txt file in the same directory. -- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware + See the ethernet-controller.yaml file in the same directory. +- xlnx,rxmem : Size of the RXMEM buffer in the hardware, in bytes. Optional properties: -- phy-mode : See ethernet.txt +- phy-mode : See ethernet-controller.yaml. - xlnx,phy-type : Deprecated, do not use, but still accepted in preference to phy-mode. -- xlnx,txcsum : 0 or empty for disabling TX checksum offload, +- xlnx,txcsum : 0 for disabling TX checksum offload (default if omitted), 1 to enable partial TX checksum offload, 2 to enable full TX checksum offload - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload @@ -48,10 +49,20 @@ Optional properties: If this is specified, the DMA-related resources from that device (DMA registers and DMA TX/RX interrupts) rather than this one will be used. - - mdio : Child node for MDIO bus. Must be defined if PHY access is +- mdio : Child node for MDIO bus. Must be defined if PHY access is required through the core's MDIO interface (i.e. always, unless the PHY is accessed through a different bus). +Required properties for axistream-connected subnode: +- reg : Address and length of the AXI DMA controller MMIO space. +- interrupts : A list of 2 interrupts: TX DMA and RX DMA, in that order. + +Optional properties for axistream-connected subnode: +- xlnx,addrwidth: Specifies the configured address width of the DMA. Newer + versions of the IP allow setting this to a value between + 32 and 64. Defaults to 32 bits if not specified. + + Example: axi_ethernet_eth: ethernet@40c00000 { compatible = "xlnx,axi-ethernet-1.00.a"; @@ -60,7 +71,7 @@ Example: interrupts = <2 0 1>; clocks = <&axi_clk>; phy-mode = "mii"; - reg = <0x40c00000 0x40000 0x50c00000 0x40000>; + reg = <0x40c00000 0x40000>, <0x50c00000 0x40000>; xlnx,rxcsum = <0x2>; xlnx,rxmem = <0x800>; xlnx,txcsum = <0x2>; @@ -74,3 +85,35 @@ Example: }; }; }; + ----------------- + axi_ethernet_eth: ethernet@7fe00000 { + compatible = "acme,fpga-ethernet", "xlnx,axi-ethernet-1.00.a"; + reg = <0 0x7fe00000 0 0x40000>; + interrupts = ; + clocks = <&soc_refclk100mhz>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + xlnx,rxmem = <4096>; + axistream-connected = <&axi_dma_eth>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + axi_dma_eth: axi_dma_ethernet@7fe40000 { + reg = <0 0x7fe40000 0 0x10000>; + interrupts = , + ; + xlnx,addrwidth = <40>; + }; + + axi_ethernetlite_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + };