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Date: Wed, 22 Jan 2020 11:45:05 +0100 Message-ID: <1579689918-7181-2-git-send-email-yamonkar@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> References: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(376002)(346002)(39860400002)(136003)(396003)(36092001)(189003)(199004)(2906002)(246002)(4326008)(86362001)(8676002)(7636002)(186003)(5660300002)(426003)(2616005)(336012)(8936002)(26005)(6666004)(107886003)(110136005)(54906003)(316002)(356004)(42186006)(70586007)(26826003)(70206006)(478600001)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR07MB7340; H:sjmaillnx1.cadence.com; FPR:; SPF:Pass; LANG:en; PTR:corp.cadence.com; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 181ff02a-4692-421f-0655-08d79f282f84 X-MS-TrafficTypeDiagnostic: DM6PR07MB7340: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-Forefront-PRVS: 029097202E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q405xZUgxC7pSx8l9TvV9g49+9U9lnUBa9k7aJYyhESHJjzVA0Jqy0kk9nx8zEqBR3r/zzUHcB9zk3p2Ewz3yluURAHJAyP1IyhK4dJa4xrrHCS0pkRtIoM/wdsjblaDgh9RrM5SWMw9lk5aNwCxQyIP3dwhe2mcZmaF3d1V71PbzeDbFzim3SGTyzSNQAKchvmoG5Kqaeh/YhNvfe0qDzGeZIxkcjNfjhDs300EQw8fvKANP4gsMAZ65ksUGTfN21It2aRNJw9hJf81HTKdvywHX7RNnZTwZis/0V8v/0RY+y5F692R5owz79Lg3kHjgNlnZwVMuQ5I2ZxNMMMy9OCw1QwExv1AQYFn9bsma7Msa14CFJjyrGrnKSC2G5i/waLRGZ0WZLRzHyZwoIPD7r7KUGRv6hY6ddFxe/bzKhZ9vT7ViOUVxSyo/CWFKwW1bXHM9z3wPvd7qFiou3qtMme+GM8YyLHO/QDK/9LnN9zsua5KbZaJDmVJFuys6nS2OnxCtfOFJvWGvosuMx8FAA== X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2020 10:45:23.9814 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 181ff02a-4692-421f-0655-08d79f282f84 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9; Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB7340 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org - Convert the MHDP PHY devicetree bindings to yaml schemas. - Rename DP PHY to have generic Torrent PHY nomrnclature. - Add Torrent PHY reference clock bindings. - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy". This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case Signed-off-by: Yuti Amonkar --- .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 -------- .../bindings/phy/phy-cadence-torrent.yaml | 82 ++++++++++++++++++++++ 2 files changed, 82 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt deleted file mode 100644 index 7f49fd54e..0000000 --- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt +++ /dev/null @@ -1,30 +0,0 @@ -Cadence MHDP DisplayPort SD0801 PHY binding -=========================================== - -This binding describes the Cadence SD0801 PHY hardware included with -the Cadence MHDP DisplayPort controller. - -------------------------------------------------------------------------------- -Required properties (controller (parent) node): -- compatible : Should be "cdns,dp-phy" -- reg : Defines the following sets of registers in the parent - mhdp device: - - Offset of the DPTX PHY configuration registers - - Offset of the SD0801 PHY configuration registers -- #phy-cells : from the generic PHY bindings, must be 0. - -Optional properties: -- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4) -- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160, - 2430, 2700, 3240, 4320, 5400 or 8100) -------------------------------------------------------------------------------- - -Example: - dp_phy: phy@f0fb030a00 { - compatible = "cdns,dp-phy"; - reg = <0xf0 0xfb030a00 0x0 0x00000040>, - <0xf0 0xfb500000 0x0 0x00100000>; - num_lanes = <4>; - max_bit_rate = <8100>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml new file mode 100644 index 0000000..eb633d7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -0,0 +1,82 @@ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence Torrent SD0801 PHY binding for DisplayPort + +description: + This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) + hardware included with the Cadence MHDP DisplayPort controller. + +maintainers: + - Swapnil Jakhade + - Yuti Amonkar + +properties: + compatible: + const: cdns,torrent-phy + + clocks: + maxItems: 1 + description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: + const: refclk + + reg: + minItems: 1 + maxItems: 2 + items: + - description: Offset of the Torrent PHY configuration registers. + - description: Offset of the DPTX PHY configuration registers. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: torrent_phy + - const: dptx_phy + + "#phy-cells": + const: 0 + + num_lanes: + description: + Number of DisplayPort lanes. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2, 4] + + max_bit_rate: + description: + Maximum DisplayPort link bit rate to use, in Mbps + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + dp_phy: phy@f0fb500000 { + compatible = "cdns,torrent-phy"; + reg = <0xf0 0xfb500000 0x0 0x00100000>, + <0xf0 0xfb030a00 0x0 0x00000040>; + reg-names = "torrent_phy", "dptx_phy"; + num_lanes = <4>; + max_bit_rate = <8100>; + #phy-cells = <0>; + clocks = <&ref_clk>; + clock-names = "refclk"; + }; +... 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR07MB2732 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade - Change private data struct cdns_dp_phy to cdns_torrent_phy - Change module description and registration accordingly - Generic torrent functions have prefix cdns_torrent_phy_* - Functions specific to Torrent phy for DisplayPort are prefixed as cdns_torrent_dp_* Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 111 ++++++++++++++++-------------- 1 file changed, 58 insertions(+), 53 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index beb80f7..eb61005 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Cadence MHDP DisplayPort SD0801 PHY driver. + * Cadence Torrent SD0801 PHY driver. * * Copyright 2018 Cadence Design Systems, Inc. * @@ -101,7 +101,7 @@ #define RX_PSC_A3 0x2000c #define PHY_PLL_CFG 0x30038 -struct cdns_dp_phy { +struct cdns_torrent_phy { void __iomem *base; /* DPTX registers base */ void __iomem *sd_base; /* SD0801 registers base */ u32 num_lanes; /* Number of lanes to use */ @@ -109,36 +109,39 @@ struct cdns_dp_phy { struct device *dev; }; -static int cdns_dp_phy_init(struct phy *phy); -static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_pma_cfg(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy, +static int cdns_torrent_dp_init(struct phy *phy); +static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy); +static +void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy); +static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy); +static +void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy); +static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, unsigned int lane); -static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy); -static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy, - unsigned int offset, - unsigned char start_bit, - unsigned char num_bits, - unsigned int val); - -static const struct phy_ops cdns_dp_phy_ops = { - .init = cdns_dp_phy_init, +static +void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy); +static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy); +static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, + unsigned int offset, + unsigned char start_bit, + unsigned char num_bits, + unsigned int val); + +static const struct phy_ops cdns_torrent_phy_ops = { + .init = cdns_torrent_dp_init, .owner = THIS_MODULE, }; -static int cdns_dp_phy_init(struct phy *phy) +static int cdns_torrent_dp_init(struct phy *phy) { unsigned char lane_bits; - struct cdns_dp_phy *cdns_phy = phy_get_drvdata(phy); + struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy); writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */ /* PHY PMA registers configuration function */ - cdns_dp_phy_pma_cfg(cdns_phy); + cdns_torrent_dp_pma_cfg(cdns_phy); /* * Set lines power state to A0 @@ -185,24 +188,25 @@ static int cdns_dp_phy_init(struct phy *phy) */ lane_bits = (1 << cdns_phy->num_lanes) - 1; writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits), - cdns_phy->base + PHY_RESET); + cdns_phy->base + PHY_RESET); /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN); /* PHY PMA registers configuration functions */ - cdns_dp_phy_pma_cmn_vco_cfg_25mhz(cdns_phy); - cdns_dp_phy_pma_cmn_rate(cdns_phy); + cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy); + cdns_torrent_dp_pma_cmn_rate(cdns_phy); /* take out of reset */ cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1); - cdns_dp_phy_wait_pma_cmn_ready(cdns_phy); - cdns_dp_phy_run(cdns_phy); + cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); + cdns_torrent_dp_run(cdns_phy); return 0; } -static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy) +static +void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) { unsigned int reg; int ret; @@ -214,19 +218,20 @@ static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy) "timeout waiting for PMA common ready\n"); } -static void cdns_dp_phy_pma_cfg(struct cdns_dp_phy *cdns_phy) +static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy) { unsigned int i; /* PMA common configuration */ - cdns_dp_phy_pma_cmn_cfg_25mhz(cdns_phy); + cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); /* PMA lane configuration to deal with multi-link operation */ for (i = 0; i < cdns_phy->num_lanes; i++) - cdns_dp_phy_pma_lane_cfg(cdns_phy, i); + cdns_torrent_dp_pma_lane_cfg(cdns_phy, i); } -static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy) +static +void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) { /* refclock registers - assumes 25 MHz refclock */ writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR); @@ -259,7 +264,8 @@ static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy) writel(0x0318, cdns_phy->sd_base + CMN_PLL0_VCOCAL_REFTIM_START); } -static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy) +static +void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) { /* Assumes 25 MHz refclock */ switch (cdns_phy->max_bit_rate) { @@ -300,7 +306,7 @@ static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy) writel(0x0318, cdns_phy->sd_base + CMN_PLL0_VCOCAL_PLLCNT_START); } -static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy) +static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy) { unsigned int clk_sel_val = 0; unsigned int hsclk_div_val = 0; @@ -340,12 +346,12 @@ static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy) /* PMA lane configuration to deal with multi-link operation */ for (i = 0; i < cdns_phy->num_lanes; i++) { writel(hsclk_div_val, - cdns_phy->sd_base + (XCVR_DIAG_HSCLK_DIV | (i<<11))); + cdns_phy->sd_base + (XCVR_DIAG_HSCLK_DIV | (i << 11))); } } -static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy, - unsigned int lane) +static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, + unsigned int lane) { unsigned int lane_bits = (lane & LANE_MASK) << 11; @@ -361,7 +367,7 @@ static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy, writel(0x0000, cdns_phy->sd_base + (XCVR_DIAG_HSCLK_SEL | lane_bits)); } -static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy) +static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy) { unsigned int read_val; u32 write_val1 = 0; @@ -382,7 +388,6 @@ static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy) ndelay(100); switch (cdns_phy->num_lanes) { - case 1: /* lane 0 */ write_val1 = 0x00000004; write_val2 = 0x00000001; @@ -425,7 +430,7 @@ static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy) ndelay(100); } -static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy, +static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, unsigned int offset, unsigned char start_bit, unsigned char num_bits, @@ -438,10 +443,10 @@ static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy, start_bit))), cdns_phy->base + offset); } -static int cdns_dp_phy_probe(struct platform_device *pdev) +static int cdns_torrent_phy_probe(struct platform_device *pdev) { struct resource *regs; - struct cdns_dp_phy *cdns_phy; + struct cdns_torrent_phy *cdns_phy; struct device *dev = &pdev->dev; struct phy_provider *phy_provider; struct phy *phy; @@ -453,9 +458,9 @@ static int cdns_dp_phy_probe(struct platform_device *pdev) cdns_phy->dev = &pdev->dev; - phy = devm_phy_create(dev, NULL, &cdns_dp_phy_ops); + phy = devm_phy_create(dev, NULL, &cdns_torrent_phy_ops); if (IS_ERR(phy)) { - dev_err(dev, "failed to create DisplayPort PHY\n"); + dev_err(dev, "failed to create Torrent PHY\n"); return PTR_ERR(phy); } @@ -470,7 +475,7 @@ static int cdns_dp_phy_probe(struct platform_device *pdev) return PTR_ERR(cdns_phy->sd_base); err = device_property_read_u32(dev, "num_lanes", - &(cdns_phy->num_lanes)); + &cdns_phy->num_lanes); if (err) cdns_phy->num_lanes = DEFAULT_NUM_LANES; @@ -487,7 +492,7 @@ static int cdns_dp_phy_probe(struct platform_device *pdev) } err = device_property_read_u32(dev, "max_bit_rate", - &(cdns_phy->max_bit_rate)); + &cdns_phy->max_bit_rate); if (err) cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; @@ -519,23 +524,23 @@ static int cdns_dp_phy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } -static const struct of_device_id cdns_dp_phy_of_match[] = { +static const struct of_device_id cdns_torrent_phy_of_match[] = { { .compatible = "cdns,torrent-phy" }, {} }; -MODULE_DEVICE_TABLE(of, cdns_dp_phy_of_match); +MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); -static struct platform_driver cdns_dp_phy_driver = { - .probe = cdns_dp_phy_probe, +static struct platform_driver cdns_torrent_phy_driver = { + .probe = cdns_torrent_phy_probe, .driver = { - .name = "cdns-dp-phy", - .of_match_table = cdns_dp_phy_of_match, + .name = "cdns-torrent-phy", + .of_match_table = cdns_torrent_phy_of_match, } }; -module_platform_driver(cdns_dp_phy_driver); +module_platform_driver(cdns_torrent_phy_driver); MODULE_AUTHOR("Cadence Design Systems, Inc."); -MODULE_DESCRIPTION("Cadence MHDP PHY driver"); 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB6170 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 71 ++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 21 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 59c85d8..5c7c185 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -140,13 +140,31 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy, writel(val, cdns_phy->sd_base + offset); } +/* DPTX mmr access functions */ + +static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy, + u32 offset, u32 val) +{ + writel(val, cdns_phy->base + offset); +} + +static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset) +{ + return readl(cdns_phy->base + offset); +} + +#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \ + delay_us, timeout_us) \ + readl_poll_timeout((cdns_phy)->base + (offset), \ + val, cond, delay_us, timeout_us) + static int cdns_torrent_dp_init(struct phy *phy) { unsigned char lane_bits; struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy); - writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */ + cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */ /* PHY PMA registers configuration function */ cdns_torrent_dp_pma_cfg(cdns_phy); @@ -195,11 +213,11 @@ static int cdns_torrent_dp_init(struct phy *phy) * used lanes */ lane_bits = (1 << cdns_phy->num_lanes) - 1; - writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits), - cdns_phy->base + PHY_RESET); + cdns_torrent_dp_write(cdns_phy, PHY_RESET, + ((0xF & ~lane_bits) << 4) | (0xF & lane_bits)); /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ - writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN); + cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); /* PHY PMA registers configuration functions */ cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy); @@ -219,8 +237,8 @@ void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) unsigned int reg; int ret; - ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg, - reg & 1, 0, 500); + ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY, + reg, reg & 1, 0, 500); if (ret == -ETIMEDOUT) dev_err(cdns_phy->dev, "timeout waiting for PMA common ready\n"); @@ -391,8 +409,10 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy) * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the * master lane */ - ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK, - read_val, read_val & 1, 0, POLL_TIMEOUT_US); + ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, + PHY_PMA_XCVR_PLLCLK_EN_ACK, + read_val, read_val & 1, 0, + POLL_TIMEOUT_US); if (ret == -ETIMEDOUT) dev_err(cdns_phy->dev, "timeout waiting for link PLL clock enable ack\n"); @@ -417,28 +437,35 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy) break; } - writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); + cdns_torrent_dp_write(cdns_phy, + PHY_PMA_XCVR_POWER_STATE_REQ, write_val1); + + ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, + PHY_PMA_XCVR_POWER_STATE_ACK, + read_val, + (read_val & mask) == write_val1, + 0, POLL_TIMEOUT_US); - ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK, - read_val, (read_val & mask) == write_val1, 0, - POLL_TIMEOUT_US); if (ret == -ETIMEDOUT) dev_err(cdns_phy->dev, "timeout waiting for link power state ack\n"); - writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); + cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0); ndelay(100); - writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); + cdns_torrent_dp_write(cdns_phy, + PHY_PMA_XCVR_POWER_STATE_REQ, write_val2); - ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK, - read_val, (read_val & mask) == write_val2, 0, - POLL_TIMEOUT_US); + ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, + PHY_PMA_XCVR_POWER_STATE_ACK, + read_val, + (read_val & mask) == write_val2, + 0, POLL_TIMEOUT_US); if (ret == -ETIMEDOUT) dev_err(cdns_phy->dev, "timeout waiting for link power state ack\n"); - writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); + cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0); ndelay(100); } @@ -450,9 +477,11 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, { unsigned int read_val; - read_val = readl(cdns_phy->base + offset); - writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) << - start_bit))), cdns_phy->base + offset); + read_val = cdns_torrent_dp_read(cdns_phy, offset); + cdns_torrent_dp_write(cdns_phy, offset, + ((val << start_bit) | + (read_val & ~(((1 << num_bits) - 1) << + start_bit)))); } static int cdns_torrent_phy_probe(struct platform_device *pdev) From patchwork Wed Jan 22 10:45:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuti Suresh Amonkar X-Patchwork-Id: 205477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F60BC33CAF for ; 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Wed, 22 Jan 2020 11:45:21 +0100 From: Yuti Amonkar To: , , , , , CC: , , , , , Subject: [PATCH v3 07/14] phy: cadence-torrent: Add 19.2 MHz reference clock support Date: Wed, 22 Jan 2020 11:45:11 +0100 Message-ID: <1579689918-7181-8-git-send-email-yamonkar@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> References: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(376002)(396003)(39860400002)(136003)(36092001)(189003)(199004)(2616005)(426003)(4326008)(5660300002)(54906003)(42186006)(2906002)(110136005)(316002)(70586007)(70206006)(356004)(6666004)(8676002)(107886003)(36756003)(26826003)(7636002)(246002)(478600001)(26005)(30864003)(86362001)(336012)(8936002)(186003); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB5741; 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB5741 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade Add configuration functions for 19.2 MHz refclock support. Add register configurations for SSC support. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 458 ++++++++++++++++++++++++++++-- 1 file changed, 441 insertions(+), 17 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index b180fba..1596d2c 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include @@ -18,7 +19,10 @@ #include #include -#define DEFAULT_NUM_LANES 2 +#define REF_CLK_19_2MHz 19200000 +#define REF_CLK_25MHz 25000000 + +#define DEFAULT_NUM_LANES 4 #define MAX_NUM_LANES 4 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ @@ -58,6 +62,7 @@ #define CMN_BGCAL_INIT_TMR 0x00190 #define CMN_BGCAL_ITER_TMR 0x00194 #define CMN_IBCAL_INIT_TMR 0x001d0 +#define CMN_PLL0_VCOCAL_TCTRL 0x00208 #define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 #define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 #define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 @@ -67,10 +72,30 @@ #define CMN_PLL0_FRACDIVH_M0 0x00248 #define CMN_PLL0_HIGH_THR_M0 0x0024c #define CMN_PLL0_DSM_DIAG_M0 0x00250 +#define CMN_PLL0_SS_CTRL1_M0 0x00260 +#define CMN_PLL0_SS_CTRL2_M0 0x00264 +#define CMN_PLL0_SS_CTRL3_M0 0x00268 +#define CMN_PLL0_SS_CTRL4_M0 0x0026C +#define CMN_PLL0_LOCK_REFCNT_START 0x00270 #define CMN_PLL0_LOCK_PLLCNT_START 0x00278 +#define CMN_PLL0_LOCK_PLLCNT_THR 0x0027C +#define CMN_PLL1_VCOCAL_TCTRL 0x00308 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00314 +#define CMN_PLL1_VCOCAL_REFTIM_START 0x00318 +#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00320 +#define CMN_PLL1_INTDIV_M0 0x00340 +#define CMN_PLL1_FRACDIVL_M0 0x00344 +#define CMN_PLL1_FRACDIVH_M0 0x00348 +#define CMN_PLL1_HIGH_THR_M0 0x0034c #define CMN_PLL1_DSM_DIAG_M0 0x00350 +#define CMN_PLL1_SS_CTRL1_M0 0x00360 +#define CMN_PLL1_SS_CTRL2_M0 0x00364 +#define CMN_PLL1_SS_CTRL3_M0 0x00368 +#define CMN_PLL1_SS_CTRL4_M0 0x0036C +#define CMN_PLL1_LOCK_REFCNT_START 0x00370 +#define CMN_PLL1_LOCK_PLLCNT_START 0x00378 +#define CMN_PLL1_LOCK_PLLCNT_THR 0x0037C #define CMN_TXPUCAL_INIT_TMR 0x00410 #define CMN_TXPUCAL_ITER_TMR 0x00414 #define CMN_TXPDCAL_INIT_TMR 0x00430 @@ -88,18 +113,30 @@ #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x00698 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x006d0 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x006d4 +#define CMN_PDIAG_PLL1_CTRL_M0 0x00700 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x00704 +#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x00710 +#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714 +#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x00718 + #define XCVR_DIAG_PLLDRC_CTRL 0x10394 #define XCVR_DIAG_HSCLK_SEL 0x10398 #define XCVR_DIAG_HSCLK_DIV 0x1039c +#define XCVR_DIAG_BIDI_CTRL 0x103a8 #define TX_PSC_A0 0x10400 #define TX_PSC_A1 0x10404 #define TX_PSC_A2 0x10408 #define TX_PSC_A3 0x1040c +#define TX_RCVDET_ST_TMR 0x1048c #define RX_PSC_A0 0x20000 #define RX_PSC_A1 0x20004 #define RX_PSC_A2 0x20008 #define RX_PSC_A3 0x2000c +#define RX_PSC_CAL 0x20018 +#define RX_REE_GCSM1_CTRL 0x20420 +#define RX_REE_GCSM2_CTRL 0x20440 +#define RX_REE_PERGCSM_CTRL 0x20460 + #define PHY_PLL_CFG 0x30038 struct cdns_torrent_phy { @@ -108,6 +145,8 @@ struct cdns_torrent_phy { u32 num_lanes; /* Number of lanes to use */ u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ struct device *dev; + struct clk *clk; + unsigned long ref_clk_rate; }; enum phy_powerstate { @@ -118,17 +157,25 @@ enum phy_powerstate { }; static int cdns_torrent_dp_init(struct phy *phy); +static int cdns_torrent_dp_exit(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy); static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy); static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy); static +void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy); +static +void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, + u32 rate, bool ssc); +static void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy); +static +void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, + u32 rate, bool ssc); static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, unsigned int lane); -static -void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy); -static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy); +static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, + u32 rate, u32 num_lanes); static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, unsigned int offset, unsigned char start_bit, @@ -137,6 +184,7 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, static const struct phy_ops cdns_torrent_phy_ops = { .init = cdns_torrent_dp_init, + .exit = cdns_torrent_dp_exit, .owner = THIS_MODULE, }; @@ -209,6 +257,29 @@ static int cdns_torrent_dp_init(struct phy *phy) struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy); + ret = clk_prepare_enable(cdns_phy->clk); + if (ret) { + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); + return ret; + } + + cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); + if (!(cdns_phy->ref_clk_rate)) { + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); + clk_disable_unprepare(cdns_phy->clk); + return -EINVAL; + } + + switch (cdns_phy->ref_clk_rate) { + case REF_CLK_19_2MHz: + case REF_CLK_25MHz: + /* Valid Ref Clock Rate */ + break; + default: + dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); + return -EINVAL; + } + cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */ /* PHY PMA registers configuration function */ @@ -232,8 +303,17 @@ static int cdns_torrent_dp_init(struct phy *phy) cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); /* PHY PMA registers configuration functions */ - cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy); - cdns_torrent_dp_pma_cmn_rate(cdns_phy); + /* Initialize PHY with max supported link rate, without SSC. */ + if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) + cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, + cdns_phy->max_bit_rate, + false); + else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) + cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, + cdns_phy->max_bit_rate, + false); + cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate, + cdns_phy->num_lanes); /* take out of reset */ cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1); @@ -246,6 +326,14 @@ static int cdns_torrent_dp_init(struct phy *phy) return ret; } +static int cdns_torrent_dp_exit(struct phy *phy) +{ + struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy); + + clk_disable_unprepare(cdns_phy->clk); + return 0; +} + static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) { @@ -268,8 +356,12 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy) { unsigned int i; - /* PMA common configuration */ - cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); + if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) + /* PMA common configuration 19.2MHz */ + cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy); + else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) + /* PMA common configuration 25MHz */ + cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); /* PMA lane configuration to deal with multi-link operation */ for (i = 0; i < cdns_phy->num_lanes; i++) @@ -277,6 +369,225 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy) } static +void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy) +{ + /* refclock registers - assumes 19.2 MHz refclock */ + cdns_torrent_phy_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0014); + cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0027); + cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1); + cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLPRE_TMR, 0x0027); + cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1); + cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_INIT_TMR, 0x0060); + cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_ITER_TMR, 0x0060); + cdns_torrent_phy_write(cdns_phy, CMN_IBCAL_INIT_TMR, 0x0014); + cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0018); + cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0018); + cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0240); + cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_INIT_TMR, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_ITER_TMR, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_REFTIM_START, 0x000B); + cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_PLLCNT_START, 0x0137); + + /* PLL registers */ + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_TCTRL, 0x0003); +} + +/* + * Set registers responsible for enabling and configuring SSC, with second and + * third register values provided by parameters. + */ +static +void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, + u32 ctrl2_val, u32 ctrl3_val) +{ + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0003); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0003); +} + +static +void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, + u32 rate, bool ssc) +{ + /* Assumes 19.2 MHz refclock */ + switch (rate) { + /* Setting VCO for 10.8GHz */ + case 2700: + case 5400: + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_INTDIV_M0, 0x0119); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVL_M0, 0x4000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_HIGH_THR_M0, 0x00BC); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL0_CTRL_M0, 0x0012); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_INTDIV_M0, 0x0119); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVL_M0, 0x4000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_HIGH_THR_M0, 0x00BC); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL1_CTRL_M0, 0x0012); + if (ssc) + cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, + 0x006A); + break; + /* Setting VCO for 9.72GHz */ + case 1620: + case 2430: + case 3240: + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_INTDIV_M0, 0x01FA); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVL_M0, 0x4000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_HIGH_THR_M0, 0x0152); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL0_CTRL_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_INTDIV_M0, 0x01FA); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVL_M0, 0x4000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_HIGH_THR_M0, 0x0152); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL1_CTRL_M0, 0x0002); + if (ssc) + cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, + 0x0069); + break; + /* Setting VCO for 8.64GHz */ + case 2160: + case 4320: + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_INTDIV_M0, 0x01C2); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_HIGH_THR_M0, 0x012C); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL0_CTRL_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_INTDIV_M0, 0x01C2); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_HIGH_THR_M0, 0x012C); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL1_CTRL_M0, 0x0002); + if (ssc) + cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, + 0x0069); + break; + /* Setting VCO for 8.1GHz */ + case 8100: + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_INTDIV_M0, 0x01A5); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVL_M0, 0xE000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_HIGH_THR_M0, 0x011A); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL0_CTRL_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_INTDIV_M0, 0x01A5); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVL_M0, 0xE000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_HIGH_THR_M0, 0x011A); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL1_CTRL_M0, 0x0002); + if (ssc) + cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, + 0x006A); + break; + } + + if (ssc) { + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); + } else { + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); + /* Set reset register values to disable SSC */ + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); + } + + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_REFCNT_START, 0x0099); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_REFCNT_START, 0x0099); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); +} + +static void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) { /* refclock registers - assumes 25 MHz refclock */ @@ -300,22 +611,47 @@ void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_PLLCNT_START, 0x012B); /* PLL registers */ - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0409); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x1001); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_DSM_DIAG_M0, 0x0004); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA); cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0318); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_TCTRL, 0x0003); +} + +/* + * Set registers responsible for enabling and configuring SSC, with second + * register value provided by a parameter. + */ +static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, + u32 ctrl2_val) +{ + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x007F); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0003); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x007F); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0003); } static -void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) +void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, + u32 rate, bool ssc) { /* Assumes 25 MHz refclock */ - switch (cdns_phy->max_bit_rate) { + switch (rate) { /* Setting VCO for 10.8GHz */ case 2700: case 5400: @@ -323,14 +659,27 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x0000); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x0120); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x01B0); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x0120); + if (ssc) + cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); break; /* Setting VCO for 9.72GHz */ + case 1620: case 2430: case 3240: cdns_torrent_phy_write(cdns_phy, CMN_PLL0_INTDIV_M0, 0x0184); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0xCCCD); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x0104); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0184); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0xCCCD); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x0104); + if (ssc) + cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); break; /* Setting VCO for 8.64GHz */ case 2160: @@ -339,6 +688,12 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x999A); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x00E7); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0159); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x999A); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x00E7); + if (ssc) + cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); break; /* Setting VCO for 8.1GHz */ case 8100: @@ -346,14 +701,55 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x0000); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x00D8); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0144); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x00D8); + if (ssc) + cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); break; } cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0318); + cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); + + if (ssc) { + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); + } else { + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); + /* Set reset register values to disable SSC */ + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(cdns_phy, + CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); + } + + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); + cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); + cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); } -static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy) +static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, + u32 rate, u32 num_lanes) { unsigned int clk_sel_val = 0; unsigned int hsclk_div_val = 0; @@ -362,7 +758,7 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy) /* 16'h0000 for single DP link configuration */ cdns_torrent_phy_write(cdns_phy, PHY_PLL_CFG, 0x0000); - switch (cdns_phy->max_bit_rate) { + switch (rate) { case 1620: clk_sel_val = 0x0f01; hsclk_div_val = 2; @@ -390,9 +786,11 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy) cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); + cdns_torrent_phy_write(cdns_phy, + CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); /* PMA lane configuration to deal with multi-link operation */ - for (i = 0; i < cdns_phy->num_lanes; i++) + for (i = 0; i < num_lanes; i++) cdns_torrent_phy_write(cdns_phy, (XCVR_DIAG_HSCLK_DIV | (i << 11)), hsclk_div_val); @@ -403,6 +801,14 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, { unsigned int lane_bits = (lane & LANE_MASK) << 11; + /* Per lane, refclock-dependent receiver detection setting */ + if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) + cdns_torrent_phy_write(cdns_phy, + (TX_RCVDET_ST_TMR | lane_bits), 0x0780); + else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) + cdns_torrent_phy_write(cdns_phy, + (TX_RCVDET_ST_TMR | lane_bits), 0x09C4); + /* Writing Tx/Rx Power State Controllers registers */ cdns_torrent_phy_write(cdns_phy, (TX_PSC_A0 | lane_bits), 0x00FB); cdns_torrent_phy_write(cdns_phy, (TX_PSC_A2 | lane_bits), 0x04AA); @@ -411,6 +817,17 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, cdns_torrent_phy_write(cdns_phy, (RX_PSC_A2 | lane_bits), 0x0000); cdns_torrent_phy_write(cdns_phy, (RX_PSC_A3 | lane_bits), 0x0000); + cdns_torrent_phy_write(cdns_phy, (RX_PSC_CAL | lane_bits), 0x0000); + + cdns_torrent_phy_write(cdns_phy, + (RX_REE_GCSM1_CTRL | lane_bits), 0x0000); + cdns_torrent_phy_write(cdns_phy, + (RX_REE_GCSM2_CTRL | lane_bits), 0x0000); + cdns_torrent_phy_write(cdns_phy, + (RX_REE_PERGCSM_CTRL | lane_bits), 0x0000); + + cdns_torrent_phy_write(cdns_phy, + (XCVR_DIAG_BIDI_CTRL | lane_bits), 0x000F); cdns_torrent_phy_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | lane_bits), 0x0001); cdns_torrent_phy_write(cdns_phy, @@ -582,6 +999,7 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; switch (cdns_phy->max_bit_rate) { + case 1620: case 2160: case 2430: case 2700: @@ -597,6 +1015,12 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) return -EINVAL; } + cdns_phy->clk = devm_clk_get(dev, "refclk"); + if (IS_ERR(cdns_phy->clk)) { + dev_err(dev, "phy ref clock not found\n"); + return PTR_ERR(cdns_phy->clk); + } + phy_set_drvdata(phy, cdns_phy); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); From patchwork Wed Jan 22 10:45:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuti Suresh Amonkar X-Patchwork-Id: 205478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE79C2D0DB for ; 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Wed, 22 Jan 2020 11:45:22 +0100 From: Yuti Amonkar To: , , , , , CC: , , , , , Subject: [PATCH v3 08/14] phy: cadence-torrent: Implement PHY configure APIs Date: Wed, 22 Jan 2020 11:45:12 +0100 Message-ID: <1579689918-7181-9-git-send-email-yamonkar@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> References: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(346002)(39860400002)(376002)(136003)(36092001)(199004)(189003)(26005)(186003)(7636002)(30864003)(5660300002)(336012)(356004)(6666004)(54906003)(36756003)(2616005)(426003)(86362001)(110136005)(42186006)(2906002)(316002)(70586007)(246002)(70206006)(8676002)(4326008)(107886003)(478600001)(8936002)(26826003); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4461; 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB4461 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade Add support for PHY configuration APIs. These will mainly reconfigure link rate, number of lanes, voltage swing and pre-emphasis values. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 436 +++++++++++++++++++++++++++++- 1 file changed, 431 insertions(+), 5 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 1596d2c..e3b3356 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -36,6 +36,9 @@ #define PHY_AUX_CONFIG 0x00 #define PHY_AUX_CTRL 0x04 #define PHY_RESET 0x20 +#define PMA_TX_ELEC_IDLE_MASK 0xF0U +#define PMA_TX_ELEC_IDLE_SHIFT 4 +#define PHY_L00_RESET_N_MASK 0x01U #define PHY_PMA_XCVR_PLLCLK_EN 0x24 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c @@ -119,6 +122,10 @@ #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x00718 +#define TX_TXCC_CTRL 0x10100 +#define TX_TXCC_CPOST_MULT_00 0x10130 +#define TX_TXCC_MGNFS_MULT_000 0x10140 +#define DRV_DIAG_TX_DRV 0x10318 #define XCVR_DIAG_PLLDRC_CTRL 0x10394 #define XCVR_DIAG_HSCLK_SEL 0x10398 #define XCVR_DIAG_HSCLK_DIV 0x1039c @@ -128,6 +135,8 @@ #define TX_PSC_A2 0x10408 #define TX_PSC_A3 0x1040c #define TX_RCVDET_ST_TMR 0x1048c +#define TX_DIAG_ACYA 0x1079c +#define TX_DIAG_ACYA_HBDC_MASK 0x0001U #define RX_PSC_A0 0x20000 #define RX_PSC_A1 0x20004 #define RX_PSC_A2 0x20008 @@ -139,6 +148,9 @@ #define PHY_PLL_CFG 0x30038 +#define PHY_PMA_CMN_CTRL2 0x38004 +#define PHY_PMA_PLL_RAW_CTRL 0x3800c + struct cdns_torrent_phy { void __iomem *base; /* DPTX registers base */ void __iomem *sd_base; /* SD0801 registers base */ @@ -158,7 +170,8 @@ enum phy_powerstate { static int cdns_torrent_dp_init(struct phy *phy); static int cdns_torrent_dp_exit(struct phy *phy); -static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy); +static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, + u32 num_lanes); static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy); static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy); @@ -182,9 +195,16 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, unsigned char num_bits, unsigned int val); +static int cdns_torrent_dp_configure(struct phy *phy, + union phy_configure_opts *opts); +static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, + u32 num_lanes, + enum phy_powerstate powerstate); + static const struct phy_ops cdns_torrent_phy_ops = { .init = cdns_torrent_dp_init, .exit = cdns_torrent_dp_exit, + .configure = cdns_torrent_dp_configure, .owner = THIS_MODULE, }; @@ -196,6 +216,16 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy, writel(val, cdns_phy->sd_base + offset); } +static u32 cdns_torrent_phy_read(struct cdns_torrent_phy *cdns_phy, u32 offset) +{ + return readl(cdns_phy->sd_base + offset); +} + +#define cdns_torrent_phy_read_poll_timeout(cdns_phy, offset, val, cond, \ + delay_us, timeout_us) \ + readl_poll_timeout((cdns_phy)->sd_base + (offset), \ + val, cond, delay_us, timeout_us) + /* DPTX mmr access functions */ static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy, @@ -214,6 +244,237 @@ static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset) readl_poll_timeout((cdns_phy)->base + (offset), \ val, cond, delay_us, timeout_us) +/* + * Structure used to store values of PHY registers for voltage-related + * coefficients, for particular voltage swing and pre-emphasis level. Values + * are shared across all physical lanes. + */ +struct coefficients { + /* Value of DRV_DIAG_TX_DRV register to use */ + u16 diag_tx_drv; + /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ + u16 mgnfs_mult; + /* Value of TX_TXCC_CPOST_MULT_00 register to use */ + u16 cpost_mult; +}; + +/* + * Array consists of values of voltage-related registers for sd0801 PHY. A value + * of 0xFFFF is a placeholder for invalid combination, and will never be used. + */ +static const struct coefficients vltg_coeff[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, + .cpost_mult = 0x0000}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, + .cpost_mult = 0x0014}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, + .cpost_mult = 0x0020}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, + .cpost_mult = 0x002A} + }, + + /* voltage swing 1, pre-emphasis 0->3 */ + { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, + .cpost_mult = 0x0000}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, + .cpost_mult = 0x0012}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, + .cpost_mult = 0x001F}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF} + }, + + /* voltage swing 2, pre-emphasis 0->3 */ + { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, + .cpost_mult = 0x0000}, + {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, + .cpost_mult = 0x0013}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF} + }, + + /* voltage swing 3, pre-emphasis 0->3 */ + { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, + .cpost_mult = 0x0000}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF}, + {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, + .cpost_mult = 0xFFFF} + } +}; + +/* + * Enable or disable PLL for selected lanes. + */ +static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp, + bool enable) +{ + u32 rd_val; + u32 ret; + /* + * Used to determine, which bits to check for or enable in + * PHY_PMA_XCVR_PLLCLK_EN register. + */ + u32 pll_bits; + /* Used to enable or disable lanes. */ + u32 pll_val; + + /* Select values of registers and mask, depending on enabled lane + * count. + */ + switch (dp->lanes) { + /* lane 0 */ + case (1): + pll_bits = 0x00000001; + break; + /* lanes 0-1 */ + case (2): + pll_bits = 0x00000003; + break; + /* lanes 0-3, all */ + default: + pll_bits = 0x0000000F; + break; + } + + if (enable) + pll_val = pll_bits; + else + pll_val = 0x00000000; + + cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_val); + + /* Wait for acknowledgment from PHY. */ + ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, + PHY_PMA_XCVR_PLLCLK_EN_ACK, + rd_val, + (rd_val & pll_bits) == pll_val, + 0, POLL_TIMEOUT_US); + ndelay(100); + return ret; +} + +/* + * Perform register operations related to setting link rate, once powerstate is + * set and PLL disable request was processed. + */ +static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp) +{ + u32 ret; + u32 read_val; + + /* Disable the cmn_pll0_en before re-programming the new data rate. */ + cdns_torrent_phy_write(cdns_phy, PHY_PMA_PLL_RAW_CTRL, 0); + + /* + * Wait for PLL ready de-assertion. + * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 + */ + ret = cdns_torrent_phy_read_poll_timeout(cdns_phy, PHY_PMA_CMN_CTRL2, + read_val, + ((read_val >> 2) & 0x01) != 0, + 0, POLL_TIMEOUT_US); + if (ret) + return ret; + ndelay(200); + + /* DP Rate Change - VCO Output settings. */ + if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) { + /* PMA common configuration 19.2MHz */ + cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, + dp->ssc); + cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy); + } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) { + /* PMA common configuration 25MHz */ + cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, + dp->ssc); + cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy); + } + cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); + + /* Enable the cmn_pll0_en. */ + cdns_torrent_phy_write(cdns_phy, PHY_PMA_PLL_RAW_CTRL, 0x3); + + /* + * Wait for PLL ready assertion. + * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 + */ + ret = cdns_torrent_phy_read_poll_timeout(cdns_phy, PHY_PMA_CMN_CTRL2, + read_val, + (read_val & 0x01) != 0, + 0, POLL_TIMEOUT_US); + return ret; +} + +/* + * Verify, that parameters to configure PHY with are correct. + */ +static int cdns_torrent_dp_verify_config(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp) +{ + u8 i; + + /* If changing link rate was required, verify it's supported. */ + if (dp->set_rate) { + switch (dp->link_rate) { + case 1620: + case 2160: + case 2430: + case 2700: + case 3240: + case 4320: + case 5400: + case 8100: + /* valid bit rate */ + break; + default: + return -EINVAL; + } + } + + /* Verify lane count. */ + switch (dp->lanes) { + case 1: + case 2: + case 4: + /* valid lane count. */ + break; + default: + return -EINVAL; + } + + /* Check against actual number of PHY's lanes. */ + if (dp->lanes > cdns_phy->num_lanes) + return -EINVAL; + + /* + * If changing voltages is required, check swing and pre-emphasis + * levels, per-lane. + */ + if (dp->set_voltages) { + /* Lane count verified previously. */ + for (i = 0; i < dp->lanes; i++) { + if (dp->voltage[i] > 3 || dp->pre[i] > 3) + return -EINVAL; + + /* Sum of voltage swing and pre-emphasis levels cannot + * exceed 3. + */ + if (dp->voltage[i] + dp->pre[i] > 3) + return -EINVAL; + } + } + + return 0; +} + /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) @@ -250,6 +511,171 @@ static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); } +/* Configure lane count as required. */ +static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp) +{ + u32 value; + u32 ret; + u8 lane_mask = (1 << dp->lanes) - 1; + + value = cdns_torrent_dp_read(cdns_phy, PHY_RESET); + /* clear pma_tx_elec_idle_ln_* bits. */ + value &= ~PMA_TX_ELEC_IDLE_MASK; + /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ + value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & + PMA_TX_ELEC_IDLE_MASK; + cdns_torrent_dp_write(cdns_phy, PHY_RESET, value); + + /* reset the link by asserting phy_l00_reset_n low */ + cdns_torrent_dp_write(cdns_phy, PHY_RESET, + value & (~PHY_L00_RESET_N_MASK)); + + /* + * Assert lane reset on unused lanes and lane 0 so they remain in reset + * and powered down when re-enabling the link + */ + value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); + cdns_torrent_dp_write(cdns_phy, PHY_RESET, value); + + cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes); + + /* release phy_l0*_reset_n based on used laneCount */ + value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); + cdns_torrent_dp_write(cdns_phy, PHY_RESET, value); + + /* Wait, until PHY gets ready after releasing PHY reset signal. */ + ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); + if (ret) + return ret; + + ndelay(100); + + /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ + cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); + + ret = cdns_torrent_dp_run(cdns_phy, dp->lanes); + + return ret; +} + +/* Configure link rate as required. */ +static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp) +{ + u32 ret; + + ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, + POWERSTATE_A3); + if (ret) + return ret; + ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false); + if (ret) + return ret; + ndelay(200); + + ret = cdns_torrent_dp_configure_rate(cdns_phy, dp); + if (ret) + return ret; + ndelay(200); + + ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true); + if (ret) + return ret; + ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, + POWERSTATE_A2); + if (ret) + return ret; + ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, + POWERSTATE_A0); + if (ret) + return ret; + ndelay(900); + + return ret; +} + +/* Configure voltage swing and pre-emphasis for all enabled lanes. */ +static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, + struct phy_configure_opts_dp *dp) +{ + u8 lane; + u16 val; + unsigned int lane_bits; + + for (lane = 0; lane < dp->lanes; lane++) { + lane_bits = (lane & LANE_MASK) << 11; + + val = cdns_torrent_phy_read(cdns_phy, + (TX_DIAG_ACYA | lane_bits)); + /* + * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the + * current state of the analog TX driver. + */ + val |= TX_DIAG_ACYA_HBDC_MASK; + cdns_torrent_phy_write(cdns_phy, + (TX_DIAG_ACYA | lane_bits), val); + + cdns_torrent_phy_write(cdns_phy, + (TX_TXCC_CTRL | lane_bits), 0x08A4); + val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; + cdns_torrent_phy_write(cdns_phy, + (DRV_DIAG_TX_DRV | lane_bits), val); + val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; + cdns_torrent_phy_write(cdns_phy, + (TX_TXCC_MGNFS_MULT_000 | lane_bits), + val); + val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; + cdns_torrent_phy_write(cdns_phy, + (TX_TXCC_CPOST_MULT_00 | lane_bits), + val); + + val = cdns_torrent_phy_read(cdns_phy, + (TX_DIAG_ACYA | lane_bits)); + /* + * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of + * analog TX driver to reflect the new programmed one. + */ + val &= ~TX_DIAG_ACYA_HBDC_MASK; + cdns_torrent_phy_write(cdns_phy, + (TX_DIAG_ACYA | lane_bits), val); + } +}; + +static int cdns_torrent_dp_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy); + int ret; + + ret = cdns_torrent_dp_verify_config(cdns_phy, &opts->dp); + if (ret) { + dev_err(&phy->dev, "invalid params for phy configure\n"); + return ret; + } + + if (opts->dp.set_lanes) { + ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp); + if (ret) { + dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); + return ret; + } + } + + if (opts->dp.set_rate) { + ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp); + if (ret) { + dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); + return ret; + } + } + + if (opts->dp.set_voltages) + cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp); + + return ret; +} + static int cdns_torrent_dp_init(struct phy *phy) { unsigned char lane_bits; @@ -321,7 +747,7 @@ static int cdns_torrent_dp_init(struct phy *phy) if (ret) return ret; - ret = cdns_torrent_dp_run(cdns_phy); + ret = cdns_torrent_dp_run(cdns_phy, cdns_phy->num_lanes); return ret; } @@ -898,7 +1324,7 @@ static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, return ret; } -static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy) +static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) { unsigned int read_val; int ret; @@ -919,12 +1345,12 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy) ndelay(100); - ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes, + ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, POWERSTATE_A2); if (ret) return ret; - ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes, + ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, POWERSTATE_A0); return ret; From patchwork Wed Jan 22 10:45:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuti Suresh Amonkar X-Patchwork-Id: 205475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7395C33CB6 for ; Wed, 22 Jan 2020 10:46:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9FF7A24697 for ; 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Wed, 22 Jan 2020 11:45:22 +0100 From: Yuti Amonkar To: , , , , , CC: , , , , , Subject: [PATCH v3 09/14] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers Date: Wed, 22 Jan 2020 11:45:13 +0100 Message-ID: <1579689918-7181-10-git-send-email-yamonkar@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> References: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(376002)(346002)(396003)(136003)(39860400002)(199004)(189003)(36092001)(5660300002)(316002)(8936002)(7636002)(26826003)(246002)(42186006)(107886003)(110136005)(8676002)(54906003)(478600001)(36756003)(426003)(4326008)(70586007)(356004)(86362001)(2906002)(6666004)(2616005)(26005)(30864003)(186003)(70206006)(336012)(579004)(559001); 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR07MB6866 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 phishscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 1019 ++++++++++++++++++----------- 1 file changed, 650 insertions(+), 369 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index e3b3356..027667a 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -18,6 +18,7 @@ #include #include #include +#include #define REF_CLK_19_2MHz 19200000 #define REF_CLK_25MHz 25000000 @@ -27,7 +28,22 @@ #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ #define POLL_TIMEOUT_US 5000 -#define LANE_MASK 0x7 + +#define TORRENT_COMMON_CDB_OFFSET 0x0 + +#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x4000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) + +#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x8000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) + +#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ + (0xC000 << (block_offset)) + +#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ + (0xE000 << (block_offset)) /* * register offsets from DPTX PHY register block base (i.e MHDP @@ -56,100 +72,114 @@ * register offsets from SD0801 PHY register block base (i.e MHDP * register base + 0x500000) */ -#define CMN_SSM_BANDGAP_TMR 0x00084 -#define CMN_SSM_BIAS_TMR 0x00088 -#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 -#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 -#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 -#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 -#define CMN_BGCAL_INIT_TMR 0x00190 -#define CMN_BGCAL_ITER_TMR 0x00194 -#define CMN_IBCAL_INIT_TMR 0x001d0 -#define CMN_PLL0_VCOCAL_TCTRL 0x00208 -#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 -#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 -#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 -#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 -#define CMN_PLL0_INTDIV_M0 0x00240 -#define CMN_PLL0_FRACDIVL_M0 0x00244 -#define CMN_PLL0_FRACDIVH_M0 0x00248 -#define CMN_PLL0_HIGH_THR_M0 0x0024c -#define CMN_PLL0_DSM_DIAG_M0 0x00250 -#define CMN_PLL0_SS_CTRL1_M0 0x00260 -#define CMN_PLL0_SS_CTRL2_M0 0x00264 -#define CMN_PLL0_SS_CTRL3_M0 0x00268 -#define CMN_PLL0_SS_CTRL4_M0 0x0026C -#define CMN_PLL0_LOCK_REFCNT_START 0x00270 -#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 -#define CMN_PLL0_LOCK_PLLCNT_THR 0x0027C -#define CMN_PLL1_VCOCAL_TCTRL 0x00308 -#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 -#define CMN_PLL1_VCOCAL_ITER_TMR 0x00314 -#define CMN_PLL1_VCOCAL_REFTIM_START 0x00318 -#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00320 -#define CMN_PLL1_INTDIV_M0 0x00340 -#define CMN_PLL1_FRACDIVL_M0 0x00344 -#define CMN_PLL1_FRACDIVH_M0 0x00348 -#define CMN_PLL1_HIGH_THR_M0 0x0034c -#define CMN_PLL1_DSM_DIAG_M0 0x00350 -#define CMN_PLL1_SS_CTRL1_M0 0x00360 -#define CMN_PLL1_SS_CTRL2_M0 0x00364 -#define CMN_PLL1_SS_CTRL3_M0 0x00368 -#define CMN_PLL1_SS_CTRL4_M0 0x0036C -#define CMN_PLL1_LOCK_REFCNT_START 0x00370 -#define CMN_PLL1_LOCK_PLLCNT_START 0x00378 -#define CMN_PLL1_LOCK_PLLCNT_THR 0x0037C -#define CMN_TXPUCAL_INIT_TMR 0x00410 -#define CMN_TXPUCAL_ITER_TMR 0x00414 -#define CMN_TXPDCAL_INIT_TMR 0x00430 -#define CMN_TXPDCAL_ITER_TMR 0x00434 -#define CMN_RXCAL_INIT_TMR 0x00450 -#define CMN_RXCAL_ITER_TMR 0x00454 -#define CMN_SD_CAL_INIT_TMR 0x00490 -#define CMN_SD_CAL_ITER_TMR 0x00494 -#define CMN_SD_CAL_REFTIM_START 0x00498 -#define CMN_SD_CAL_PLLCNT_START 0x004a0 -#define CMN_PDIAG_PLL0_CTRL_M0 0x00680 -#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x00684 -#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x00690 -#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x00694 -#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x00698 -#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x006d0 -#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x006d4 -#define CMN_PDIAG_PLL1_CTRL_M0 0x00700 -#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x00704 -#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x00710 -#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714 -#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x00718 - -#define TX_TXCC_CTRL 0x10100 -#define TX_TXCC_CPOST_MULT_00 0x10130 -#define TX_TXCC_MGNFS_MULT_000 0x10140 -#define DRV_DIAG_TX_DRV 0x10318 -#define XCVR_DIAG_PLLDRC_CTRL 0x10394 -#define XCVR_DIAG_HSCLK_SEL 0x10398 -#define XCVR_DIAG_HSCLK_DIV 0x1039c -#define XCVR_DIAG_BIDI_CTRL 0x103a8 -#define TX_PSC_A0 0x10400 -#define TX_PSC_A1 0x10404 -#define TX_PSC_A2 0x10408 -#define TX_PSC_A3 0x1040c -#define TX_RCVDET_ST_TMR 0x1048c -#define TX_DIAG_ACYA 0x1079c +#define CMN_SSM_BANDGAP_TMR 0x0021U +#define CMN_SSM_BIAS_TMR 0x0022U +#define CMN_PLLSM0_PLLPRE_TMR 0x002AU +#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU +#define CMN_PLLSM1_PLLPRE_TMR 0x0032U +#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U +#define CMN_BGCAL_INIT_TMR 0x0064U +#define CMN_BGCAL_ITER_TMR 0x0065U +#define CMN_IBCAL_INIT_TMR 0x0074U +#define CMN_PLL0_VCOCAL_TCTRL 0x0082U +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U +#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U +#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U +#define CMN_PLL0_INTDIV_M0 0x0090U +#define CMN_PLL0_FRACDIVL_M0 0x0091U +#define CMN_PLL0_FRACDIVH_M0 0x0092U +#define CMN_PLL0_HIGH_THR_M0 0x0093U +#define CMN_PLL0_DSM_DIAG_M0 0x0094U +#define CMN_PLL0_SS_CTRL1_M0 0x0098U +#define CMN_PLL0_SS_CTRL2_M0 0x0099U +#define CMN_PLL0_SS_CTRL3_M0 0x009AU +#define CMN_PLL0_SS_CTRL4_M0 0x009BU +#define CMN_PLL0_LOCK_REFCNT_START 0x009CU +#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU +#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU +#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U +#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U +#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U +#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U +#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U +#define CMN_PLL1_INTDIV_M0 0x00D0U +#define CMN_PLL1_FRACDIVL_M0 0x00D1U +#define CMN_PLL1_FRACDIVH_M0 0x00D2U +#define CMN_PLL1_HIGH_THR_M0 0x00D3U +#define CMN_PLL1_DSM_DIAG_M0 0x00D4U +#define CMN_PLL1_SS_CTRL1_M0 0x00D8U +#define CMN_PLL1_SS_CTRL2_M0 0x00D9U +#define CMN_PLL1_SS_CTRL3_M0 0x00DAU +#define CMN_PLL1_SS_CTRL4_M0 0x00DBU +#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU +#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU +#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU +#define CMN_TXPUCAL_INIT_TMR 0x0104U +#define CMN_TXPUCAL_ITER_TMR 0x0105U +#define CMN_TXPDCAL_INIT_TMR 0x010CU +#define CMN_TXPDCAL_ITER_TMR 0x010DU +#define CMN_RXCAL_INIT_TMR 0x0114U +#define CMN_RXCAL_ITER_TMR 0x0115U +#define CMN_SD_CAL_INIT_TMR 0x0124U +#define CMN_SD_CAL_ITER_TMR 0x0125U +#define CMN_SD_CAL_REFTIM_START 0x0126U +#define CMN_SD_CAL_PLLCNT_START 0x0128U +#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U +#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U +#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U +#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U +#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U +#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U +#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U +#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U +#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U +#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U +#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U +#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U + +/* PMA TX Lane registers */ +#define TX_TXCC_CTRL 0x0040U +#define TX_TXCC_CPOST_MULT_00 0x004CU +#define TX_TXCC_MGNFS_MULT_000 0x0050U +#define DRV_DIAG_TX_DRV 0x00C6U +#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U +#define XCVR_DIAG_HSCLK_SEL 0x00E6U +#define XCVR_DIAG_HSCLK_DIV 0x00E7U +#define XCVR_DIAG_BIDI_CTRL 0x00EAU +#define TX_PSC_A0 0x0100U +#define TX_PSC_A2 0x0102U +#define TX_PSC_A3 0x0103U +#define TX_RCVDET_ST_TMR 0x0123U +#define TX_DIAG_ACYA 0x01E7U #define TX_DIAG_ACYA_HBDC_MASK 0x0001U -#define RX_PSC_A0 0x20000 -#define RX_PSC_A1 0x20004 -#define RX_PSC_A2 0x20008 -#define RX_PSC_A3 0x2000c -#define RX_PSC_CAL 0x20018 -#define RX_REE_GCSM1_CTRL 0x20420 -#define RX_REE_GCSM2_CTRL 0x20440 -#define RX_REE_PERGCSM_CTRL 0x20460 -#define PHY_PLL_CFG 0x30038 +/* PMA RX Lane registers */ +#define RX_PSC_A0 0x0000U +#define RX_PSC_A2 0x0002U +#define RX_PSC_A3 0x0003U +#define RX_PSC_CAL 0x0006U +#define RX_REE_GCSM1_CTRL 0x0108U +#define RX_REE_GCSM2_CTRL 0x0110U +#define RX_REE_PERGCSM_CTRL 0x0118U + +/* PHY PCS common registers */ +#define PHY_PLL_CFG 0x000EU + +/* PHY PMA common registers */ +#define PHY_PMA_CMN_CTRL2 0x0001U +#define PHY_PMA_PLL_RAW_CTRL 0x0003U -#define PHY_PMA_CMN_CTRL2 0x38004 -#define PHY_PMA_PLL_RAW_CTRL 0x3800c +static const struct reg_field phy_pll_cfg = + REG_FIELD(PHY_PLL_CFG, 0, 1); + +static const struct reg_field phy_pma_cmn_ctrl_2 = + REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); + +static const struct reg_field phy_pma_pll_raw_ctrl = + REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); + +static const struct of_device_id cdns_torrent_phy_of_match[]; struct cdns_torrent_phy { void __iomem *base; /* DPTX registers base */ @@ -159,6 +189,15 @@ struct cdns_torrent_phy { struct device *dev; struct clk *clk; unsigned long ref_clk_rate; + struct regmap *regmap; + struct regmap *regmap_common_cdb; + struct regmap *regmap_phy_pcs_common_cdb; + struct regmap *regmap_phy_pma_common_cdb; + struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; + struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; + struct regmap_field *phy_pll_cfg; + struct regmap_field *phy_pma_cmn_ctrl_2; + struct regmap_field *phy_pma_pll_raw_ctrl; }; enum phy_powerstate { @@ -208,23 +247,106 @@ static const struct phy_ops cdns_torrent_phy_ops = { .owner = THIS_MODULE, }; -/* PHY mmr access functions */ +struct cdns_torrent_data { + u8 block_offset_shift; + u8 reg_offset_shift; +}; -static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy, - u32 offset, u32 val) +struct cdns_regmap_cdb_context { + struct device *dev; + void __iomem *base; + u8 reg_offset_shift; +}; + +static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) { - writel(val, cdns_phy->sd_base + offset); + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + writew(val, ctx->base + offset); + + return 0; } -static u32 cdns_torrent_phy_read(struct cdns_torrent_phy *cdns_phy, u32 offset) +static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) { - return readl(cdns_phy->sd_base + offset); + struct cdns_regmap_cdb_context *ctx = context; + u32 offset = reg << ctx->reg_offset_shift; + + *val = readw(ctx->base + offset); + return 0; } -#define cdns_torrent_phy_read_poll_timeout(cdns_phy, offset, val, cond, \ - delay_us, timeout_us) \ - readl_poll_timeout((cdns_phy)->sd_base + (offset), \ - val, cond, delay_us, timeout_us) +#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ +{ \ + .name = "torrent_tx_lane" n "_cdb", \ + .reg_stride = 1, \ + .fast_io = true, \ + .reg_write = cdns_regmap_write, \ + .reg_read = cdns_regmap_read, \ +} + +#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ +{ \ + .name = "torrent_rx_lane" n "_cdb", \ + .reg_stride = 1, \ + .fast_io = true, \ + .reg_write = cdns_regmap_write, \ + .reg_read = cdns_regmap_read, \ +} + +static struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { + TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), + TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), + TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), + TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), +}; + +static struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { + TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), + TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), + TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), + TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), +}; + +static struct regmap_config cdns_torrent_common_cdb_config = { + .name = "torrent_common_cdb", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + +static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { + .name = "torrent_phy_pcs_cmn_cdb", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + +static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { + .name = "torrent_phy_pma_cmn_cdb", + .reg_stride = 1, + .fast_io = true, + .reg_write = cdns_regmap_write, + .reg_read = cdns_regmap_read, +}; + +/* PHY mmr access functions */ + +static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) +{ + regmap_write(regmap, offset, val); +} + +static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) +{ + unsigned int val; + + regmap_read(regmap, offset, &val); + return val; +} /* DPTX mmr access functions */ @@ -371,16 +493,16 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, u32 read_val; /* Disable the cmn_pll0_en before re-programming the new data rate. */ - cdns_torrent_phy_write(cdns_phy, PHY_PMA_PLL_RAW_CTRL, 0); + regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0); /* * Wait for PLL ready de-assertion. * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 */ - ret = cdns_torrent_phy_read_poll_timeout(cdns_phy, PHY_PMA_CMN_CTRL2, - read_val, - ((read_val >> 2) & 0x01) != 0, - 0, POLL_TIMEOUT_US); + ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, + read_val, + ((read_val >> 2) & 0x01) != 0, + 0, POLL_TIMEOUT_US); if (ret) return ret; ndelay(200); @@ -400,16 +522,16 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); /* Enable the cmn_pll0_en. */ - cdns_torrent_phy_write(cdns_phy, PHY_PMA_PLL_RAW_CTRL, 0x3); + regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3); /* * Wait for PLL ready assertion. * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 */ - ret = cdns_torrent_phy_read_poll_timeout(cdns_phy, PHY_PMA_CMN_CTRL2, - read_val, - (read_val & 0x01) != 0, - 0, POLL_TIMEOUT_US); + ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, + read_val, + (read_val & 0x01) != 0, + 0, POLL_TIMEOUT_US); return ret; } @@ -601,44 +723,41 @@ static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, { u8 lane; u16 val; - unsigned int lane_bits; for (lane = 0; lane < dp->lanes; lane++) { - lane_bits = (lane & LANE_MASK) << 11; - - val = cdns_torrent_phy_read(cdns_phy, - (TX_DIAG_ACYA | lane_bits)); + val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], + TX_DIAG_ACYA); /* * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the * current state of the analog TX driver. */ val |= TX_DIAG_ACYA_HBDC_MASK; - cdns_torrent_phy_write(cdns_phy, - (TX_DIAG_ACYA | lane_bits), val); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_DIAG_ACYA, val); - cdns_torrent_phy_write(cdns_phy, - (TX_TXCC_CTRL | lane_bits), 0x08A4); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_TXCC_CTRL, 0x08A4); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; - cdns_torrent_phy_write(cdns_phy, - (DRV_DIAG_TX_DRV | lane_bits), val); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + DRV_DIAG_TX_DRV, val); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; - cdns_torrent_phy_write(cdns_phy, - (TX_TXCC_MGNFS_MULT_000 | lane_bits), + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_TXCC_MGNFS_MULT_000, val); val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; - cdns_torrent_phy_write(cdns_phy, - (TX_TXCC_CPOST_MULT_00 | lane_bits), + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_TXCC_CPOST_MULT_00, val); - val = cdns_torrent_phy_read(cdns_phy, - (TX_DIAG_ACYA | lane_bits)); + val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], + TX_DIAG_ACYA); /* * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of * analog TX driver to reflect the new programmed one. */ val &= ~TX_DIAG_ACYA_HBDC_MASK; - cdns_torrent_phy_write(cdns_phy, - (TX_DIAG_ACYA | lane_bits), val); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_DIAG_ACYA, val); } }; @@ -797,43 +916,45 @@ static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy) static void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy) { + struct regmap *regmap = cdns_phy->regmap_common_cdb; + /* refclock registers - assumes 19.2 MHz refclock */ - cdns_torrent_phy_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0014); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0027); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLPRE_TMR, 0x0027); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1); - cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_INIT_TMR, 0x0060); - cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_ITER_TMR, 0x0060); - cdns_torrent_phy_write(cdns_phy, CMN_IBCAL_INIT_TMR, 0x0014); - cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0018); - cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0005); - cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0018); - cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0005); - cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0240); - cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0005); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_INIT_TMR, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_ITER_TMR, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_REFTIM_START, 0x000B); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_PLLCNT_START, 0x0137); + cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014); + cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027); + cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1); + cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027); + cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1); + cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060); + cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060); + cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014); + cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018); + cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018); + cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240); + cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137); /* PLL registers */ - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_DSM_DIAG_M0, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_DSM_DIAG_M0, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_TCTRL, 0x0003); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003); } /* @@ -844,44 +965,48 @@ static void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, u32 ctrl2_val, u32 ctrl3_val) { - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0001); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0003); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0001); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0003); + struct regmap *regmap = cdns_phy->regmap_common_cdb; + + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); } static void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, u32 rate, bool ssc) { + struct regmap *regmap = cdns_phy->regmap_common_cdb; + /* Assumes 19.2 MHz refclock */ switch (rate) { /* Setting VCO for 10.8GHz */ case 2700: case 5400: - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); if (ssc) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, @@ -891,25 +1016,25 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, case 1620: case 2430: case 3240: - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); if (ssc) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, @@ -918,25 +1043,25 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, /* Setting VCO for 8.64GHz */ case 2160: case 4320: - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); if (ssc) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, @@ -944,25 +1069,25 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, break; /* Setting VCO for 8.1GHz */ case 8100: - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); if (ssc) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, @@ -971,88 +1096,90 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, } if (ssc) { - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); } else { - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); /* Set reset register values to disable SSC */ - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); } - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_REFCNT_START, 0x0099); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_REFCNT_START, 0x0099); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); } static void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) { + struct regmap *regmap = cdns_phy->regmap_common_cdb; + /* refclock registers - assumes 25 MHz refclock */ - cdns_torrent_phy_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0019); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0032); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLPRE_TMR, 0x0032); - cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1); - cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_INIT_TMR, 0x007D); - cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_ITER_TMR, 0x007D); - cdns_torrent_phy_write(cdns_phy, CMN_IBCAL_INIT_TMR, 0x0019); - cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x001E); - cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006); - cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x001E); - cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006); - cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x02EE); - cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_INIT_TMR, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_ITER_TMR, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_REFTIM_START, 0x000E); - cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_PLLCNT_START, 0x012B); + cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019); + cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032); + cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1); + cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032); + cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1); + cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D); + cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D); + cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019); + cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E); + cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006); + cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E); + cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006); + cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE); + cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E); + cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B); /* PLL registers */ - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_DSM_DIAG_M0, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_DSM_DIAG_M0, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_TCTRL, 0x0003); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); + cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317); + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317); + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003); } /* @@ -1062,33 +1189,37 @@ void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy) static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, u32 ctrl2_val) { - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0001); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x007F); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0003); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0001); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x007F); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0003); + struct regmap *regmap = cdns_phy->regmap_common_cdb; + + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); } static void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, u32 rate, bool ssc) { + struct regmap *regmap = cdns_phy->regmap_common_cdb; + /* Assumes 25 MHz refclock */ switch (rate) { /* Setting VCO for 10.8GHz */ case 2700: case 5400: - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_INTDIV_M0, 0x01B0); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x0120); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x01B0); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x0120); + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); if (ssc) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); break; @@ -1096,82 +1227,82 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, case 1620: case 2430: case 3240: - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_INTDIV_M0, 0x0184); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0xCCCD); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x0104); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0184); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0xCCCD); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x0104); + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); if (ssc) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); break; /* Setting VCO for 8.64GHz */ case 2160: case 4320: - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_INTDIV_M0, 0x0159); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x999A); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x00E7); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0159); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x999A); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x00E7); + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); if (ssc) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); break; /* Setting VCO for 8.1GHz */ case 8100: - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_INTDIV_M0, 0x0144); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_HIGH_THR_M0, 0x00D8); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_INTDIV_M0, 0x0144); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVL_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_FRACDIVH_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_HIGH_THR_M0, 0x00D8); + cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); + cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); if (ssc) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); break; } - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); if (ssc) { - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); } else { - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); /* Set reset register values to disable SSC */ - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL1_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL2_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL3_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_SS_CTRL4_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL1_M0, 0x0002); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL2_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL3_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_SS_CTRL4_M0, 0x0000); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); } - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); - cdns_torrent_phy_write(cdns_phy, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); - cdns_torrent_phy_write(cdns_phy, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); + cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); + cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); } static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, @@ -1182,7 +1313,7 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, unsigned int i; /* 16'h0000 for single DP link configuration */ - cdns_torrent_phy_write(cdns_phy, PHY_PLL_CFG, 0x0000); + regmap_field_write(cdns_phy->phy_pll_cfg, 0x0); switch (rate) { case 1620: @@ -1210,54 +1341,58 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, break; } - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); - cdns_torrent_phy_write(cdns_phy, + cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); /* PMA lane configuration to deal with multi-link operation */ for (i = 0; i < num_lanes; i++) - cdns_torrent_phy_write(cdns_phy, - (XCVR_DIAG_HSCLK_DIV | (i << 11)), - hsclk_div_val); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i], + XCVR_DIAG_HSCLK_DIV, hsclk_div_val); } static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy, unsigned int lane) { - unsigned int lane_bits = (lane & LANE_MASK) << 11; - /* Per lane, refclock-dependent receiver detection setting */ if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) - cdns_torrent_phy_write(cdns_phy, - (TX_RCVDET_ST_TMR | lane_bits), 0x0780); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_RCVDET_ST_TMR, 0x0780); else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) - cdns_torrent_phy_write(cdns_phy, - (TX_RCVDET_ST_TMR | lane_bits), 0x09C4); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_RCVDET_ST_TMR, 0x09C4); /* Writing Tx/Rx Power State Controllers registers */ - cdns_torrent_phy_write(cdns_phy, (TX_PSC_A0 | lane_bits), 0x00FB); - cdns_torrent_phy_write(cdns_phy, (TX_PSC_A2 | lane_bits), 0x04AA); - cdns_torrent_phy_write(cdns_phy, (TX_PSC_A3 | lane_bits), 0x04AA); - cdns_torrent_phy_write(cdns_phy, (RX_PSC_A0 | lane_bits), 0x0000); - cdns_torrent_phy_write(cdns_phy, (RX_PSC_A2 | lane_bits), 0x0000); - cdns_torrent_phy_write(cdns_phy, (RX_PSC_A3 | lane_bits), 0x0000); - - cdns_torrent_phy_write(cdns_phy, (RX_PSC_CAL | lane_bits), 0x0000); - - cdns_torrent_phy_write(cdns_phy, - (RX_REE_GCSM1_CTRL | lane_bits), 0x0000); - cdns_torrent_phy_write(cdns_phy, - (RX_REE_GCSM2_CTRL | lane_bits), 0x0000); - cdns_torrent_phy_write(cdns_phy, - (RX_REE_PERGCSM_CTRL | lane_bits), 0x0000); - - cdns_torrent_phy_write(cdns_phy, - (XCVR_DIAG_BIDI_CTRL | lane_bits), 0x000F); - cdns_torrent_phy_write(cdns_phy, - (XCVR_DIAG_PLLDRC_CTRL | lane_bits), 0x0001); - cdns_torrent_phy_write(cdns_phy, - (XCVR_DIAG_HSCLK_SEL | lane_bits), 0x0000); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_PSC_A0, 0x00FB); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_PSC_A2, 0x04AA); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + TX_PSC_A3, 0x04AA); + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_PSC_A0, 0x0000); + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_PSC_A2, 0x0000); + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_PSC_A3, 0x0000); + + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_PSC_CAL, 0x0000); + + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_REE_GCSM1_CTRL, 0x0000); + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_REE_GCSM2_CTRL, 0x0000); + cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane], + RX_REE_PERGCSM_CTRL, 0x0000); + + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + XCVR_DIAG_BIDI_CTRL, 0x000F); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + XCVR_DIAG_PLLDRC_CTRL, 0x0001); + cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], + XCVR_DIAG_HSCLK_SEL, 0x0000); } static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, @@ -1371,14 +1506,142 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy, start_bit)))); } +static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, + u32 block_offset, + u8 reg_offset_shift, + const struct regmap_config *config) +{ + struct cdns_regmap_cdb_context *ctx; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev = dev; + ctx->base = base + block_offset; + ctx->reg_offset_shift = reg_offset_shift; + + return devm_regmap_init(dev, NULL, ctx, config); +} + +static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + struct regmap_field *field; + struct regmap *regmap; + + regmap = cdns_phy->regmap_phy_pcs_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); + return PTR_ERR(field); + } + cdns_phy->phy_pll_cfg = field; + + regmap = cdns_phy->regmap_phy_pma_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); + return PTR_ERR(field); + } + cdns_phy->phy_pma_cmn_ctrl_2 = field; + + regmap = cdns_phy->regmap_phy_pma_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); + return PTR_ERR(field); + } + cdns_phy->phy_pma_pll_raw_ctrl = field; + + return 0; +} + +static int cdns_regmap_init_torrent_dp(struct cdns_torrent_phy *cdns_phy, + void __iomem *sd_base, + void __iomem *base, + u8 block_offset_shift, + u8 reg_offset_shift) +{ + struct device *dev = cdns_phy->dev; + struct regmap *regmap; + u32 block_offset; + int i; + + for (i = 0; i < MAX_NUM_LANES; i++) { + block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, + reg_offset_shift); + regmap = cdns_regmap_init(dev, sd_base, block_offset, + reg_offset_shift, + &cdns_torrent_tx_lane_cdb_config[i]); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init tx lane CDB regmap\n"); + return PTR_ERR(regmap); + } + cdns_phy->regmap_tx_lane_cdb[i] = regmap; + + block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, + reg_offset_shift); + regmap = cdns_regmap_init(dev, sd_base, block_offset, + reg_offset_shift, + &cdns_torrent_rx_lane_cdb_config[i]); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init rx lane CDB regmap\n"); + return PTR_ERR(regmap); + } + cdns_phy->regmap_rx_lane_cdb[i] = regmap; + } + + block_offset = TORRENT_COMMON_CDB_OFFSET; + regmap = cdns_regmap_init(dev, sd_base, block_offset, + reg_offset_shift, + &cdns_torrent_common_cdb_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init common CDB regmap\n"); + return PTR_ERR(regmap); + } + cdns_phy->regmap_common_cdb = regmap; + + block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); + regmap = cdns_regmap_init(dev, sd_base, block_offset, + reg_offset_shift, + &cdns_torrent_phy_pcs_cmn_cdb_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); + return PTR_ERR(regmap); + } + cdns_phy->regmap_phy_pcs_common_cdb = regmap; + + block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); + regmap = cdns_regmap_init(dev, sd_base, block_offset, + reg_offset_shift, + &cdns_torrent_phy_pma_cmn_cdb_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); + return PTR_ERR(regmap); + } + cdns_phy->regmap_phy_pma_common_cdb = regmap; + + return 0; +} + static int cdns_torrent_phy_probe(struct platform_device *pdev) { struct resource *regs; struct cdns_torrent_phy *cdns_phy; struct device *dev = &pdev->dev; struct phy_provider *phy_provider; + const struct of_device_id *match; + struct cdns_torrent_data *data; struct phy *phy; - int err; + int err, ret; + + /* Get init data for this PHY */ + match = of_match_device(cdns_torrent_phy_of_match, dev); + if (!match) + return -EINVAL; + + data = (struct cdns_torrent_data *)match->data; cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); if (!cdns_phy) @@ -1393,14 +1656,15 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(cdns_phy->sd_base)) + return PTR_ERR(cdns_phy->sd_base); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); cdns_phy->base = devm_ioremap_resource(&pdev->dev, regs); if (IS_ERR(cdns_phy->base)) return PTR_ERR(cdns_phy->base); - regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); - cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs); - if (IS_ERR(cdns_phy->sd_base)) - return PTR_ERR(cdns_phy->sd_base); err = device_property_read_u32(dev, "num_lanes", &cdns_phy->num_lanes); @@ -1449,6 +1713,17 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) phy_set_drvdata(phy, cdns_phy); + ret = cdns_regmap_init_torrent_dp(cdns_phy, cdns_phy->sd_base, + cdns_phy->base, + data->block_offset_shift, + data->reg_offset_shift); + if (ret) + return ret; + + ret = cdns_regfield_init(cdns_phy); + if (ret) + return ret; + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n", @@ -1459,9 +1734,15 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } +static const struct cdns_torrent_data cdns_map_torrent = { + .block_offset_shift = 0x2, + .reg_offset_shift = 0x2, +}; + static const struct of_device_id cdns_torrent_phy_of_match[] = { { - .compatible = "cdns,torrent-phy" + .compatible = "cdns,torrent-phy", + .data = &cdns_map_torrent, }, {} }; From patchwork Wed Jan 22 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR0701MB3772 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new compatible string used for TI SoCs using Torrent PHY. Signed-off-by: Yuti Amonkar Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index eb633d7..dbb8aa5 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -15,7 +15,9 @@ maintainers: properties: compatible: - const: cdns,torrent-phy + enum: + - cdns,torrent-phy + - ti,j721e-serdes-10g clocks: maxItems: 1 From patchwork Wed Jan 22 10:45:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuti Suresh Amonkar X-Patchwork-Id: 205476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A775C33CBA for ; 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Wed, 22 Jan 2020 11:45:24 +0100 From: Yuti Amonkar To: , , , , , CC: , , , , , Subject: [PATCH v3 12/14] phy: cadence-torrent: Add platform dependent initialization structure Date: Wed, 22 Jan 2020 11:45:16 +0100 Message-ID: <1579689918-7181-13-git-send-email-yamonkar@cadence.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> References: <1579689918-7181-1-git-send-email-yamonkar@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:158.140.1.28; IPV:CAL; SCL:-1; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(396003)(136003)(376002)(39860400002)(199004)(189003)(36092001)(4326008)(36756003)(2906002)(246002)(7636002)(6666004)(26005)(2616005)(186003)(336012)(107886003)(426003)(356004)(86362001)(316002)(26826003)(8676002)(8936002)(110136005)(478600001)(42186006)(5660300002)(54906003)(70586007)(70206006); DIR:OUT; SFP:1101; SCL:1; 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Ip=[158.140.1.28]; Helo=[sjmaillnx1.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR07MB4939 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16,2020-01-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001220098 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Swapnil Jakhade Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade --- drivers/phy/cadence/phy-cadence-torrent.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 0e03d3c..851a685 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -1770,11 +1770,20 @@ static const struct cdns_torrent_data cdns_map_torrent = { .reg_offset_shift = 0x2, }; +static const struct cdns_torrent_data ti_j721e_map_torrent = { + .block_offset_shift = 0x0, + .reg_offset_shift = 0x1, +}; + static const struct of_device_id cdns_torrent_phy_of_match[] = { { .compatible = "cdns,torrent-phy", .data = &cdns_map_torrent, }, + { + .compatible = "ti,j721e-serdes-10g", + .data = &ti_j721e_map_torrent, + }, {} }; MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);