From patchwork Fri Jan 24 12:05:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 205391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73646C47409 for ; Fri, 24 Jan 2020 12:06:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54964206D4 for ; Fri, 24 Jan 2020 12:06:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730684AbgAXMGI (ORCPT ); Fri, 24 Jan 2020 07:06:08 -0500 Received: from out28-97.mail.aliyun.com ([115.124.28.97]:46865 "EHLO out28-97.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730819AbgAXMGI (ORCPT ); Fri, 24 Jan 2020 07:06:08 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.120704-0.00787874-0.871418; DS=CONTINUE|ham_alarm|0.00674226-0.00141592-0.991842; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03309; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=30; RT=30; SR=0; TI=SMTPD_---.Gh-0wLC_1579867533; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Gh-0wLC_1579867533) by smtp.aliyun-inc.com(10.147.40.2); Fri, 24 Jan 2020 20:06:01 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org, shawnguo@kernel.org, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, miquel.raynal@bootlin.com, keescook@chromium.org, ebiederm@xmission.com, krzk@kernel.org, geert+renesas@glider.be, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, chenhc@lemote.com, jiaxun.yang@flygoat.com, paul@boddie.org.uk, hns@goldelico.com, mips-creator-ci20-dev@googlegroups.com, rick.tyliu@ingenic.com Subject: [PATCH v3 2/6] clocksource: Ingenic: Add high resolution timer support for SMP. Date: Fri, 24 Jan 2020 20:05:04 +0800 Message-Id: <1579867508-81499-4-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable clock event handling on per CPU core basis. Make sure that interrupts raised on the first core execute event handlers on the correct CPU core. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: 1.Adjust function naming to make it more reasonable. 2.Replace function smp_call_function_single() with smp_call_function_single_async() in order to resolve the warning below: [ 0.350942] smp: Brought up 1 node, 2 CPUs [ 0.365497] ------------[ cut here ]------------ [ 0.365522] WARNING: CPU: 0 PID: 1 at kernel/smp.c:300 smp_call_function_single+0x110/0x200 [ 0.365533] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc1+ #5 [ 0.365537] Stack : 00000000 59c73bcd 00000037 80074e80 80000000 80670000 805a0000 80620590 [ 0.365557] 8065ce38 8fc0dc8c 806d0000 00000000 80670000 00000001 8fc0dc20 59c73bcd [ 0.365574] 00000000 00000000 806f0000 80670000 00000000 806dab00 00000000 2d302e35 [ 0.365591] 203a6d6d 806e0000 806e0000 70617773 80670000 00000000 00000000 00000009 [ 0.365610] 00000000 8fc94e20 8fc0de30 80690000 00000018 803592dc 00000000 806d0000 [ 0.365627] ... [ 0.365634] Call Trace: [ 0.365647] [<8001b9a0>] show_stack+0x6c/0x12c [ 0.365663] [<804aed20>] dump_stack+0x98/0xc8 [ 0.365673] [<8003044c>] __warn+0xc4/0xe8 [ 0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8 [ 0.365690] [<800a886c>] smp_call_function_single+0x110/0x200 [ 0.365703] ---[ end trace 5785856ca39c79d5 ]--- [ 0.365557] 8065ce38 8fc0dc8c 806d0000 00000000 80670000 00000001 8fc0dc20 59c73bcd [ 0.365574] 00000000 00000000 806f0000 80670000 00000000 806dab00 00000000 2d302e35 [ 0.365591] 203a6d6d 806e0000 806e0000 70617773 80670000 00000000 00000000 00000009 [ 0.365610] 00000000 8fc94e20 8fc0de30 80690000 00000018 803592dc 00000000 806d0000 [ 0.365627] ... [ 0.365634] Call Trace: [ 0.365647] [<8001b9a0>] show_stack+0x6c/0x12c [ 0.365663] [<804aed20>] dump_stack+0x98/0xc8 [ 0.365673] [<8003044c>] __warn+0xc4/0xe8 [ 0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8 [ 0.365690] [<800a886c>] smp_call_function_single+0x110/0x200 [ 0.365703] ---[ end trace 5785856ca39c79d5 ]--- v2->v3: No Change. drivers/clocksource/ingenic-timer.c | 201 ++++++++++++++++++++++++------------ 1 file changed, 135 insertions(+), 66 deletions(-) diff --git a/drivers/clocksource/ingenic-timer.c b/drivers/clocksource/ingenic-timer.c index 4bbdb3d..c8c5489 100644 --- a/drivers/clocksource/ingenic-timer.c +++ b/drivers/clocksource/ingenic-timer.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * JZ47xx SoCs TCU IRQ driver + * XBurst SoCs TCU IRQ driver * Copyright (C) 2019 Paul Cercueil + * Copyright (C) 2020 周琰杰 (Zhou Yanjie) */ #include @@ -21,18 +22,23 @@ #include +static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd); + struct ingenic_soc_info { unsigned int num_channels; }; struct ingenic_tcu { struct regmap *map; + struct device_node *np; struct clk *timer_clk, *cs_clk; + unsigned int timer_local[NR_CPUS]; unsigned int timer_channel, cs_channel; struct clock_event_device cevt; struct clocksource cs; - char name[4]; + char name[16]; unsigned long pwm_channels_mask; + int cpu; }; static struct ingenic_tcu *ingenic_tcu; @@ -81,6 +87,25 @@ static int ingenic_tcu_cevt_set_next(unsigned long next, return 0; } +static void ingenic_per_cpu_event_handler(void *info) +{ + struct clock_event_device *cevt = (struct clock_event_device *) info; + + if (cevt->event_handler) + cevt->event_handler(cevt); +} + +static void ingenic_tcu_per_cpu_cb(struct clock_event_device *evt) +{ + struct ingenic_tcu *tcu = to_ingenic_tcu(evt); + call_single_data_t *csd; + + csd = &per_cpu(ingenic_cevt_csd, tcu->cpu); + csd->info = (void *) evt; + csd->func = ingenic_per_cpu_event_handler; + smp_call_function_single_async(tcu->cpu, csd); +} + static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; @@ -88,8 +113,7 @@ static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel)); - if (evt->event_handler) - evt->event_handler(evt); + ingenic_tcu_per_cpu_cb(evt); return IRQ_HANDLED; } @@ -105,15 +129,75 @@ static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id) return of_clk_get_from_provider(&args); } -static int __init ingenic_tcu_timer_init(struct device_node *np, - struct ingenic_tcu *tcu) +static int __init ingenic_tcu_clocksource_init(struct device_node *np, + struct ingenic_tcu *tcu) +{ + unsigned int channel = tcu->cs_channel; + struct clocksource *cs = &tcu->cs; + unsigned long rate; + int err; + + tcu->cs_clk = ingenic_tcu_get_clock(np, channel); + if (IS_ERR(tcu->cs_clk)) + return PTR_ERR(tcu->cs_clk); + + err = clk_prepare_enable(tcu->cs_clk); + if (err) + goto err_clk_put; + + rate = clk_get_rate(tcu->cs_clk); + if (!rate) { + err = -EINVAL; + goto err_clk_disable; + } + + /* Reset channel */ + regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel), + 0xffff & ~TCU_TCSR_RESERVED_BITS, 0); + + /* Reset counter */ + regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff); + regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0); + + /* Enable channel */ + regmap_write(tcu->map, TCU_REG_TESR, BIT(channel)); + + cs->name = "ingenic-timer"; + cs->rating = 200; + cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; + cs->mask = CLOCKSOURCE_MASK(16); + cs->read = ingenic_tcu_timer_cs_read; + + err = clocksource_register_hz(cs, rate); + if (err) + goto err_clk_disable; + + return 0; + +err_clk_disable: + clk_disable_unprepare(tcu->cs_clk); +err_clk_put: + clk_put(tcu->cs_clk); + return err; +} + +static int ingenic_tcu_setup_per_cpu_cevt(struct device_node *np, + unsigned int channel) { - unsigned int timer_virq, channel = tcu->timer_channel; + unsigned int timer_virq; struct irq_domain *domain; + struct ingenic_tcu *tcu; unsigned long rate; int err; + tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->map = ingenic_tcu->map; + tcu->timer_clk = ingenic_tcu_get_clock(np, channel); + if (IS_ERR(tcu->timer_clk)) return PTR_ERR(tcu->timer_clk); @@ -139,13 +223,15 @@ static int __init ingenic_tcu_timer_init(struct device_node *np, goto err_clk_disable; } - snprintf(tcu->name, sizeof(tcu->name), "TCU"); + snprintf(tcu->name, sizeof(tcu->name), "TCU channel.%u", channel); err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER, tcu->name, &tcu->cevt); if (err) goto err_irq_dispose_mapping; + tcu->cpu = smp_processor_id(); + tcu->timer_channel = channel; tcu->cevt.cpumask = cpumask_of(smp_processor_id()); tcu->cevt.features = CLOCK_EVT_FEAT_ONESHOT; tcu->cevt.name = tcu->name; @@ -166,56 +252,23 @@ static int __init ingenic_tcu_timer_init(struct device_node *np, return err; } -static int __init ingenic_tcu_clocksource_init(struct device_node *np, - struct ingenic_tcu *tcu) +static int ingenic_tcu_setup_cevt(unsigned int cpu) { - unsigned int channel = tcu->cs_channel; - struct clocksource *cs = &tcu->cs; - unsigned long rate; - int err; - - tcu->cs_clk = ingenic_tcu_get_clock(np, channel); - if (IS_ERR(tcu->cs_clk)) - return PTR_ERR(tcu->cs_clk); - - err = clk_prepare_enable(tcu->cs_clk); - if (err) - goto err_clk_put; - - rate = clk_get_rate(tcu->cs_clk); - if (!rate) { - err = -EINVAL; - goto err_clk_disable; - } - - /* Reset channel */ - regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel), - 0xffff & ~TCU_TCSR_RESERVED_BITS, 0); - - /* Reset counter */ - regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff); - regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0); - - /* Enable channel */ - regmap_write(tcu->map, TCU_REG_TESR, BIT(channel)); - - cs->name = "ingenic-timer"; - cs->rating = 200; - cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; - cs->mask = CLOCKSOURCE_MASK(16); - cs->read = ingenic_tcu_timer_cs_read; + int ret; - err = clocksource_register_hz(cs, rate); - if (err) - goto err_clk_disable; + ret = ingenic_tcu_setup_per_cpu_cevt(ingenic_tcu->np, + ingenic_tcu->timer_local[cpu]); + if (ret) + goto err_tcu_clocksource_cleanup; return 0; -err_clk_disable: - clk_disable_unprepare(tcu->cs_clk); -err_clk_put: - clk_put(tcu->cs_clk); - return err; +err_tcu_clocksource_cleanup: + clocksource_unregister(&ingenic_tcu->cs); + clk_disable_unprepare(ingenic_tcu->cs_clk); + clk_put(ingenic_tcu->cs_clk); + kfree(ingenic_tcu); + return ret; } static const struct ingenic_soc_info jz4740_soc_info = { @@ -239,6 +292,7 @@ static int __init ingenic_tcu_init(struct device_node *np) const struct ingenic_soc_info *soc_info = id->data; struct ingenic_tcu *tcu; struct regmap *map; + unsigned cpu = 0; long rate; int ret; @@ -253,12 +307,14 @@ static int __init ingenic_tcu_init(struct device_node *np) return -ENOMEM; /* Enable all TCU channels for PWM use by default except channels 0/1 */ - tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2); + tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, + NR_CPUS + 1); of_property_read_u32(np, "ingenic,pwm-channels-mask", (u32 *)&tcu->pwm_channels_mask); /* Verify that we have at least two free channels */ - if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) { + if (hweight8(tcu->pwm_channels_mask) > + soc_info->num_channels - NR_CPUS + 1) { pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__, tcu->pwm_channels_mask); ret = -EINVAL; @@ -266,13 +322,29 @@ static int __init ingenic_tcu_init(struct device_node *np) } tcu->map = map; + tcu->np = np; ingenic_tcu = tcu; - tcu->timer_channel = find_first_zero_bit(&tcu->pwm_channels_mask, + tcu->timer_local[cpu] = find_first_zero_bit(&tcu->pwm_channels_mask, soc_info->num_channels); - tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, - soc_info->num_channels, - tcu->timer_channel + 1); + + if (NR_CPUS > 1) { + for (cpu = 1; cpu < NR_CPUS; cpu++) + tcu->timer_local[cpu] = find_next_zero_bit( + &tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu - 1] + 1); + + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu-1] + 1); + } else { + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu] + 1); + } + + ret = ingenic_tcu_clocksource_init(np, tcu); if (ret) { @@ -280,9 +352,10 @@ static int __init ingenic_tcu_init(struct device_node *np) goto err_free_ingenic_tcu; } - ret = ingenic_tcu_timer_init(np, tcu); - if (ret) - goto err_tcu_clocksource_cleanup; + /* Setup clock events on each CPU core */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online", + ingenic_tcu_setup_cevt, NULL); + WARN_ON(ret < 0); /* Register the sched_clock at the end as there's no way to undo it */ rate = clk_get_rate(tcu->cs_clk); @@ -290,10 +363,6 @@ static int __init ingenic_tcu_init(struct device_node *np) return 0; -err_tcu_clocksource_cleanup: - clocksource_unregister(&tcu->cs); - clk_disable_unprepare(tcu->cs_clk); - clk_put(tcu->cs_clk); err_free_ingenic_tcu: kfree(tcu); return ret; From patchwork Fri Jan 24 12:05:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 205392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D42AFC35242 for ; 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Fri, 24 Jan 2020 20:06:03 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org, shawnguo@kernel.org, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, miquel.raynal@bootlin.com, keescook@chromium.org, ebiederm@xmission.com, krzk@kernel.org, geert+renesas@glider.be, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, chenhc@lemote.com, jiaxun.yang@flygoat.com, paul@boddie.org.uk, hns@goldelico.com, mips-creator-ci20-dev@googlegroups.com, rick.tyliu@ingenic.com Subject: [PATCH v3 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding. Date: Fri, 24 Jan 2020 20:05:05 +0800 Message-Id: <1579867508-81499-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: Change the two Document from txt to yaml. v2->v3: Fix formatting errors. .../bindings/mips/ingenic/ingenic,cpu.yaml | 53 ++++++++++++++++++++++ .../bindings/mips/ingenic/ingenic,soc,yaml | 35 ++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index 00000000..014c2b5 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) +description: | + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: + oneOf: + - ingenic,xburst + - ingenic,xburst2 + + reg: + description: | + The number of the CPU. + +required: + - device_type + - compatible + - reg + +Example: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml new file mode 100644 index 00000000..324c4bb --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic SoCs with XBurst CPU inside. + +maintainers: + - 周琰杰 (Zhou Yanjie) +description: | + Ingenic SoCs with XBurst CPU inside shall have the following properties. + +properties: + compatible: + oneOf: + - ingenic,jz4740 + - ingenic,jz4725b + - ingenic,jz4760 + - ingenic,jz4760b + - ingenic,jz4770 + - ingenic,jz4780 + - ingenic,x1000 + - ingenic,x1000e + - ingenic,x1500 + +required: + - compatible + +examples: + - | + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; +... From patchwork Fri Jan 24 12:05:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 205393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAAF8C32771 for ; Fri, 24 Jan 2020 12:06:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8875B20709 for ; Fri, 24 Jan 2020 12:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388516AbgAXMGS (ORCPT ); Fri, 24 Jan 2020 07:06:18 -0500 Received: from out28-77.mail.aliyun.com ([115.124.28.77]:53981 "EHLO out28-77.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388400AbgAXMGR (ORCPT ); Fri, 24 Jan 2020 07:06:17 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.2751907|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.0446825-0.00421084-0.951107; DS=CONTINUE|ham_system_inform|0.0101188-0.000462388-0.989419; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03296; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=30; RT=30; SR=0; TI=SMTPD_---.Gh-0wLC_1579867533; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Gh-0wLC_1579867533) by smtp.aliyun-inc.com(10.147.40.2); Fri, 24 Jan 2020 20:06:10 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, jhogan@kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org, shawnguo@kernel.org, mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org, miquel.raynal@bootlin.com, keescook@chromium.org, ebiederm@xmission.com, krzk@kernel.org, geert+renesas@glider.be, paul@crapouillou.net, prasannatsmkumar@gmail.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, chenhc@lemote.com, jiaxun.yang@flygoat.com, paul@boddie.org.uk, hns@goldelico.com, mips-creator-ci20-dev@googlegroups.com, rick.tyliu@ingenic.com Subject: [PATCH v3 6/6] MIPS: CI20: Update defconfig to support SMP. Date: Fri, 24 Jan 2020 20:05:08 +0800 Message-Id: <1579867508-81499-8-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1579867508-81499-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "CONFIG_SMP=y" and "CONFIG_NR_CPUS=2" to support SMP. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: No change. v2->v3: No change. arch/mips/configs/ci20_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index be41df2..3aadb2e 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -1,3 +1,5 @@ +CONFIG_SMP=y +CONFIG_NR_CPUS=2 # CONFIG_LOCALVERSION_AUTO is not set CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y