From patchwork Tue Jan 28 15:38:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 205292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5405C35240 for ; Tue, 28 Jan 2020 15:39:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7270B24683 for ; Tue, 28 Jan 2020 15:39:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="wTOGQAb+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbgA1Pim (ORCPT ); Tue, 28 Jan 2020 10:38:42 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:64686 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726781AbgA1Pik (ORCPT ); Tue, 28 Jan 2020 10:38:40 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00SFYEVU022156; Tue, 28 Jan 2020 16:38:21 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=q/c0qNSKj8aYswDcead/4rOA6djgvx5JBXYvwUSuNrU=; b=wTOGQAb+jrvgWsFvkQe7UITD8lRaoydzKMvXf6LhhVSPJPXqER5XhlHjt5Qd8KJpVIqo ern5j0Uc1MgnJ5NG/SSVxoqj9oluZ1y37aZxQhry7E4EoZ3EF1F4jtUqJEILVAVOhXja JgYCARmW3Bi/oDqR+euXGioPquML7xc6G0Dz3W5732HvbBNaS+Thwr/ndK8bQLdmQefz t0v+I6rBo3zny+jLRYnMHjGZJ5BcASB1Ax9vXfAg6ZrMK1HnVv/xUDVepEiEg9TZDn72 Cjud04QZNU2Rqdz5T7Z0dP0LW3l/MJyARHQDwlUDWuyqQYv1g7rUIgETK9Y58cQJxaJG vw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2xrc136p53-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2020 16:38:21 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B80D2100038; Tue, 28 Jan 2020 16:38:20 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A2EC92BF9CF; Tue, 28 Jan 2020 16:38:20 +0100 (CET) Received: from localhost (10.75.127.45) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 28 Jan 2020 16:38:20 +0100 From: Benjamin Gaignard To: , , , , , , , CC: , , , , , , , , , Benjamin Gaignard Subject: [PATCH v2 2/7] bus: Introduce firewall controller framework Date: Tue, 28 Jan 2020 16:38:01 +0100 Message-ID: <20200128153806.7780-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200128153806.7780-1-benjamin.gaignard@st.com> References: <20200128153806.7780-1-benjamin.gaignard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-28_05:2020-01-28,2020-01-28 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The goal of this framework is to offer an interface for the hardware blocks controlling bus accesses rights. Bus firewall controllers are typically used to control if a hardware block can perform read or write operations on bus. Smarter firewall controllers could be able to define accesses rights per hardware blocks to control where they can read or write. Firewall controller configurations are provided in device node, parsed by the framework and send to the driver to apply them. Each controller may need different number and type of inputs to configure the firewall so device-tree properties size have to be define by using "#firewall-cells". Firewall configurations properties have to be named "firewall-X" on device node. "firewall-names" keyword can also be used to give a name to a specific configuration. Example of device-tree: ctrl0: firewall@0 { #firewall-cells = <2>; }; foo: foo@0 { firewall-names = "default", "setting1"; firewall-0 = <&ctrl0 1 2>; firewall-1 = <&ctrl0 3 4>; }; Configurations could be applied with functions like firewall_set_config_by_index() or firewall_set_config_by_name(). firewall_set_default_config() function will apply the configuration named "default" (if existing) or the configuration with index 0 (i.e. firewall-0). Drivers could register/unregister themselves be calling firewall_register/firewall_unregister functions. When a configuration has to be applied the driver callback, provided in the ops at registration time, set_config is called by the framework. Signed-off-by: Benjamin Gaignard --- version 2: - rename the framework "firewall" - rebased on top of v5.5 drivers/bus/Kconfig | 2 + drivers/bus/Makefile | 2 + drivers/bus/firewall/Kconfig | 7 ++ drivers/bus/firewall/Makefile | 1 + drivers/bus/firewall/firewall.c | 264 ++++++++++++++++++++++++++++++++++++++++ include/linux/firewall.h | 70 +++++++++++ 6 files changed, 346 insertions(+) create mode 100644 drivers/bus/firewall/Kconfig create mode 100644 drivers/bus/firewall/Makefile create mode 100644 drivers/bus/firewall/firewall.c create mode 100644 include/linux/firewall.h diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 50200d1c06ea..d3f636c64e1c 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -203,4 +203,6 @@ config DA8XX_MSTPRI source "drivers/bus/fsl-mc/Kconfig" +source "drivers/bus/firewall/Kconfig" + endmenu diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 1320bcf9fa9d..278c27fd57cd 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -34,3 +34,5 @@ obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o obj-$(CONFIG_DA8XX_MSTPRI) += da8xx-mstpri.o + +obj-$(CONFIG_FIREWALL_CONTROLLERS) += firewall/ diff --git a/drivers/bus/firewall/Kconfig b/drivers/bus/firewall/Kconfig new file mode 100644 index 000000000000..893bacb955f5 --- /dev/null +++ b/drivers/bus/firewall/Kconfig @@ -0,0 +1,7 @@ +menu "Bus Firewall Controllers" + +config FIREWALL_CONTROLLERS + bool "Support of bus firewall controllers" + depends on OF + +endmenu diff --git a/drivers/bus/firewall/Makefile b/drivers/bus/firewall/Makefile new file mode 100644 index 000000000000..eb6b978d6450 --- /dev/null +++ b/drivers/bus/firewall/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_FIREWALL_CONTROLLERS) += firewall.o diff --git a/drivers/bus/firewall/firewall.c b/drivers/bus/firewall/firewall.c new file mode 100644 index 000000000000..765105d29075 --- /dev/null +++ b/drivers/bus/firewall/firewall.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Mutex taken to protect firewall_list */ +static DEFINE_MUTEX(firewall_list_mutex); + +/* Global list of firewall control devices */ +static LIST_HEAD(firewall_list); + +struct firewall_ctrl { + struct list_head node; + struct device *dev; + struct firewall_ops *ops; +}; + +static struct firewall_ctrl *get_firewallctrl_from_node(struct device_node *np) +{ + struct firewall_ctrl *ctrl; + + mutex_lock(&firewall_list_mutex); + + list_for_each_entry(ctrl, &firewall_list, node) { + if (ctrl->dev->of_node == np) { + mutex_unlock(&firewall_list_mutex); + return ctrl; + } + } + + mutex_unlock(&firewall_list_mutex); + + return NULL; +} + +/** + * firewall_dt_has_default + * + * Check if the device node provide firewall configuration + * + * @dev: device with possible firewall configuration + * + * Return: true is firewall-0 property exist in the device node + */ +static bool firewall_dt_has_default(struct device *dev) +{ + struct device_node *np; + struct property *prop; + int size; + + np = dev->of_node; + if (!np) + return false; + + prop = of_find_property(np, "firewall-0", &size); + + return prop ? true : false; +} + +/** + * firewall_set_config_by_index + * + * Set a firewall controller configuration based on given index. + * + * @dev: device with firewall configuration to apply. + * @index: the index of the configuration in device node. + * + * Return: 0 if OK, -EPROBE_DEFER if waiting for firewall controller to be + * registered or negative value on other errors. + */ +int firewall_set_config_by_index(struct device *dev, int index) +{ + struct device_node *np = dev->of_node; + char *propname; + int configs, i, err = 0; + + if (!np) + return 0; + + propname = kasprintf(GFP_KERNEL, "firewall-%d", index); + configs = of_count_phandle_with_args(np, propname, "#firewall-cells"); + if (configs < 0) { + err = -EINVAL; + goto error; + } + + for (i = 0; i < configs; i++) { + struct firewall_ctrl *ctrl; + struct of_phandle_args args; + + err = of_parse_phandle_with_args(np, propname, + "#firewall-cells", + i, &args); + if (err) + goto error; + + /* Test if the controller is (or will be) available */ + if (!of_device_is_available(args.np)) { + of_node_put(args.np); + continue; + } + + ctrl = get_firewallctrl_from_node(args.np); + of_node_put(args.np); + + /* Controller is not yet registered */ + if (!ctrl) { + err = -EPROBE_DEFER; + goto error; + } + + err = ctrl->ops->set_config(ctrl->dev, &args); + if (err) + goto error; + } + +error: + kfree(propname); + return err; +} +EXPORT_SYMBOL_GPL(firewall_set_config_by_index); + +/** + * firewall_set_config_by_name + * + * Set a firwall controller configuration based on given name. + * + * @dev: device with firewall configuration to apply. + * @name: the name of the configuration in device node. + * + * Return: 0 if OK, -EPROBE_DEFER if waiting for firewall controller to be + * registered or negative value on other errors. + */ +int firewall_set_config_by_name(struct device *dev, char *name) +{ + const char *configname; + int count, i; + + count = of_property_count_strings(dev->of_node, "firewall-names"); + for (i = 0; i < count; i++) { + int err; + + err = of_property_read_string_index(dev->of_node, + "firewall-names", + i, &configname); + if (err) + return err; + + if (strcmp(name, configname)) + continue; + + return firewall_set_config_by_index(dev, i); + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(firewall_set_config_by_name); + +/** + * firewall_set_default_config + * + * Set the default configuration for device. + * First try to apply configuration named "default", if it fails + * or doesn't exist, try to apply firewall-0 configuration. + * + * @dev: device with firewall configuration to apply. + * + * Return: 0 if OK, -EPROBE_DEFER if waiting for firewall controller to be + * registered or negative value on other errors. + */ +int firewall_set_default_config(struct device *dev) +{ + int ret; + + /* Nothing to do if device node doesn't contain at least + * one configuration + */ + if (!firewall_dt_has_default(dev)) + return 0; + + ret = firewall_set_config_by_name(dev, "default"); + if (!ret || (ret == -EPROBE_DEFER)) + return ret; + + return firewall_set_config_by_index(dev, 0); +} +EXPORT_SYMBOL_GPL(firewall_set_default_config); + +/** + * firewall_register + * + * Register a firewall controller device. + * + * @dev: device implementing firewall controller. + * @ops: firewall controller operations. + * + * Return: 0 if OK or negative value on error. + */ +int firewall_register(struct device *dev, + struct firewall_ops *ops) +{ + struct firewall_ctrl *ctrl; + + if (!dev || !ops || !ops->set_config) + return -EINVAL; + + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + INIT_LIST_HEAD(&ctrl->node); + + ctrl->dev = dev; + ctrl->ops = ops; + + mutex_lock(&firewall_list_mutex); + list_add_tail(&ctrl->node, &firewall_list); + mutex_unlock(&firewall_list_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(firewall_register); + +/** + * firewall_unregister + * + * Unregister a firewall controller device. + * + * @dev: device implementing firewall controller. + */ +void firewall_unregister(struct device *dev) +{ + struct firewall_ctrl *ctrl; + + ctrl = get_firewallctrl_from_node(dev->of_node); + if (!ctrl) + return; + + mutex_lock(&firewall_list_mutex); + list_del(&ctrl->node); + mutex_unlock(&firewall_list_mutex); + + kfree(ctrl); +} +EXPORT_SYMBOL_GPL(firewall_unregister); + +static int __init firewall_init(void) +{ + pr_info("initialized bus firewall controller subsystem\n"); + return 0; +} + +/* Init early since drivers really need to configure firewall early */ +core_initcall(firewall_init); diff --git a/include/linux/firewall.h b/include/linux/firewall.h new file mode 100644 index 000000000000..67eb9985821c --- /dev/null +++ b/include/linux/firewall.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#ifndef _FIREWALL_H_ +#define _FIREWALL_H_ + +#include +#include + +/** + * struct firewall_ops + * + * Firewall controller operations structure to be filled by drivers. + */ +struct firewall_ops { + /** + * @set_config: + * + * Driver callback to set a firewall configuration on a controller. + * Configuration arguments are provided in out_args parameter. + * + * Return: 0 on success, a negative error code on failure. + */ + int (*set_config)(struct device *dev, struct of_phandle_args *out_args); +}; + +#ifdef CONFIG_FIREWALL_CONTROLLERS + +int firewall_set_config_by_index(struct device *dev, int index); +int firewall_set_config_by_name(struct device *dev, char *name); +int firewall_set_default_config(struct device *dev); + +int firewall_register(struct device *dev, struct firewall_ops *ops); + +void firewall_unregister(struct device *dev); + +#else + +static inline int firewall_set_config_by_index(struct device *dev, int index) +{ + return 0; +} + +static inline int firewall_set_config_by_name(struct device *dev, char *name) +{ + return 0; +} + +static inline int firewall_set_default_config(struct device *dev) +{ + return 0; +} + +static inline int firewall_register(struct device *dev, + struct firewall_ops *ops) +{ + return 0; +} + +static inline void firewall_unregister(struct device *dev) +{ + /* Empty */ +} + +#endif + +#endif /* _FIREWALL_H_ */ From patchwork Tue Jan 28 15:38:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 205293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AF7EC33CB3 for ; Tue, 28 Jan 2020 15:39:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0964F24683 for ; Tue, 28 Jan 2020 15:39:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="HUDdqXCB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbgA1Pim (ORCPT ); Tue, 28 Jan 2020 10:38:42 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:53023 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726772AbgA1Pij (ORCPT ); Tue, 28 Jan 2020 10:38:39 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00SFX6Nw021992; Tue, 28 Jan 2020 16:38:24 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=Ar4ysUo6whK/cok6Jdojo6d6gqeT3A3cGFa6YycKXws=; b=HUDdqXCBXSH4J6+9bwwuYs6E9kZAM1p5eGF5qzVMVnFj2Btihh1QQXcLDVcj0SPpMwlA ApMmu4k8KGPSluwjJ1paOuIC9+hzyGiFkA9O5wnAO54R8j1o/BX61qyZuJF+pxI3macr n4jWj3aBJrwe02jr6YiehZgY49YxLJOmx4nSsHc6K+yHchB96beFP3GLlELIvD2m0Psv BXBXlHkKuwJXa9ipKM8ODes1MY/tOQ7PZHn5wrPf12tCUxKmHXFNuiKcUm9OVvewVjoz PFEEaoqvVfe+F+ZGriUs7XGuyUwcMWqFUZK7w4P/1QZkllAhf72VPx+MBEviEs/TX6AB EA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2xrcaxxmdk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2020 16:38:24 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 807AF100034; Tue, 28 Jan 2020 16:38:24 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6CD632BF9D0; Tue, 28 Jan 2020 16:38:24 +0100 (CET) Received: from localhost (10.75.127.45) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 28 Jan 2020 16:38:23 +0100 From: Benjamin Gaignard To: , , , , , , , CC: , , , , , , , , , Benjamin Gaignard Subject: [PATCH v2 5/7] bus: firewall: Add driver for STM32 ETZPC controller Date: Tue, 28 Jan 2020 16:38:04 +0100 Message-ID: <20200128153806.7780-6-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200128153806.7780-1-benjamin.gaignard@st.com> References: <20200128153806.7780-1-benjamin.gaignard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-28_05:2020-01-28,2020-01-28 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org STM32 Extended TrustZone Protection Controller (ETZPC) got 3 possible configurations per hardware block: - secure: hardware blocks are only accessible by software running on trust zone (i.e op-tee firmware). - non-secure: hardware blocks are accessible by non-secure software (i.e. linux kernel). - coprocessor: hardware blocks are only accessible by the coprocessor. Each hardware block status is defined by a 2 bits field and all of them are packed into 32 bits registers. ETZPC can manage up to 94 hardware blocks. Signed-off-by: Benjamin Gaignard --- version 2: - provide the full list the hardware blocks drivers/bus/firewall/Kconfig | 7 ++ drivers/bus/firewall/Makefile | 1 + drivers/bus/firewall/stm32-etzpc.c | 140 +++++++++++++++++++++++++ include/dt-bindings/bus/firewall/stm32-etzpc.h | 90 ++++++++++++++++ 4 files changed, 238 insertions(+) create mode 100644 drivers/bus/firewall/stm32-etzpc.c create mode 100644 include/dt-bindings/bus/firewall/stm32-etzpc.h diff --git a/drivers/bus/firewall/Kconfig b/drivers/bus/firewall/Kconfig index 893bacb955f5..f724c09801e0 100644 --- a/drivers/bus/firewall/Kconfig +++ b/drivers/bus/firewall/Kconfig @@ -4,4 +4,11 @@ config FIREWALL_CONTROLLERS bool "Support of bus firewall controllers" depends on OF +config STM32_ETZPC + bool "STM32 ETZPC Domain Controller" + depends on FIREWALL_CONTROLLERS && MACH_STM32MP157 + help + Select y to enable STM32 Extended TrustZone Protection + Controller (ETZPC) + endmenu diff --git a/drivers/bus/firewall/Makefile b/drivers/bus/firewall/Makefile index eb6b978d6450..d42e99b5865e 100644 --- a/drivers/bus/firewall/Makefile +++ b/drivers/bus/firewall/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_FIREWALL_CONTROLLERS) += firewall.o +obj-$(CONFIG_STM32_ETZPC) += stm32-etzpc.o diff --git a/drivers/bus/firewall/stm32-etzpc.c b/drivers/bus/firewall/stm32-etzpc.c new file mode 100644 index 000000000000..39999579fe92 --- /dev/null +++ b/drivers/bus/firewall/stm32-etzpc.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ETZPC_DECPROT 0x010 +#define ETZPC_NUM_LOCKS 94 + +struct stm32_etzpc { + struct regmap_field *fields[ETZPC_NUM_LOCKS]; +}; + +static int stm32_etzpc_set_config(struct device *dev, + struct of_phandle_args *out_args) +{ + struct stm32_etzpc *etzpc = dev_get_drvdata(dev); + int index = out_args->args[0]; + unsigned int value = out_args->args[1]; + u32 status; + + if (out_args->args_count != 2) + return -EINVAL; + + if (index >= ETZPC_NUM_LOCKS) + return -EINVAL; + + if (value > STM32_ETZPC_NON_SECURE) + return -EINVAL; + + regmap_field_force_write(etzpc->fields[index], value); + + /* Hardware could denied the new value, read it back to check it */ + regmap_field_read(etzpc->fields[index], &status); + + if (value != status) { + dev_info(dev, "failed to set configuration: index %d, value %d\n", + index, value); + return -EINVAL; + } + + return 0; +} + +static struct firewall_ops stm32_etzpc_ops = { + .set_config = stm32_etzpc_set_config, +}; + +static const struct regmap_config stm32_etzpc_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = sizeof(u32), + .max_register = 0x3FF, + .fast_io = true, +}; + +static int stm32_etzpc_probe(struct platform_device *pdev) +{ + struct stm32_etzpc *etzpc; + struct resource *res; + void __iomem *mmio; + struct regmap *regmap; + int i; + + etzpc = devm_kzalloc(&pdev->dev, sizeof(*etzpc), GFP_KERNEL); + if (!etzpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + regmap = devm_regmap_init_mmio(&pdev->dev, mmio, + &stm32_etzpc_regmap_cfg); + + for (i = 0; i < ETZPC_NUM_LOCKS; i++) { + struct reg_field field; + + /* + * Each hardware block status is defined by + * a 2 bits field and all of them are packed into + * 32 bits registers. Do some computation to get + * register offset and the shift. + */ + field.reg = ETZPC_DECPROT + (i >> 4) * sizeof(u32); + field.lsb = (i % 0x10) << 1; + field.msb = field.lsb + 1; + + etzpc->fields[i] = devm_regmap_field_alloc(&pdev->dev, + regmap, field); + } + + platform_set_drvdata(pdev, etzpc); + + return firewall_register(&pdev->dev, &stm32_etzpc_ops); +} + +static int stm32_etzpc_remove(struct platform_device *pdev) +{ + firewall_unregister(&pdev->dev); + + return 0; +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { .compatible = "st,stm32-etzpc" }, + { /* end node */ } +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static struct platform_driver stm32_etzpc_driver = { + .probe = stm32_etzpc_probe, + .remove = stm32_etzpc_remove, + .driver = { + .name = "stm32-etzpc", + .of_match_table = stm32_etzpc_of_match, + }, +}; + +static int __init stm32_etzpc_init(void) +{ + return platform_driver_register(&stm32_etzpc_driver); +} +arch_initcall(stm32_etzpc_init); + +MODULE_AUTHOR("Benjamin Gaignard "); +MODULE_DESCRIPTION("STMicroelectronics STM32 Bus Firewall Controller"); diff --git a/include/dt-bindings/bus/firewall/stm32-etzpc.h b/include/dt-bindings/bus/firewall/stm32-etzpc.h new file mode 100644 index 000000000000..9c4783b9783c --- /dev/null +++ b/include/dt-bindings/bus/firewall/stm32-etzpc.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#ifndef _STM32_ETZPC_H_ +#define _STM32_ETZPC_H_ + +/* ETZPC configurations: trust-zone, non-secure or coprocessor*/ +#define STM32_ETZPC_TRUST 1 +#define STM32_ETPCZ_COPRO 2 +#define STM32_ETZPC_NON_SECURE 3 + +/* ETZPC hard blocks index */ +#define STM32_ETZPC_USART1 3 +#define STM32_ETZPC_SPI6 4 +#define STM32_ETZPC_I2C4 5 +#define STM32_ETZPC_RNG1 7 +#define STM32_ETZPC_HASH1 8 +#define STM32_ETZPC_CRYP1 9 +#define STM32_ETZPC_I2C6 12 +#define STM32_ETZPC_TIM2 16 +#define STM32_ETZPC_TIM3 17 +#define STM32_ETZPC_TIM4 18 +#define STM32_ETZPC_TIM5 19 +#define STM32_ETZPC_TIM6 20 +#define STM32_ETZPC_TIM7 21 +#define STM32_ETZPC_TIM12 22 +#define STM32_ETZPC_TIM13 23 +#define STM32_ETZPC_TIM14 24 +#define STM32_ETZPC_LPTIM1 25 +#define STM32_ETZPC_SPI2 27 +#define STM32_ETZPC_SPI3 28 +#define STM32_ETZPC_USART2 30 +#define STM32_ETZPC_USART3 31 +#define STM32_ETZPC_USART4 32 +#define STM32_ETZPC_USART5 33 +#define STM32_ETZPC_I2C1 34 +#define STM32_ETZPC_I2C2 35 +#define STM32_ETZPC_I2C3 36 +#define STM32_ETZPC_I2C5 37 +#define STM32_ETZPC_CEC 38 +#define STM32_ETZPC_DAC 39 +#define STM32_ETZPC_UART7 40 +#define STM32_ETZPC_UART8 41 +#define STM32_ETZPC_MDIOS 44 +#define STM32_ETZPC_TIM1 48 +#define STM32_ETZPC_TIM8 49 +#define STM32_ETZPC_USART6 51 +#define STM32_ETZPC_SPI1 52 +#define STM32_ETZPC_SPI4 53 +#define STM32_ETZPC_TIM15 54 +#define STM32_ETZPC_TIM16 55 +#define STM32_ETZPC_TIM17 56 +#define STM32_ETZPC_SPI5 57 +#define STM32_ETZPC_SAI1 58 +#define STM32_ETZPC_SAI2 59 +#define STM32_ETZPC_SAI3 60 +#define STM32_ETZPC_DFSDM 61 +#define STM32_ETZPC_TT_FDCAN 62 +#define STM32_ETZPC_LPTIM2 64 +#define STM32_ETZPC_LPTIM3 65 +#define STM32_ETZPC_LPTIM4 66 +#define STM32_ETZPC_LPTIM5 67 +#define STM32_ETZPC_SAI4 68 +#define STM32_ETZPC_VREFBUF 69 +#define STM32_ETZPC_DCMI 70 +#define STM32_ETZPC_CRC2 71 +#define STM32_ETZPC_ADC 72 +#define STM32_ETZPC_HASH2 73 +#define STM32_ETZPC_RNG2 74 +#define STM32_ETZPC_CRYP2 75 +#define STM32_ETZPC_SRAM1 80 +#define STM32_ETZPC_SRAM2 81 +#define STM32_ETZPC_SRAM3 82 +#define STM32_ETZPC_SRAM4 83 +#define STM32_ETZPC_RETRAM 84 +#define STM32_ETZPC_OTG 85 +#define STM32_ETZPC_SDMMC3 86 +#define STM32_ETZPC_DLYBSD3 87 +#define STM32_ETZPC_DMA1 88 +#define STM32_ETZPC_DMA2 89 +#define STM32_ETZPC_DMAMUX 90 +#define STM32_ETZPC_FMC 91 +#define STM32_ETZPC_QSPI 92 +#define STM32_ETZPC_DLYBQ 93 +#define STM32_ETZPC_ETH1 94 + +#endif /* _STM32_ETZPC_H_ */ From patchwork Tue Jan 28 15:38:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 205294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B0AC33CB2 for ; Tue, 28 Jan 2020 15:39:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CBBE024683 for ; Tue, 28 Jan 2020 15:39:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="FirNxXdn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726909AbgA1Pim (ORCPT ); Tue, 28 Jan 2020 10:38:42 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:1475 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726770AbgA1Pil (ORCPT ); Tue, 28 Jan 2020 10:38:41 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00SFX6T6021991; Tue, 28 Jan 2020 16:38:29 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=BYJzgUMk733kauvTheIZCyk54aZylmh0QOl0v2b0GrM=; b=FirNxXdnv49pNeVN1usCbem2Cb2nRu2k4Tw4PsQujj7GM8CmdqSeR+fy5T6U6fuL92CN CgupI1Hyz0yV8cXqR1FRnKkOvfrD0PROALtQDWZfX5pffmVw+ZAJuNjaQuGnizWk6LR3 7Y8dZNYWahYPZWjXpSHNZPHzP43Allr2xocKcwv0dAN2KtbwCdB9iiJOiwnpnvmTuMT/ oTY6aGLyrfP5dQgYiv4mg2xtu/TzxbLs0Qvc9faObd49LcyaK8lI9/Izo4Zs8nnNK3cm q0T3I+Xykq6+9rG9UL3n8KtqornDLYjSrjoOphBaXUie3yuPeMSvHVqiE71/1QKz0BX3 cA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2xrcaxxmdt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2020 16:38:29 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 351F710002A; Tue, 28 Jan 2020 16:38:25 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 22FDE2BF9D0; Tue, 28 Jan 2020 16:38:25 +0100 (CET) Received: from localhost (10.75.127.44) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 28 Jan 2020 16:38:24 +0100 From: Benjamin Gaignard To: , , , , , , , CC: , , , , , , , , , Benjamin Gaignard Subject: [PATCH v2 6/7] ARM: dts: stm32: Add firewall node for stm32mp157 SoC Date: Tue, 28 Jan 2020 16:38:05 +0100 Message-ID: <20200128153806.7780-7-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200128153806.7780-1-benjamin.gaignard@st.com> References: <20200128153806.7780-1-benjamin.gaignard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-28_05:2020-01-28,2020-01-28 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Declare ETZPC device as a firewall controller node for stm32mp157 SoC Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32mp157c.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index ed8b258256d7..8a00dad9688e 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -1499,6 +1499,13 @@ }; }; + etzpc: etzpc@5c007000 { + compatible = "st,stm32-etzpc"; + reg = <0x5c007000 0x400>; + #firewall-cells = <2>; + status = "okay"; + }; + i2c6: i2c@5c009000 { compatible = "st,stm32f7-i2c"; reg = <0x5c009000 0x400>;