From patchwork Thu Jan 30 06:52:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 205248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDF49C33C9E for ; Thu, 30 Jan 2020 06:53:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9ECE2206F0 for ; Thu, 30 Jan 2020 06:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726659AbgA3Gwz (ORCPT ); Thu, 30 Jan 2020 01:52:55 -0500 Received: from mx.socionext.com ([202.248.49.38]:26335 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725873AbgA3Gwy (ORCPT ); Thu, 30 Jan 2020 01:52:54 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Jan 2020 15:52:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 5C9E9180C09; Thu, 30 Jan 2020 15:52:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 30 Jan 2020 15:53:58 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id AADE01A01BB; Thu, 30 Jan 2020 15:52:52 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 1/7] phy: socionext: Use devm_platform_ioremap_resource() Date: Thu, 30 Jan 2020 15:52:39 +0900 Message-Id: <1580367165-16760-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-pcie.c | 4 +--- drivers/phy/socionext/phy-uniphier-usb3hs.c | 4 +--- drivers/phy/socionext/phy-uniphier-usb3ss.c | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index 93ffbd2..25d1d9d 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -163,7 +163,6 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) struct phy_provider *phy_provider; struct device *dev = &pdev->dev; struct regmap *regmap; - struct resource *res; struct phy *phy; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -176,8 +175,7 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) priv->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c index 50f379f..1d3f9e8 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3hs.c +++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c @@ -309,7 +309,6 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct uniphier_u3hsphy_priv *priv; struct phy_provider *phy_provider; - struct resource *res; struct phy *phy; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -322,8 +321,7 @@ static int uniphier_u3hsphy_probe(struct platform_device *pdev) priv->data->nparams > MAX_PHY_PARAMS)) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c index ec231e4..05e40a2 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3ss.c +++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c @@ -215,7 +215,6 @@ static int uniphier_u3ssphy_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct uniphier_u3ssphy_priv *priv; struct phy_provider *phy_provider; - struct resource *res; struct phy *phy; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -228,8 +227,7 @@ static int uniphier_u3ssphy_probe(struct platform_device *pdev) priv->data->nparams > MAX_PHY_PARAMS)) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); From patchwork Thu Jan 30 06:52:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 205251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 113A8C3F68F for ; Thu, 30 Jan 2020 06:53:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E60F02082E for ; Thu, 30 Jan 2020 06:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726811AbgA3Gw4 (ORCPT ); Thu, 30 Jan 2020 01:52:56 -0500 Received: from mx.socionext.com ([202.248.49.38]:26335 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726647AbgA3Gw4 (ORCPT ); Thu, 30 Jan 2020 01:52:56 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 30 Jan 2020 15:52:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id D82DD603AB; Thu, 30 Jan 2020 15:52:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 30 Jan 2020 15:53:58 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 89A631A01BB; Thu, 30 Jan 2020 15:52:53 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 2/7] dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphy Date: Thu, 30 Jan 2020 15:52:40 +0900 Message-Id: <1580367165-16760-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds compatible string for Pro5 SoC that needs to manage gio clock and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this removes Pro4 description from usb3-hsphy. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt | 13 +++++++++---- .../devicetree/bindings/phy/uniphier-usb3-hsphy.txt | 6 +++--- .../devicetree/bindings/phy/uniphier-usb3-ssphy.txt | 5 +++-- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt index 1889d3b..3cee372 100644 --- a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt @@ -5,14 +5,19 @@ PCIe controller implemented on Socionext UniPhier SoCs. Required properties: - compatible: Should contain one of the following: + "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY - reg: Specifies offset and length of the register set for the device. - #phy-cells: Must be zero. -- clocks: A phandle to the clock gate for PCIe glue layer including - this phy. -- resets: A phandle to the reset line for PCIe glue layer including - this phy. +- clocks: A list of phandles to the clock gate for PCIe glue layer + including this phy. +- clock-names: For Pro5 only, should contain the following: + "gio", "link" - for Pro5 SoC +- resets: A list of phandles to the reset line for PCIe glue layer + including this phy. +- reset-names: For Pro5 only, should contain the following: + "gio", "link" - for Pro5 SoC Optional properties: - socionext,syscon: A phandle to system control to set configurations diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt index e8d8086..093d4f0 100644 --- a/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt +++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt @@ -7,7 +7,7 @@ this describes about High-Speed PHY. Required properties: - compatible: Should contain one of the following: - "socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC + "socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC @@ -16,13 +16,13 @@ Required properties: - clocks: A list of phandles to the clock gate for USB3 glue layer. According to the clock-names, appropriate clocks are required. - clock-names: Should contain the following: - "gio", "link" - for Pro4 SoC + "gio", "link" - for Pro5 SoC "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. "phy", "link" - for others - resets: A list of phandles to the reset control for USB3 glue layer. According to the reset-names, appropriate resets are required. - reset-names: Should contain the following: - "gio", "link" - for Pro4 SoC + "gio", "link" - for Pro5 SoC "phy", "link" - for others Optional properties: diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt index 490b815..9df2bc2 100644 --- a/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt +++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt @@ -8,6 +8,7 @@ this describes about Super-Speed PHY. Required properties: - compatible: Should contain one of the following: "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC + "socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC @@ -16,13 +17,13 @@ Required properties: - clocks: A list of phandles to the clock gate for USB3 glue layer. According to the clock-names, appropriate clocks are required. - clock-names: - "gio", "link" - for Pro4 SoC + "gio", "link" - for Pro4 and Pro5 SoC "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. "phy", "link" - for others - resets: A list of phandles to the reset control for USB3 glue layer. According to the reset-names, appropriate resets are required. - reset-names: - "gio", "link" - for Pro4 SoC + "gio", "link" - for Pro4 and Pro5 SoC "phy", "link" - for others Optional properties: From patchwork Thu Jan 30 06:52:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 205249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D981AC35240 for ; Thu, 30 Jan 2020 06:53:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4275206F0 for ; Thu, 30 Jan 2020 06:53:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbgA3Gw7 (ORCPT ); Thu, 30 Jan 2020 01:52:59 -0500 Received: from mx.socionext.com ([202.248.49.38]:26330 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726828AbgA3Gw6 (ORCPT ); Thu, 30 Jan 2020 01:52:58 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 30 Jan 2020 15:52:56 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 87C5C603AB; Thu, 30 Jan 2020 15:52:56 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 30 Jan 2020 15:54:16 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id DDA481A01BB; Thu, 30 Jan 2020 15:52:55 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 5/7] phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failure Date: Thu, 30 Jan 2020 15:52:43 +0900 Message-Id: <1580367165-16760-6-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-usb3hs.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c index bdf696e..a9bc741 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3hs.c +++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c @@ -41,10 +41,12 @@ #define PHY_F(regno, msb, lsb) { (regno), (msb), (lsb) } +#define RX_CHK_SYNC PHY_F(0, 5, 5) /* RX sync mode */ +#define RX_SYNC_SEL PHY_F(1, 1, 0) /* RX sync length */ #define LS_SLEW PHY_F(10, 6, 6) /* LS mode slew rate */ #define FS_LS_DRV PHY_F(10, 5, 5) /* FS/LS slew rate */ -#define MAX_PHY_PARAMS 2 +#define MAX_PHY_PARAMS 4 struct uniphier_u3hsphy_param { struct { @@ -395,13 +397,19 @@ static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = { static const struct uniphier_u3hsphy_soc_data uniphier_pxs2_data = { .is_legacy = false, - .nparams = 0, + .nparams = 2, + .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, + }, }; static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { .is_legacy = false, - .nparams = 2, + .nparams = 4, .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, { LS_SLEW, 1 }, { FS_LS_DRV, 1 }, }, @@ -412,7 +420,11 @@ static const struct uniphier_u3hsphy_soc_data uniphier_ld20_data = { static const struct uniphier_u3hsphy_soc_data uniphier_pxs3_data = { .is_legacy = false, - .nparams = 0, + .nparams = 2, + .param = { + { RX_CHK_SYNC, 1 }, + { RX_SYNC_SEL, 1 }, + }, .trim_func = uniphier_u3hsphy_trim_ld20, .config0 = 0x92316680, .config1 = 0x00000106, From patchwork Thu Jan 30 06:52:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 205250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 442AAC33C9E for ; Thu, 30 Jan 2020 06:53:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 230B52083E for ; Thu, 30 Jan 2020 06:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726948AbgA3GxI (ORCPT ); Thu, 30 Jan 2020 01:53:08 -0500 Received: from mx.socionext.com ([202.248.49.38]:26335 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726841AbgA3GxA (ORCPT ); Thu, 30 Jan 2020 01:53:00 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Jan 2020 15:52:57 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 18D55180C09; Thu, 30 Jan 2020 15:52:58 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 30 Jan 2020 15:54:18 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 6A5F51A01BB; Thu, 30 Jan 2020 15:52:57 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 7/7] phy: uniphier-pcie: Add SoC-dependent phy-mode function support Date: Thu, 30 Jan 2020 15:52:45 +0900 Message-Id: <1580367165-16760-8-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1580367165-16760-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/phy-uniphier-pcie.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index cd17c70..e4adab3 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -55,8 +55,8 @@ struct uniphier_pciephy_priv { }; struct uniphier_pciephy_soc_data { - bool has_syscon; bool is_legacy; + void (*set_phymode)(struct regmap *regmap); }; static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, @@ -243,9 +243,8 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "socionext,syscon"); - if (!IS_ERR(regmap) && priv->data->has_syscon) - regmap_update_bits(regmap, SG_USBPCIESEL, - SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); + if (!IS_ERR(regmap) && priv->data->set_phymode) + priv->data->set_phymode(regmap); phy_set_drvdata(phy, priv); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); @@ -253,18 +252,22 @@ static int uniphier_pciephy_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(phy_provider); } +static void uniphier_pciephy_ld20_setmode(struct regmap *regmap) +{ + regmap_update_bits(regmap, SG_USBPCIESEL, + SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); +} + static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { - .has_syscon = false, .is_legacy = true, }; static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { - .has_syscon = true, .is_legacy = false, + .set_phymode = uniphier_pciephy_ld20_setmode, }; static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { - .has_syscon = false, .is_legacy = false, };