From patchwork Mon Feb 3 18:31:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B742EC35251 for ; Mon, 3 Feb 2020 18:32:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 940CE2082E for ; Mon, 3 Feb 2020 18:32:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Wasqs3eQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729812AbgBCScP (ORCPT ); Mon, 3 Feb 2020 13:32:15 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:42983 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729800AbgBCScP (ORCPT ); Mon, 3 Feb 2020 13:32:15 -0500 Received: by mail-pf1-f195.google.com with SMTP id 4so8001800pfz.9 for ; Mon, 03 Feb 2020 10:32:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VgteBj9kECksIDTJrgniP2446O1fnhyCOGN0Ivx+enM=; b=Wasqs3eQqUzCosW2InB859U3pOvbe38Hb1XgxdLpg6eoIZdzcG1bmQE2AkHc/hD56S skYrU9/Iz0iHIwxBM896C1cPiba1pe/l33EBfXbzaovXELHSeSoE0WG1x5UfI+GdVv6r qBlhIePFzl/Daj1DGeuKd6ey0dTb9aO3yY33I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VgteBj9kECksIDTJrgniP2446O1fnhyCOGN0Ivx+enM=; b=fUFkn1NfYJzMMAhlZ+4kJZ5zEdBmXNVx2Am8Kvj6GLvZtbHGIJovrQ811bD6oqdve2 XCQj5d/+YDRMZMJItVYd22tyelgbc1B8QSaSAZJj/o50zAjU3Joemvt/vRe7t2nDG/7E f0IIzWHqyTlMrp0s5W8kz6eMHhoB5GnIhGb68IEK5i3gzss4xJ498OElUlZR9JdCvVWA /hFeb5u5igu3AN4O49UgO90mFLZqbWUTPvzyzFcF+gGfXZ6D+/1jMkHh+9kXBcAahZAR Yu7VJW5Ylaiq8D9b/LAo+H6HNb05nuO8yCMC7iv1ekkKcZY+JsMIfC5uOs1rjwuSql+k h+iA== X-Gm-Message-State: APjAAAUdR9lWOeJbsqyuAJa7BRL2phDiFlEkhDbYeDlQ0t28M6z+oCGJ uaGEV6qKYZKuSRfYEx6ddXWDxw== X-Google-Smtp-Source: APXvYqzvauFbriTETiUnafbrlgvwI/wPoIrVw6ombXysZj6zY/10IZRZSdiVV5V0bmXbBDeIPjRjjw== X-Received: by 2002:a63:511:: with SMTP id 17mr4524461pgf.221.1580754734404; Mon, 03 Feb 2020 10:32:14 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:13 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v4 01/15] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Date: Mon, 3 Feb 2020 10:31:34 -0800 Message-Id: <20200203103049.v4.1.I7487325fe8e701a68a07d3be8a6a4b571eca9cfa@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When I got my clock parenting slightly wrong I ended up with a crash that looked like this: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... pc : clk_hw_get_rate+0x14/0x44 ... Call trace: clk_hw_get_rate+0x14/0x44 _freq_tbl_determine_rate+0x94/0xfc clk_rcg2_determine_rate+0x2c/0x38 clk_core_determine_round_nolock+0x4c/0x88 clk_core_round_rate_nolock+0x6c/0xa8 clk_core_round_rate_nolock+0x9c/0xa8 clk_core_set_rate_nolock+0x70/0x180 clk_set_rate+0x3c/0x6c of_clk_set_defaults+0x254/0x360 platform_drv_probe+0x28/0xb0 really_probe+0x120/0x2dc driver_probe_device+0x64/0xfc device_driver_attach+0x4c/0x6c __driver_attach+0xac/0xc0 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0xfc/0x1d0 driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 msm_drm_register+0x5c/0x60 ... It turned out that clk_hw_get_parent_by_index() was returning NULL and we weren't checking. Let's check it so that we don't crash. Fixes: ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs") Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke --- I haven't gone back and tried to reproduce this same crash on older kernels, but I'll put the blame on commit ac269395cdd8 ("clk: qcom: Convert to clk_hw based provider APIs"). Before that if we got a NULL parent back it was fine and dandy since a NULL "struct clk" is valid to use but a NULL "struct clk_hw" is not. Changes in v4: None Changes in v3: - Add Matthias tag. Changes in v2: - Patch ("clk: qcom: rcg2: Don't crash...") new for v2. drivers/clk/qcom/clk-rcg2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index da045b200def..9098001ac805 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -218,6 +218,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, clk_flags = clk_hw_get_flags(hw); p = clk_hw_get_parent_by_index(hw, index); + if (!p) + return -EINVAL; + if (clk_flags & CLK_SET_RATE_PARENT) { rate = f->freq; if (f->pre_div) { From patchwork Mon Feb 3 18:31:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2969EC35247 for ; Mon, 3 Feb 2020 18:33:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F32D82082E for ; Mon, 3 Feb 2020 18:33:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="KArXZabh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727253AbgBCSdV (ORCPT ); Mon, 3 Feb 2020 13:33:21 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:39223 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729835AbgBCScR (ORCPT ); Mon, 3 Feb 2020 13:32:17 -0500 Received: by mail-pj1-f66.google.com with SMTP id e9so124711pjr.4 for ; Mon, 03 Feb 2020 10:32:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dnHettLd109wANxmdLuXyjYbhCkrWo2MBVjX008Rwpo=; b=KArXZabhSftb0nm4KAEC8Kh1eRvQA9bTbTyctAjK4VDpavX5woENwIipPOLRK7mNTO FYyPfsFYmEThLjIMpcQkGmKCgkjXAY7tSdFE/YOz7ZCV6BJWt5DWPurXYVPhTRckrZFo kBkNttwnUMA05tTj+bQqGlZvOA380ZD3Oo5Y0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dnHettLd109wANxmdLuXyjYbhCkrWo2MBVjX008Rwpo=; b=PfuvH+OJMlakOfD+m9xWr8Of+hKdEsuzK0afUe376IlyHaiWPfthX2pq9r+q1aPDu5 m0+ITOnTQZLDozAuwJPbfPoh7iQhye8iJn0OzSrhcwRTmm1dmPLogjQwvWSTyTQX224z RR8G83FevL5tulc2jsJzzX5TLBP1uhmfXsrM1x2SRXZ4M6j4TAsK0nvQ00m8AOlw3JNv zvoZIXwxXchWmEjK76qPQD77fNa+auFFh04RXQ9alvUeS+WzHaZ64x10IWzPcI8Qvu9l bAjGg0MupE5DbRvvYfJ7PvmFwOgXuT6i3s6krKt2FgO91wtbcWVoQlONfiKny/j0GMez SbqQ== X-Gm-Message-State: APjAAAWnUYlgEZPlwVg4qQ0PfTwq+VQdw/TWfW+ppz3d7tL285go8sES wJ4/8CX/Tu/GuCXTvgvYsdpJkg== X-Google-Smtp-Source: APXvYqzupddr0m+0FM3AlZBJi/XgpMRn2ETFD6Sx9S1ysEUvEJeqNWIF5FlGp7vm535awanJb+BeJg== X-Received: by 2002:a17:90a:35e6:: with SMTP id r93mr448876pjb.44.1580754736620; Mon, 03 Feb 2020 10:32:16 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:16 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v4 03/15] arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc Date: Mon, 3 Feb 2020 10:31:36 -0800 Message-Id: <20200203103049.v4.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We're transitioning over to requiring the Qualcomm Display Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTES: - Until the Linux driver for sdm845's dispcc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. - Although the clocks from the DP PHY are required, the DP PHY isn't represented in the dts yet. Apparently the magic for this is just to use <0>. Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Newly discovered gcc_disp_gpll0_div_clk_src added. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...dispcc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d42302b8889b..0985813fee50 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2933,6 +2933,24 @@ opp-200000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Mon Feb 3 18:31:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03E78C35249 for ; Mon, 3 Feb 2020 18:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D34AA2082E for ; Mon, 3 Feb 2020 18:32:22 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 03 Feb 2020 10:32:17 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v4 04/15] clk: qcom: Get rid of fallback global names for dispcc-sc7180 Date: Mon, 3 Feb 2020 10:31:37 -0800 Message-Id: <20200203103049.v4.4.Ia3706a5d5add72e88dbff60fd13ec06bf7a2fd48@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the new world input clocks should be matched by ".fw_name". sc7180 is new enough that no backward compatibility use of global names should be needed. Remove it. With a proper device tree and downstream display patches I have verified booting a sc7180 up and seeing the display after this patch. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Patch ("clk: qcom: Get rid of fallback...dispcc-sc7180") split out for v3. - Unlike in v2, use internal name instead of purist name. Changes in v2: None drivers/clk/qcom/dispcc-sc7180.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 30c1e25d3edb..a820e1558677 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -81,7 +81,7 @@ static const struct parent_map disp_cc_parent_map_0[] = { static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_1[] = { @@ -93,10 +93,9 @@ static const struct parent_map disp_cc_parent_map_1[] = { static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "dp_phy_pll_vco_div_clk", - .name = "dp_phy_pll_vco_div_clk"}, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_2[] = { @@ -107,9 +106,8 @@ static const struct parent_map disp_cc_parent_map_2[] = { static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_byteclk", - .name = "dsi0_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -125,7 +123,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { { .hw = &disp_cc_pll0.clkr.hw }, { .fw_name = "gcc_disp_gpll0_clk_src" }, { .hw = &disp_cc_pll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { @@ -137,7 +135,7 @@ static const struct parent_map disp_cc_parent_map_4[] = { static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "gcc_disp_gpll0_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_5[] = { @@ -148,9 +146,8 @@ static const struct parent_map disp_cc_parent_map_5[] = { static const struct clk_parent_data disp_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_dsiclk", - .name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { From patchwork Mon Feb 3 18:31:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F7EC35247 for ; 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Mon, 03 Feb 2020 10:32:20 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:19 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v4 06/15] clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks Date: Mon, 3 Feb 2020 10:31:39 -0800 Message-Id: <20200203103049.v4.6.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Patch ("clk: qcom: Use ARRAY_SIZE in dispcc-sc7180...") split out for v3. Changes in v2: None drivers/clk/qcom/dispcc-sc7180.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 397f5d9dafc8..dd7af41e47eb 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -154,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -168,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -188,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -201,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -215,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -229,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -244,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -267,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -280,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -295,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -309,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; From patchwork Mon Feb 3 18:31:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8556FC35247 for ; Mon, 3 Feb 2020 18:32:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D56D2086A for ; Mon, 3 Feb 2020 18:32:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="G8Vtypw/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728006AbgBCSc6 (ORCPT ); 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Remove it. Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Patch ("clk: qcom: Get rid of the test...gpucc-sc7180") split out for v3. Changes in v2: None drivers/clk/qcom/gpucc-sc7180.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194cceaf..c88f00125775 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -60,7 +60,6 @@ static const struct parent_map gpu_cc_parent_map_0[] = { { P_GPU_CC_PLL1_OUT_MAIN, 3 }, { P_GPLL0_OUT_MAIN, 5 }, { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { @@ -68,7 +67,6 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .hw = &gpu_cc_pll1.clkr.hw }, { .fw_name = "gcc_gpu_gpll0_clk_src" }, { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { @@ -86,7 +84,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_0, - .num_parents = 5, + .num_parents = 4, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Mon Feb 3 18:31:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D976C35247 for ; Mon, 3 Feb 2020 18:32:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D26B32086A for ; Mon, 3 Feb 2020 18:32:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BdULmOCW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729680AbgBCScv (ORCPT ); Mon, 3 Feb 2020 13:32:51 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:41650 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729952AbgBCSc1 (ORCPT ); Mon, 3 Feb 2020 13:32:27 -0500 Received: by mail-pf1-f196.google.com with SMTP id j9so4919557pfa.8 for ; Mon, 03 Feb 2020 10:32:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RKN0WqAtpRXlZLQAbpsRUXVNFr6J7IAd3QgsbRQLWCk=; b=BdULmOCWTTwykDLz/VlJIkPI0WyQDbO088Vq1dRFwoLFTk+mvm5+zUgCcI8G9c+QeK pYKZPSenwIK8qffyRMZLBeUPZOKZ2QQzmfRLwVFDOE7CcY0jWv8kyhHspDW1mqhGKgZF 2MV7dPAEW4DzLGYDQtyAW8lGlWWo6JuKPwL+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RKN0WqAtpRXlZLQAbpsRUXVNFr6J7IAd3QgsbRQLWCk=; b=ACQzHROIZ52tsU6tj6NOEiHrLnx0v+NGHUYqaz7Q2aa5i327m5Ha3fZjjUfUrWokIm uTMduZDaFm90UQD3wbZIc5aGAfksL3lSUz9KlEGULnLURqD0eqL7rRe+fxXy2AIdewae kyDMIs68cVJ1if0nkaKm0zjEA26ugjV8LZePZj/VaBwUF0mn8+Lspa22iW+QAHRL6hyJ XfVz1dAvNV9/+6KrpQ67K0JHxz7HaKnf8ki02XXPLn19gqXIMwCJz5V8aP4taC8a2o07 fXP3/ZA0f9I6nAXd7Jez/4x5CR98xU5yIxDtMw4MqIRxdt9uIKydYMqM6k35n9gQ9QPP Ti9g== X-Gm-Message-State: APjAAAWDfPXg8HxANFTCoNF8W9WYIM0kkSh6tuL1L8hCW1O6Cl0MEmvZ 90Hjs6kIGtVQ79Yedew2PmjOaQ== X-Google-Smtp-Source: APXvYqyucrWizz3g5g3rxQ3ARzLwqEguVciLlZpzkfUtkox3V5loKVi8ThNlpT37NInXwcHjLrCiHQ== X-Received: by 2002:a62:e217:: with SMTP id a23mr7651932pfi.50.1580754746509; Mon, 03 Feb 2020 10:32:26 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:25 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v4 11/15] dt-bindings: clock: Cleanup qcom, videocc bindings for sdm845/sc7180 Date: Mon, 3 Feb 2020 10:31:44 -0800 Message-Id: <20200203103049.v4.11.I27bbd90045f38cd3218c259526409d52a48efb35@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This makes the qcom,videocc bindings match the recent changes to the dispcc and gpucc. 1. Switched to using "bi_tcxo" instead of "xo". 2. Adds a description for the XO clock. Not terribly important but nice if it cleanly matches its cousins. 3. Updates the example to use the symbolic name for the RPMH clock and also show that the real devices are currently using 2 address cells / size cells and fixes the spacing on the closing brace. 4. Split into 2 files. In this case they could probably share one file, but let's be consistent. Signed-off-by: Douglas Anderson --- Changes in v4: - Added Rob's review tag. - Fixed schema id to not have "bindings/" as per Rob. Changes in v3: - Added include file to description. - Split videocc bindings into 2 files. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Patch ("dt-bindings: clock: Cleanup qcom,videocc") new for v2. .../bindings/clock/qcom,sc7180-videocc.yaml | 63 +++++++++++++++++++ ...,videocc.yaml => qcom,sdm845-videocc.yaml} | 27 ++++---- 2 files changed, 77 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml rename Documentation/devicetree/bindings/clock/{qcom,videocc.yaml => qcom,sdm845-videocc.yaml} (61%) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml new file mode 100644 index 000000000000..31df901884ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module which supports the clocks, resets and + power domains on SC7180. + + See also dt-bindings/clock/qcom,videocc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-videocc + + clocks: + items: + - description: Board XO source + + clock-names: + items: + - const: bi_tcxo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +examples: + - | + #include + clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml similarity index 61% rename from Documentation/devicetree/bindings/clock/qcom,videocc.yaml rename to Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml index 43cfc893a8d1..9d216c0f11d4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml @@ -1,30 +1,31 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/bindings/clock/qcom,videocc.yaml# +$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Video Clock & Reset Controller Binding +title: Qualcomm Video Clock & Reset Controller Binding for SDM845 maintainers: - Taniya Das description: | Qualcomm video clock control module which supports the clocks, resets and - power domains. + power domains on SDM845. + + See also dt-bindings/clock/qcom,videocc-sdm845.h. properties: compatible: - enum: - - qcom,sc7180-videocc - - qcom,sdm845-videocc + const: qcom,sdm845-videocc clocks: - maxItems: 1 + items: + - description: Board XO source clock-names: items: - - const: xo + - const: bi_tcxo '#clock-cells': const: 1 @@ -48,15 +49,15 @@ required: - '#power-domain-cells' examples: - # Example of VIDEOCC with clock node properties for SDM845: - | + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; - reg = <0xab00000 0x10000>; - clocks = <&rpmhcc 0>; - clock-names = "xo"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Mon Feb 3 18:31:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59C35C35249 for ; Mon, 3 Feb 2020 18:32:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 362552082E for ; Mon, 3 Feb 2020 18:32:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="nYUJygIU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730009AbgBCSca (ORCPT ); Mon, 3 Feb 2020 13:32:30 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41652 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729982AbgBCSc3 (ORCPT ); Mon, 3 Feb 2020 13:32:29 -0500 Received: by mail-pf1-f195.google.com with SMTP id j9so4919608pfa.8 for ; Mon, 03 Feb 2020 10:32:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jo0olqgMnkzurEg4dWqwCBwLi+N2wWcbXWJXOIPzme8=; b=nYUJygIUSbVTXhXFO7+qNnTNnfukf5txscppTz+MTPVZ4oFv8iXEP9AkclCpjSHewY XScnMbFGsaAUEa016ps6Q2v6Ivmcqffkepe0FN9stFAbXRmw7UOMx50mpNzqQdtuvO9p B/yff2fq5OPRcUgalVaEDfWwTZXZ/R520zizk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jo0olqgMnkzurEg4dWqwCBwLi+N2wWcbXWJXOIPzme8=; b=kIZViN6QJBmkUCaEn0PTEZJwIKpmJwAhdeD8LOt/GkhqytkpsfKfV9QD0hcWd05LTk mMI8dZp3ukTVCpaprxIcryRGHZ3UkgOsbw0UZKoIboIr6UITN5OVOaGJtZc+uKNKQi8p O8qA9JGukyUSMQJv9zuJwgip+DpptKY0KERaojLxYH1hiDCiZwPhmR0fZMu9UAFTrsWR tuL6eeza+3BO0D73pMfZ7q7QDdSoVfpD9fGJW6edwrs1jre4HhmVe5eopX0CIo6rwdzg 9Sz9t9Io3jMv7h6Dvpus8rJnrJ/FuPg62Ao3Eb/AgbTkDAdS+Yyw37Kpk8mrpfw08rFA lYZg== X-Gm-Message-State: APjAAAUqLSa4cbNf/g3Xb2Qi16S7LPz4BKzoN5cRH5t5swg6rAdmM6Ts CiPq2whf1s//f+ULJfxdj1Y57SaXrCs= X-Google-Smtp-Source: APXvYqxhWhgChXoUPvOD81GXdBg/j2G+GZuWLcUcvqFxA4nxIp7F10nCV9y5Pk48VXZ+rxgns3JLQQ== X-Received: by 2002:a63:e545:: with SMTP id z5mr26100199pgj.209.1580754748647; Mon, 03 Feb 2020 10:32:28 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:28 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , linux-kernel@vger.kernel.org Subject: [PATCH v4 13/15] clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks Date: Mon, 3 Feb 2020 10:31:46 -0800 Message-Id: <20200203103049.v4.13.If37e4b1b5553ac9db5ea51e84a6eec286cdf209e@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always been doing this it would have prevented a previous bug. See commit 74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6"). Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Patch ("clk: qcom: Use ARRAY_SIZE in videocc-sc7180...") new for v3. Changes in v2: None drivers/clk/qcom/videocc-sc7180.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index 653fc4e6bb6f..c363c3cc544e 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -76,7 +76,7 @@ static struct clk_rcg2 video_cc_venus_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "video_cc_venus_clk_src", .parent_data = video_cc_parent_data_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, From patchwork Mon Feb 3 18:31:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 205178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D558C3F68F for ; Mon, 3 Feb 2020 18:32:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A3F62082E for ; Mon, 3 Feb 2020 18:32:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Gi/MTaHs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730027AbgBCSce (ORCPT ); Mon, 3 Feb 2020 13:32:34 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:41658 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730018AbgBCScc (ORCPT ); Mon, 3 Feb 2020 13:32:32 -0500 Received: by mail-pf1-f196.google.com with SMTP id j9so4919659pfa.8 for ; Mon, 03 Feb 2020 10:32:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GcQPmK/EL5PoNkrImo6wzmVbqHzRjqrCxX5jeH1GDVc=; b=Gi/MTaHsVWTX49DUKWopOV2+0N0eP8zKJ5xdlfwWhsT3f+OcxCe1lJktY9QLSZhIKz 9GB+xpaVIkOlaGWNG9Hw/9IChuRDtoHU5mDGq+BoryAYgWQBAbqS5Ru3Utnyhl0avZZu 0pr9cda/+qTDQotla82A6OnzXWzrW6dXE/Oz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GcQPmK/EL5PoNkrImo6wzmVbqHzRjqrCxX5jeH1GDVc=; b=mlJ3K9ueJAfP9aFydQvWYrladXu6hYiUP/uk1VaE3Pdkpn/3Mls6DxNxxTpFz03wfR 4IAnl3LcIYEQ0Ws9UV/y1nYc0KkIW02cxSeigzAUG/ZT9lm5s6p/Oc6nWNz823x6KJGl o7lavvojhFOVboVpOjmWRauantW8/0GP6UJpaMqizA4QjH0EdftJVHxWb4wIu+41v6cI iCWG02Cy5WFRsFLaXHNtPftA5pUQC+NVMmHW11zkGkkzsnBVCpok2fLsaKoDgv29D/Sz 6VH3N9XEYhZ2IDMJ81iFjyD5pQPn1udugmlhAIa6hhoBXDjWeVo4LPmKyjFwm+VSlcW6 ujWw== X-Gm-Message-State: APjAAAWdetC7Ai2xU1yNoeevgAIMFi0Pmw5cyAEIQLm+Qd83YsNoZueL MjbeQAjWdfu3moZ2qlrJdac4Iw== X-Google-Smtp-Source: APXvYqxZZESrsKizk1ZwzzsrnzuSxnKXSwRiJMTS+PwoYXAq69qJ2bPEUC3EQesTffzVikG7ozabhg== X-Received: by 2002:a63:6787:: with SMTP id b129mr26811249pgc.103.1580754750870; Mon, 03 Feb 2020 10:32:30 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id f9sm21009137pfd.141.2020.02.03.10.32.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 10:32:30 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v4 15/15] arm64: dts: sc7180: Add clock controller nodes Date: Mon, 3 Feb 2020 10:31:48 -0800 Message-Id: <20200203103049.v4.15.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200203183149.73842-1-dianders@chromium.org> References: <20200203183149.73842-1-dianders@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Taniya Das Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson --- Changes in v4: None Changes in v3: - Added videocc include file. - Unlike in v2, use internal name instead of purist name. Changes in v2: - Added includes - Changed various parent names to match bindings / driver arch/arm64/boot/dts/qcom/sc7180.dtsi | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..57ff5e0f7ae6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,8 +5,11 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include +#include #include +#include #include #include #include @@ -1039,6 +1042,20 @@ pinmux { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1151,6 +1168,36 @@ usb_1_dwc3: dwc3@a600000 { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;