From patchwork Mon Feb 10 08:11:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19834C352A4 for ; Mon, 10 Feb 2020 08:12:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E5C712080C for ; Mon, 10 Feb 2020 08:12:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="GCcEMYyY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727587AbgBJIMb (ORCPT ); Mon, 10 Feb 2020 03:12:31 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:3645 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726061AbgBJIMb (ORCPT ); Mon, 10 Feb 2020 03:12:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:11:27 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:12:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:12:30 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:12:29 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:12:29 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:12:28 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 02/21] dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding Date: Mon, 10 Feb 2020 13:41:28 +0530 Message-ID: <1581322307-11140-3-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322287; bh=xL7kQ/KWlZkGepoN2jkiRaQFt/AncKqbOrKpKkGcZoE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=GCcEMYyYkq0c4NllYfRhpudRBQcKhSeKDDFexRicZYt+soYbnb/MWyPWMxG8I6VwD ntzIZRz2ymTOAXE1YGHfp0AdRGBsH1gAEHYJQuI+y0YDZHL9xzcAc3bJ+Ximj+2U85 ete62bz/trYDuojDJ+oZmO/o4Arn/JGHhEXY4RwE/TlcAg7/JDDGfIY3TWrydb4Ju4 tNDWu0P3VRTzT/Lna4tTMrVue3FPDNPFVwiAuHNmdAxU8yqxM6tMmjIsc7zxeeMaII 7yCWfODTWTCxFKf/gAtWmJkBrvGRsiuqa0UppRj9zcO7x8ZARLjbKE2bLZSvPbjmoe 9ErBm7s/c4ZiQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device-tree binding documentation for the XUSB device mode controller present on Tegra210 and Tegra186 SoC. This controller supports the USB 3.0 specification. Signed-off-by: Nagarjuna Kristam Reviewed-by: Rob Herring Acked-by: Thierry Reding --- V4-V5: - No changes. --- V3: - Added Reviewed-by and Acked-by updates to commit message. --- V2: - used enum instead of oneOf and const. - Moved reg, reg-names, clocks, clock-names to property section from allOf. - Limited allOf to min and max items based on soc. - Updated description for power-domains. - Added V1 reference --- V1 - This document is yaml version of [1], with difference of usb-role-switch removal. [1] https://patchwork.kernel.org/patch/11156253/ --- .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 190 +++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml new file mode 100644 index 0000000..b84ed8e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC) + +description: + The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and + USB 3.0 SuperSpeed protocols. + +maintainers: + - Nagarjuna Kristam + - JC Kuo + - Thierry Reding + +properties: + compatible: + items: + - enum: + - nvidia,tegra210-xudc # For Tegra210 + - nvidia,tegra186-xudc # For Tegra186 + + reg: + minItems: 2 + maxItems: 3 + items: + - description: XUSB device controller registers + - description: XUSB device PCI Config registers + - description: XUSB device registers. + + reg-names: + minItems: 2 + maxItems: 3 + items: + - const: base + - const: fpci + - const: ipfs + + interrupts: + maxItems: 1 + description: Must contain the XUSB device interrupt. + + clocks: + minItems: 4 + maxItems: 5 + items: + - description: Clock to enable core XUSB dev clock. + - description: Clock to enable XUSB super speed clock. + - description: Clock to enable XUSB super speed dev clock. + - description: Clock to enable XUSB high speed dev clock. + - description: Clock to enable XUSB full speed dev clock. + + clock-names: + minItems: 4 + maxItems: 5 + items: + - const: dev + - const: ss + - const: ss_src + - const: fs_src + - const: hs_src + + power-domains: + maxItems: 2 + items: + - description: XUSBB(device) power-domain + - description: XUSBA(superspeed) power-domain + + power-domain-names: + maxItems: 2 + items: + - const: dev + - const: ss + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + phandle to the XUSB pad controller that is used to configure the USB pads + used by the XUDC controller. + + phys: + minItems: 1 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + phy-names: + minItems: 1 + items: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + avddio-usb-supply: + description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. + + hvdd-usb-supply: + description: USB controller power supply. Must supply 3.3 V. + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + - power-domain-names + - nvidia,xusb-padctl + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-xudc + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 5 + clock-names: + minItems: 5 + required: + - avddio-usb-supply + - hvdd-usb-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-xudc + then: + properties: + reg: + maxItems: 2 + reg-names: + maxItems: 2 + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + +examples: + - | + #include + #include + #include + + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + + interrupts = ; + + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; + clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; + + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + + nvidia,xusb-padctl = <&padctl>; + + phys = <µ_b>; + phy-names = "usb2-0"; + + avddio-usb-supply = <&vdd_pex_1v05>; + hvdd-usb-supply = <&vdd_3v3_sys>; + }; From patchwork Mon Feb 10 08:11:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A37CDC352A4 for ; Mon, 10 Feb 2020 08:12:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7AFCD2080C for ; Mon, 10 Feb 2020 08:12:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="YT/PO7ai" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727652AbgBJIMj (ORCPT ); Mon, 10 Feb 2020 03:12:39 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8845 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727646AbgBJIMi (ORCPT ); Mon, 10 Feb 2020 03:12:38 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:10 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:12:37 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 10 Feb 2020 00:12:37 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:12:36 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:12:36 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:12:36 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 04/21] phy: tegra: xusb: Add usb-phy support Date: Mon, 10 Feb 2020 13:41:30 +0530 Message-ID: <1581322307-11140-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322330; bh=RDr+f4VWDdPuVBNBVCOfEX4NxvDpI3sfd78jG4l5fGU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=YT/PO7aisR6GHUc1Rf5jttL9AcnBdKXkDSS4lNS6IVnIhmsrYrgudNU//F8pZ9tG9 PaSQSC2lydXVPt72sI0S+C1I8JZPlulFzCqWbg6tOMyZcdXhw9034Q10jJSy1R0JGX 3rLYqlE1YQfyZTXGSapp2Q7DUxNMsqfAegrTS826qRxUsM7zy2yRr8JoAxzE2jxclO NCuSMqBS9qU7lHGz4b2E88hOPBy/y5064KVxtb3Mu+LI7imx4pbHWLelM4iprjorYn jq7GqwDG1aOYQk9sjoJhpAlj7r5B96qtN4X8TwlWdNdFijExs2WBBMPTogHAaZ+Jvw zIhkL4SsDr20A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For USB 2 ports that has usb-role-switch enabled, add usb-phy for corresponding USB 2 phy. USB role changes from role switch are then updated to corresponding host and device mode drivers via usb-phy notifier block. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V5: - No changes. --- V4: - Addressed nit comments from Thierry. - usb_phy_event is set accoring to received usb_role. - Added Acked-by info. V3: - Updated arguments and variable allignments as per Thierry inputs. --- V2: - Added dev_set_drvdata for port->dev. --- drivers/phy/tegra/xusb.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.h | 2 ++ 2 files changed, 86 insertions(+) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 0fdbaa2..2c0e29c 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -532,6 +532,8 @@ static int tegra_xusb_port_init(struct tegra_xusb_port *port, if (err < 0) goto unregister; + dev_set_drvdata(&port->dev, port); + return 0; unregister: @@ -544,6 +546,8 @@ static void tegra_xusb_port_unregister(struct tegra_xusb_port *port) if (!IS_ERR_OR_NULL(port->usb_role_sw)) { of_platform_depopulate(&port->dev); usb_role_switch_unregister(port->usb_role_sw); + cancel_work_sync(&port->usb_phy_work); + usb_remove_phy(&port->usb_phy); } device_unregister(&port->dev); @@ -562,15 +566,70 @@ static const char * const usb_roles[] = { [USB_ROLE_DEVICE] = "device", }; +static enum usb_phy_events to_usb_phy_event(enum usb_role role) +{ + switch (role) { + case USB_ROLE_DEVICE: return USB_EVENT_VBUS; + case USB_ROLE_HOST: return USB_EVENT_ID; + default: return USB_EVENT_NONE; + } +} + +static void tegra_xusb_usb_phy_work(struct work_struct *work) +{ + struct tegra_xusb_port *port = container_of(work, + struct tegra_xusb_port, + usb_phy_work); + enum usb_role role = usb_role_switch_get_role(port->usb_role_sw); + + usb_phy_set_event(&port->usb_phy, to_usb_phy_event(role)); + + dev_dbg(&port->dev, "%s(): calling notifier for role %s\n", __func__, + usb_roles[role]); + + atomic_notifier_call_chain(&port->usb_phy.notifier, 0, &port->usb_phy); +} + static int tegra_xusb_role_sw_set(struct device *dev, enum usb_role role) { + struct tegra_xusb_port *port = dev_get_drvdata(dev); + dev_dbg(dev, "%s(): role %s\n", __func__, usb_roles[role]); + schedule_work(&port->usb_phy_work); + + return 0; +} + +static int tegra_xusb_set_peripheral(struct usb_otg *otg, + struct usb_gadget *gadget) +{ + struct tegra_xusb_port *port = container_of(otg->usb_phy, + struct tegra_xusb_port, + usb_phy); + + if (gadget != NULL) + schedule_work(&port->usb_phy_work); + return 0; } +static int tegra_xusb_set_host(struct usb_otg *otg, struct usb_bus *host) +{ + struct tegra_xusb_port *port = container_of(otg->usb_phy, + struct tegra_xusb_port, + usb_phy); + + if (host != NULL) + schedule_work(&port->usb_phy_work); + + return 0; +} + + static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port) { + struct tegra_xusb_lane *lane; struct usb_role_switch_desc role_sx_desc = { .fwnode = dev_fwnode(&port->dev), .set = tegra_xusb_role_sw_set, @@ -597,6 +656,31 @@ static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port) return err; } + INIT_WORK(&port->usb_phy_work, tegra_xusb_usb_phy_work); + + port->usb_phy.otg = devm_kzalloc(&port->dev, sizeof(struct usb_otg), + GFP_KERNEL); + if (!port->usb_phy.otg) + return -ENOMEM; + + lane = tegra_xusb_find_lane(port->padctl, "usb2", port->index); + + /* + * Assign phy dev to usb-phy dev. Host/device drivers can use phy + * reference to retrieve usb-phy details. + */ + port->usb_phy.dev = &lane->pad->lanes[port->index]->dev; + port->usb_phy.dev->driver = port->padctl->dev->driver; + port->usb_phy.otg->usb_phy = &port->usb_phy; + port->usb_phy.otg->set_peripheral = tegra_xusb_set_peripheral; + port->usb_phy.otg->set_host = tegra_xusb_set_host; + + err = usb_add_phy_dev(&port->usb_phy); + if (err < 0) { + dev_err(&port->dev, "Failed to add USB PHY: %d\n", err); + return err; + } + /* populate connector entry */ of_platform_populate(port->dev.of_node, NULL, NULL, &port->dev); diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 9f27899..2345657 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -268,6 +268,8 @@ struct tegra_xusb_port { struct device dev; struct usb_role_switch *usb_role_sw; + struct work_struct usb_phy_work; + struct usb_phy usb_phy; const struct tegra_xusb_port_ops *ops; }; From patchwork Mon Feb 10 08:11:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 204997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 176AEC3B184 for ; Mon, 10 Feb 2020 08:14:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC30D2080C for ; Mon, 10 Feb 2020 08:14:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="YPYSbhgZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727691AbgBJIMr (ORCPT ); Mon, 10 Feb 2020 03:12:47 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18207 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727522AbgBJIMq (ORCPT ); Mon, 10 Feb 2020 03:12:46 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:30 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:12:44 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:12:44 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:12:44 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:12:44 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:12:43 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 06/21] phy: tegra: xusb: Add set_mode support for USB 2 phy on Tegra210 Date: Mon, 10 Feb 2020 13:41:32 +0530 Message-ID: <1581322307-11140-7-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322350; bh=XodaTLC2VSUtO4PzxYzekka/lD0xigZ8PFJGJP2uRos=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=YPYSbhgZ51pqR3ZE43fV70bcNe56pUZCrgXIIbw1+xXCY/EizAQJ/7c9yFOL8CqzK r8Uoueq2tNR0t0gL6j1E3pC5uLn+QXsS1EXoLgmFVKzEXNKxx12spEMYy1KyWR8a23 Io3olTF5LkFqvtk5to6YoieOi1aJT2CUF+BkNKXeS9LiAk4eWyxh/knS3bTUJSQ2BW ZH/cxE1ORtIQGzece6V5vIhbEvfjOHQipe2Fdu9pS8n4Blxb9/+qjvCfS5Y2mDX4rc MVte5RpmfhZGTqGUPUw6oEPO4XPnjlgazwgUGeeY9ynhBuEbnGOYSbCGImcTf6Qz0J RH6kuYiJgiS8Q== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for set_mode on USB 2 phy. This allow XUSB host/device mode drivers to configure the hardware to corresponding modes. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V5: - No changes. --- V4: - Added comment for conditional regulator disable. - Added Acked-by info. --- V2-V3: - No changes in this version --- drivers/phy/tegra/xusb-tegra210.c | 131 ++++++++++++++++++++++++++++++-------- 1 file changed, 104 insertions(+), 27 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index 394913b..54d6826 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -236,6 +236,7 @@ #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8 +#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0 struct tegra210_xusb_fuse_calibration { u32 hs_curr_level[4]; @@ -935,6 +936,103 @@ static int tegra210_usb2_phy_exit(struct phy *phy) return tegra210_xusb_padctl_disable(lane->pad->padctl); } +static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, + bool status) +{ + u32 value; + + dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); + + if (status) { + value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; + value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT); + value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT; + } else { + value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; + } + + padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); + + return 0; +} + +static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, + bool status) +{ + u32 value; + + dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); + + if (status) { + if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) { + value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); + usleep_range(1000, 2000); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); + } + + value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT); + value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT; + } else { + value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT); + value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << + XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT; + } + + padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); + + return 0; +} + +static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, + lane->index); + int err = 0; + + mutex_lock(&padctl->lock); + + dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); + + if (mode == PHY_MODE_USB_OTG) { + if (submode == USB_ROLE_HOST) { + tegra210_xusb_padctl_id_override(padctl, true); + + err = regulator_enable(port->supply); + } else if (submode == USB_ROLE_DEVICE) { + tegra210_xusb_padctl_vbus_override(padctl, true); + } else if (submode == USB_ROLE_NONE) { + /* + * When port is peripheral only or role transitions to + * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not + * be enabled. + */ + if (regulator_is_enabled(port->supply)) + regulator_disable(port->supply); + + tegra210_xusb_padctl_id_override(padctl, false); + tegra210_xusb_padctl_vbus_override(padctl, false); + } + } + + mutex_unlock(&padctl->lock); + + return err; +} + static int tegra210_usb2_phy_power_on(struct phy *phy) { struct tegra_xusb_lane *lane = phy_get_drvdata(phy); @@ -1048,9 +1146,11 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) padctl_writel(padctl, value, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); - err = regulator_enable(port->supply); - if (err) - return err; + if (port->supply && port->mode == USB_DR_MODE_HOST) { + err = regulator_enable(port->supply); + if (err) + return err; + } mutex_lock(&padctl->lock); @@ -1164,6 +1264,7 @@ static const struct phy_ops tegra210_usb2_phy_ops = { .exit = tegra210_usb2_phy_exit, .power_on = tegra210_usb2_phy_power_on, .power_off = tegra210_usb2_phy_power_off, + .set_mode = tegra210_usb2_phy_set_mode, .owner = THIS_MODULE, }; @@ -2023,30 +2124,6 @@ static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = { .map = tegra210_usb3_port_map, }; -static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, - bool status) -{ - u32 value; - - dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); - - value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); - - if (status) { - value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; - value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK << - XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT); - value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING << - XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT; - } else { - value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON; - } - - padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); - - return 0; -} - static int tegra210_utmi_port_reset(struct phy *phy) { struct tegra_xusb_padctl *padctl; From patchwork Mon Feb 10 08:11:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 204998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14DACC3B184 for ; Mon, 10 Feb 2020 08:14:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF64F21739 for ; Mon, 10 Feb 2020 08:14:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="fmB8vTIV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727588AbgBJIMu (ORCPT ); Mon, 10 Feb 2020 03:12:50 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18218 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727707AbgBJIMu (ORCPT ); Mon, 10 Feb 2020 03:12:50 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:34 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:12:48 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:12:48 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:12:47 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:12:47 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:12:47 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 07/21] phy: tegra: xusb: Add set_mode support for UTMI phy on Tegra186 Date: Mon, 10 Feb 2020 13:41:33 +0530 Message-ID: <1581322307-11140-8-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322354; bh=Y389Vbo0qSoZ7bEjswVj6WBVgDKXBxnfWfVQytx9TXQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fmB8vTIV47+KexiFUE1IeSs6EU1t97acpRtjWo2P4aej61nVuGGnicbbC2YoompI0 TZCr9Y4Z381rx4X3u11EYZ6NcWAwZEXN06AsckYrDOCf0Dy+WPD3e5spXEt50bQsf0 msxRoBqijJSi8ze58GVIwAacinr+TDueVOg3COFkLiPOIFWO4C3nxAuLvRfpj8NT6A btP6afPG6EBcJBZDeOFaHrWe8xbDyPuuZ2KwSMBkAhwWItB0+GoOrjHlfAoOHuc2vO LeG+ouGH9i9SNTvsrlok68JMhjKGo02UrjGlYGo98Z4syC+hVbOSRtXDT8AioXPVC2 XduJNL+wKPD1A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for set_mode on UTMI phy. This allow XUSB host/device mode drivers to configure the hardware to corresponding modes. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V5: - No changes. --- V4: - Added comment for conditional regulator disable. - Added Acked-by info. --- V2-V3: - No changes in this version --- drivers/phy/tegra/xusb-tegra186.c | 114 ++++++++++++++++++++++++++++++-------- 1 file changed, 92 insertions(+), 22 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 84c2739..ea62251 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -301,6 +301,97 @@ static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy) tegra186_utmi_bias_pad_power_off(padctl); } +static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, + bool status) +{ + u32 value; + + dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); + + value = padctl_readl(padctl, USB2_VBUS_ID); + + if (status) { + value |= VBUS_OVERRIDE; + value &= ~ID_OVERRIDE(~0); + value |= ID_OVERRIDE_FLOATING; + } else { + value &= ~VBUS_OVERRIDE; + } + + padctl_writel(padctl, value, USB2_VBUS_ID); + + return 0; +} + +static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, + bool status) +{ + u32 value; + + dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); + + value = padctl_readl(padctl, USB2_VBUS_ID); + + if (status) { + if (value & VBUS_OVERRIDE) { + value &= ~VBUS_OVERRIDE; + padctl_writel(padctl, value, USB2_VBUS_ID); + usleep_range(1000, 2000); + + value = padctl_readl(padctl, USB2_VBUS_ID); + } + + value &= ~ID_OVERRIDE(~0); + value |= ID_OVERRIDE_GROUNDED; + } else { + value &= ~ID_OVERRIDE(~0); + value |= ID_OVERRIDE_FLOATING; + } + + padctl_writel(padctl, value, USB2_VBUS_ID); + + return 0; +} + +static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, + lane->index); + int err = 0; + + mutex_lock(&padctl->lock); + + dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); + + if (mode == PHY_MODE_USB_OTG) { + if (submode == USB_ROLE_HOST) { + tegra186_xusb_padctl_id_override(padctl, true); + + err = regulator_enable(port->supply); + } else if (submode == USB_ROLE_DEVICE) { + tegra186_xusb_padctl_vbus_override(padctl, true); + } else if (submode == USB_ROLE_NONE) { + /* + * When port is peripheral only or role transitions to + * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not + * enabled. + */ + if (regulator_is_enabled(port->supply)) + regulator_disable(port->supply); + + tegra186_xusb_padctl_id_override(padctl, false); + tegra186_xusb_padctl_vbus_override(padctl, false); + } + } + + mutex_unlock(&padctl->lock); + + return err; +} + static int tegra186_utmi_phy_power_on(struct phy *phy) { struct tegra_xusb_lane *lane = phy_get_drvdata(phy); @@ -439,6 +530,7 @@ static const struct phy_ops utmi_phy_ops = { .exit = tegra186_utmi_phy_exit, .power_on = tegra186_utmi_phy_power_on, .power_off = tegra186_utmi_phy_power_off, + .set_mode = tegra186_utmi_phy_set_mode, .owner = THIS_MODULE, }; @@ -857,28 +949,6 @@ static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) { } -static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, - bool status) -{ - u32 value; - - dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); - - value = padctl_readl(padctl, USB2_VBUS_ID); - - if (status) { - value |= VBUS_OVERRIDE; - value &= ~ID_OVERRIDE(~0); - value |= ID_OVERRIDE_FLOATING; - } else { - value &= ~VBUS_OVERRIDE; - } - - padctl_writel(padctl, value, USB2_VBUS_ID); - - return 0; -} - static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .probe = tegra186_xusb_padctl_probe, .remove = tegra186_xusb_padctl_remove, From patchwork Mon Feb 10 08:11:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 204999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68A63C3B184 for ; Mon, 10 Feb 2020 08:14:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4005B21739 for ; Mon, 10 Feb 2020 08:14:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="lAH+8G2c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727793AbgBJINB (ORCPT ); Mon, 10 Feb 2020 03:13:01 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18259 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727764AbgBJINA (ORCPT ); Mon, 10 Feb 2020 03:13:00 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:45 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:12:59 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:12:59 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:12:59 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:12:59 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:12:58 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 10/21] usb: gadget: tegra-xudc: Add usb-phy support Date: Mon, 10 Feb 2020 13:41:36 +0530 Message-ID: <1581322307-11140-11-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322365; bh=fM3ZAjPUPkY9CGZ1xeMcfY9eoH1/576Ng/4psDfAtjk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=lAH+8G2cLInkZY2vGi41FsrbwhCtv57O8Jbx2lGWXMjWg5PfYsbFmEMXZYAtKpG6+ gB9R/8bac+UXihE1KyvfyKWXr1WiNs4J+lDf7pn+uGQ/xpZPsGD8HYepoPAQDMiiFX 48i8mGZ3P/DYw8aoqQOtzP5zXS8FhEUMhG45ca/Ydfx+05Al+JbwIj6H/xafomwh8Q hnk2abgpIVXF/a4sxD1cul0sraBMphYQ6Ju4Pg5sG894FGSs/A8JaEoTsaIPlsHo0G 9AoCKQ5PK/f0ikNo6eWS5SjehozLF6NsdV9eLsK/BvfJ9lgEk0GVjzIYF0jgrI0GC0 eNOm7Uwihxr6A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org usb-phy is used to get notified on the USB role changes. Get usb-phy from the UTMI PHY. Signed-off-by: Nagarjuna Kristam --- V5: - No changes. --- V4: - Addressed nit comments from Thierry. - usb_phy_event is used to detect device mode instead of usb_role. --- V2-V3: - No changes in this version --- drivers/usb/gadget/udc/tegra-xudc.c | 48 ++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index acecdcf..7411dd15 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -26,7 +26,9 @@ #include #include #include +#include #include +#include #include /* XUSB_DEV registers */ @@ -487,6 +489,9 @@ struct tegra_xudc { bool suspended; bool powergated; + struct usb_phy *usbphy; + struct notifier_block vbus_nb; + struct completion disconnect_complete; bool selfpowered; @@ -669,6 +674,31 @@ static void tegra_xudc_usb_role_sw_work(struct work_struct *work) tegra_xudc_device_mode_off(xudc); } +static int tegra_xudc_vbus_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct tegra_xudc *xudc = container_of(nb, struct tegra_xudc, + vbus_nb); + struct usb_phy *usbphy = (struct usb_phy *)data; + + dev_dbg(xudc->dev, "%s(): event is %d\n", __func__, usbphy->last_event); + + if ((xudc->device_mode && usbphy->last_event == USB_EVENT_VBUS) || + (!xudc->device_mode && usbphy->last_event != USB_EVENT_VBUS)) { + dev_dbg(xudc->dev, "Same role(%d) received. Ignore", + xudc->device_mode); + return NOTIFY_OK; + } + + xudc->device_mode = (usbphy->last_event == USB_EVENT_VBUS) ? true : + false; + + if (!xudc->suspended) + schedule_work(&xudc->usb_role_sw_work); + + return NOTIFY_OK; +} + static void tegra_xudc_plc_reset_work(struct work_struct *work) { struct delayed_work *dwork = to_delayed_work(work); @@ -1937,6 +1967,9 @@ static int tegra_xudc_gadget_start(struct usb_gadget *gadget, xudc_writel(xudc, val, CTRL); } + if (xudc->usbphy) + otg_set_peripheral(xudc->usbphy->otg, gadget); + xudc->driver = driver; unlock: dev_dbg(xudc->dev, "%s: ret value is %d", __func__, ret); @@ -1957,6 +1990,9 @@ static int tegra_xudc_gadget_stop(struct usb_gadget *gadget) spin_lock_irqsave(&xudc->lock, flags); + if (xudc->usbphy) + otg_set_peripheral(xudc->usbphy->otg, NULL); + val = xudc_readl(xudc, CTRL); val &= ~(CTRL_IE | CTRL_ENABLE); xudc_writel(xudc, val, CTRL); @@ -3561,9 +3597,15 @@ static int tegra_xudc_probe(struct platform_device *pdev) INIT_DELAYED_WORK(&xudc->port_reset_war_work, tegra_xudc_port_reset_war_work); - /* Set the mode as device mode and this keeps phy always ON */ - xudc->device_mode = true; - schedule_work(&xudc->usb_role_sw_work); + xudc->vbus_nb.notifier_call = tegra_xudc_vbus_notify; + xudc->usbphy = devm_usb_get_phy_by_node(xudc->dev, + xudc->utmi_phy->dev.of_node, + &xudc->vbus_nb); + if (IS_ERR(xudc->usbphy)) { + err = PTR_ERR(xudc->usbphy); + dev_err(xudc->dev, "failed to get USB PHY: %d\n", err); + goto free_eps; + } pm_runtime_enable(&pdev->dev); From patchwork Mon Feb 10 08:11:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12036C352A4 for ; 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by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:13:03 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:13:02 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:13:02 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:13:02 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 11/21] usb: gadget: tegra-xudc: use phy_set_mode to set/unset device mode Date: Mon, 10 Feb 2020 13:41:37 +0530 Message-ID: <1581322307-11140-12-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322369; bh=enSyMPzTayP8VechD0lnuAhplv7sin8uwClOTcl+XQQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=goSBVyeEQff02Q8ND2Q4UCmjWnlG9dvVi/KlHeqv1EvT4kjOOTYU6xi3+bEFitE86 MJcMcYC8ahXAGfpisjWa5IgedVcQ6pPpXdpxe86uwLJ48zSu8B2QBjbeIu+h6Wru7K YkcPxg8mnstFTwbhnMXIiBdjoeyPiKS8xBd4lMmtrlMMzkdLRz3NWzld7coAr6j02E 98uxkEeg7EMd2zAyeCLVr8sgL4TB62Hw9UYvzxGxRq6WiQGdyVLa03Rjp23HPNVY+4 z+t0nb/geyw71ww3eloeuR6Sce7M1Ft25m8DSknK8FWWuN1qVg9RS/xKcLOoJV1cui DD2sj1s7MVbmw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When device mode is set/uset, VBUS override activity is done via exported functions from padctl driver. Use phy_set_mode() instead. Signed-off-by: Nagarjuna Kristam --- V5: - No changes. --- V4: - Updated commit message as per comments from Thierry. --- V2-V3: - No changes in this version --- drivers/usb/gadget/udc/tegra-xudc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 7411dd15..a2299ee 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -612,7 +612,7 @@ static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) dev_dbg(xudc->dev, "device mode on\n"); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, true); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_DEVICE); } static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) @@ -627,7 +627,7 @@ static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) reinit_completion(&xudc->disconnect_complete); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, false); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> PORTSC_PLS_SHIFT; @@ -714,9 +714,11 @@ static void tegra_xudc_plc_reset_work(struct work_struct *work) if (pls == PORTSC_PLS_INACTIVE) { dev_info(xudc->dev, "PLS = Inactive. Toggle VBUS\n"); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, - false); - tegra_xusb_padctl_set_vbus_override(xudc->padctl, true); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, + USB_ROLE_NONE); + phy_set_mode_ext(xudc->utmi_phy, PHY_MODE_USB_OTG, + USB_ROLE_DEVICE); + xudc->wait_csc = false; } } From patchwork Mon Feb 10 08:11:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70FD4C352A4 for ; Mon, 10 Feb 2020 08:13:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4826921739 for ; Mon, 10 Feb 2020 08:13:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="UZnzq3I+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727852AbgBJINL (ORCPT ); Mon, 10 Feb 2020 03:13:11 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:3719 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727842AbgBJINL (ORCPT ); Mon, 10 Feb 2020 03:13:11 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:08 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:13:10 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:13:10 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:13:10 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:13:10 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:13:09 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 13/21] arm64: tegra: update OTG port entries for jetson-tx1 Date: Mon, 10 Feb 2020 13:41:39 +0530 Message-ID: <1581322307-11140-14-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322328; bh=y15v5G/rXu3alwT2NMBoAGJAjAx5EZBOKD4pJ4se3Qc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=UZnzq3I+GqMM4DPJT2ihWsoUb+zT6RE8ylNZJCZbv5HRwCUMrvV60SfL/RuY50lyZ ESbBnqh6L1VBYbyxqCLvkVaDghZJLD4SnPY6t/uEWO5h2xv9G2VLivIvrrcOgd51Zz YsAUuTQmutiWejm9MmOL3pnFAIPO+/wk1uuQY5wQhUY6WVnCZ/INSG3rRxZTa+HFnB JmS3MfdjJsNChDIztVm/uJ2bm+kYS5SK9QgUKDeYZCcrAIoB+l3KEdQXVAGpSqknQh kY9vak3k3K0zcrOLlKbQVnEpiBujY0NNOCDzBBxGkddJiisS19cE2JQd1lk3y1yaPW aGN9/bzQopf6A== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Populate OTG vbus regulator. Add usb-role-switch entry to USB 2-0 port and corresponding connector details. Signed-off-by: Nagarjuna Kristam --- V2-V5: - No changes in this version --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index b009507..18c0610 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1336,7 +1336,6 @@ <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", "usb3-1"; - dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; avdd-usb-supply = <&vdd_3v3_sys>; @@ -1440,7 +1439,19 @@ ports { usb2-0 { status = "okay"; + vbus-supply = <&vdd_usb_vbus_otg>; mode = "otg"; + + usb-role-switch; + connector { + compatible = "usb-b-connector", + "gpio-usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpio = <&gpio TEGRA_GPIO(Z, 0) + GPIO_ACTIVE_LOW>; + id-gpio = <&pmic 0 0>; + }; }; usb2-1 { @@ -1606,6 +1617,17 @@ vin-supply = <&vdd_5v0_sys>; }; + vdd_usb_vbus_otg: regulator@11 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "USB_VBUS_EN0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + vdd_hdmi: regulator@10 { compatible = "regulator-fixed"; reg = <10>; From patchwork Mon Feb 10 08:11:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DDB3C352A4 for ; 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by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:13:17 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:13:17 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:13:17 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:13:16 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 15/21] arm64: tegra: Add xudc node for Tegra210 Date: Mon, 10 Feb 2020 13:41:41 +0530 Message-ID: <1581322307-11140-16-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322371; bh=sFULIdqYSawgY10+NddCDDj7IoncaxsFRSfYUUk88QM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AAU8V7JXvaFQVOEsoje9zxyW7S6wW2/QpamfYi0ISC+JDBSICooQW24htmlO9gtZA lpxLpUWP9gd3H0ANZt1ZFD19xx91C+KQzyNG+sgphWukCcvLlhJxYhEd2lWw6AyPy7 /bpMOx4UvNJAZmM+ssWkwUMV+Fl4qchoo19VT4UTjsXwP9KIlfN8XdbqrAfVHyX2s0 NQkJ20uGYshiIOewomCEaVsUdjzxdi3HwQJimJMqFRA/Fhn+3N9n40HYxnCpSCRyDO Hi0xX/SZuE007qUfN3H9xk/RqZBlJZ6BFgymSR0oOO9Q4WELVWPWH2plmel25g3/CK rnVaPROcUWEEw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- V2-V5: - Updated clocks and clock-names sequence as per change in bindings doc. --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c6325..dfce47b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1207,6 +1207,25 @@ status = "disabled"; }; + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; + clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra210-mipi"; reg = <0x0 0x700e3000 0x0 0x100>; From patchwork Mon Feb 10 08:11:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3156C3B185 for ; Mon, 10 Feb 2020 08:13:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC14721739 for ; Mon, 10 Feb 2020 08:13:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ajmBCPQR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727435AbgBJIN1 (ORCPT ); Mon, 10 Feb 2020 03:13:27 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8968 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727916AbgBJINZ (ORCPT ); Mon, 10 Feb 2020 03:13:25 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:58 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:13:25 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:13:25 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:13:25 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:13:24 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:13:24 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 17/21] arm64: tegra: Add xudc node for Tegra186 Date: Mon, 10 Feb 2020 13:41:43 +0530 Message-ID: <1581322307-11140-18-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322378; bh=BuWHHhwvPmPvH7bLgd46nyYsIXSOV7ID3/i1Lv0Pluc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ajmBCPQR+EghjqZm4eAvgZP2vSXM9t1tJ6Ha4U03+La43jNsYXKu8catd+jA1g4gt nqBlR3ASZezdZzHir4Paw94vh+t39GFxEPTaMMwN9s2FRNGrVGGtks5h7UkjpQu8Ng ElHerZI6t0NPzJOZqIchQe+isVevKSaj+mvIWGv3VIKiWHS8yDBXVwzAAn5Ee2K0vF KzpI3ZvWEFsX0bkqBg/NSnnnbJ13xpGW0zuwyvUzH3SdbHuuiTQAT/GhU1s9vgi4p2 dMGyFMulxd3BPA04D/BS9oa4MFbxtamARZW4paGvy78BRoqxJn1XpRm3YW04eHZjBe WL1YveajXTIzQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra186 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- V2-V5: - No changes in this version --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index c905527..58100fb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -572,6 +572,25 @@ nvidia,xusb-padctl = <&padctl>; }; + usb@3550000 { + compatible = "nvidia,tegra186-xudc"; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA186_CLK_XUSB_SS>, + <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA186_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + iommus = <&smmu TEGRA186_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + fuse@3820000 { compatible = "nvidia,tegra186-efuse"; reg = <0x0 0x03820000 0x0 0x10000>; From patchwork Mon Feb 10 08:11:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 205001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27919C352A4 for ; Mon, 10 Feb 2020 08:13:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F3C8E21739 for ; Mon, 10 Feb 2020 08:13:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Mky4OvM9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727969AbgBJINh (ORCPT ); Mon, 10 Feb 2020 03:13:37 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:3865 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727575AbgBJINh (ORCPT ); Mon, 10 Feb 2020 03:13:37 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 10 Feb 2020 00:12:33 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 10 Feb 2020 00:13:36 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 10 Feb 2020 00:13:36 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 10 Feb 2020 08:13:35 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 10 Feb 2020 08:13:35 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 10 Feb 2020 00:13:35 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V5 20/21] arm64: tegra: update OTG port entries for jetson-nano Date: Mon, 10 Feb 2020 13:41:46 +0530 Message-ID: <1581322307-11140-21-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> References: <1581322307-11140-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1581322354; bh=Ldb3UZv2AkiRIXVHdJWKa0Yw4NWPxPcisyX+eCZxiBI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Mky4OvM96hyVUxpYCW2Xsv5tsewJMJq6QW73Gna1zczfIAis71uwC6FXfVIqNHhKE OPp1gMNiTP4oALNnEvttxTIK0TwPzPxlI3WIL1Vx3Thq3XGqkrhX/bHh7Z1z2O7ERz Ki9ImdeMruvJ4vEyD7rzJc+DLzOQo+jXncoGIOz7a++clQSouGrcVST+HK3n8YZ8K1 3SfImntwLpbY/ZdPkPnKVm4RUv3ASpeS0a0s6lhm6eYtCKLGyRErWQeT+Pn1mbWv2i XdoR+Oe0ut7LnLeGpOTUjnpIHrOnyVRZaJ9TvkUDD0mNYgfj6ZNbwQNrVHNYhROuYU QMFbz5VHezWiA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add usb-role-switch entry to peripheral usb port and add corresponding connector details. Signed-off-by: Nagarjuna Kristam --- V5: - New patch in the series. --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9101d3a..b75f69d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -505,7 +505,17 @@ ports { usb2-0 { status = "okay"; - mode = "otg"; + mode = "peripheral"; + + usb-role-switch; + connector { + compatible = "usb-b-connector", + "gpio-usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) + GPIO_ACTIVE_LOW>; + }; }; usb2-1 {