From patchwork Fri Feb 14 17:27:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2B25C2BA83 for ; Fri, 14 Feb 2020 17:28:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B42B924650 for ; Fri, 14 Feb 2020 17:28:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390958AbgBNR2Z (ORCPT ); Fri, 14 Feb 2020 12:28:25 -0500 Received: from out28-221.mail.aliyun.com ([115.124.28.221]:38590 "EHLO out28-221.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391144AbgBNR2W (ORCPT ); Fri, 14 Feb 2020 12:28:22 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07512346|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.63799-0.012238-0.349772; DS=CONTINUE|ham_system_inform|0.345318-0.00103386-0.653648; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07440; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Go9djQb_1581701284; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Go9djQb_1581701284) by smtp.aliyun-inc.com(10.147.41.231); Sat, 15 Feb 2020 01:28:17 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v5 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. Date: Sat, 15 Feb 2020 01:27:37 +0800 Message-Id: <1581701262-110556-3-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is not necessary to use spinlock when reading registers, so remove it from cgu.c. Suggested-by: Paul Cercueil Suggested-by: Paul Burton Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v2: New patch. v2->v3: Adjust order from [5/5] in v2 to [1/5] in v3. v3->v4: Remove the spinlock around ingenic_cgu_gate_get(). v4->v5: Rebase on top of kernel 5.6-rc1. drivers/clk/ingenic/cgu.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 6e96303..ab1302a 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) const struct ingenic_cgu_pll_info *pll_info; unsigned m, n, od_enc, od; bool bypass; - unsigned long flags; u32 ctl; clk_info = &cgu->clock_info[ingenic_clk->idx]; BUG_ON(clk_info->type != CGU_CLK_PLL); pll_info = &clk_info->pll; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m += pll_info->m_offset; @@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; - unsigned long flags; u32 ctl; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); return !!(ctl & BIT(pll_info->enable_bit)); } @@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw) struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info; - unsigned long flags; int enabled = 1; clk_info = &cgu->clock_info[ingenic_clk->idx]; - if (clk_info->type & CGU_CLK_GATE) { - spin_lock_irqsave(&cgu->lock, flags); + if (clk_info->type & CGU_CLK_GATE) enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); - spin_unlock_irqrestore(&cgu->lock, flags); - } return enabled; } From patchwork Fri Feb 14 17:27:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED849C3B1A6 for ; Fri, 14 Feb 2020 17:28:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D447624650 for ; Fri, 14 Feb 2020 17:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394636AbgBNR2i (ORCPT ); Fri, 14 Feb 2020 12:28:38 -0500 Received: from out28-3.mail.aliyun.com ([115.124.28.3]:51964 "EHLO out28-3.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403808AbgBNR2i (ORCPT ); Fri, 14 Feb 2020 12:28:38 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0743638|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.271369-0.00538365-0.723248; DS=CONTINUE|ham_system_inform|0.0395298-0.000262629-0.960208; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03303; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Go9djQb_1581701284; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Go9djQb_1581701284) by smtp.aliyun-inc.com(10.147.41.231); Sat, 15 Feb 2020 01:28:18 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v5 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830. Date: Sat, 15 Feb 2020 01:27:38 +0800 Message-Id: <1581701262-110556-4-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, the original "reg" was changed to "pll_reg", and a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: 1.Use two fields (pll_reg & bypass_reg) instead of the 2-values array (reg[2]). 2.Remove the "pll_info->version" and add a "pll_info->rate_multiplier". 3.Fix the coding style and add more detailed commit message. 4.Change my Signed-off-by from "Zhou Yanjie " to "周琰杰 (Zhou Yanjie) " because the old mailbox is in an unstable state. v2->v3: Adjust order from [1/5] in v2 to [2/5] in v3. v3->v4: Merge [3/5] in v3 into this patch. v4->v5: Rebase on top of kernel 5.6-rc1. drivers/clk/ingenic/cgu.c | 32 +++++++++++++++++++++----------- drivers/clk/ingenic/cgu.h | 8 ++++++-- drivers/clk/ingenic/jz4725b-cgu.c | 4 +++- drivers/clk/ingenic/jz4740-cgu.c | 4 +++- drivers/clk/ingenic/jz4770-cgu.c | 8 ++++++-- drivers/clk/ingenic/jz4780-cgu.c | 4 +++- drivers/clk/ingenic/x1000-cgu.c | 8 ++++++-- 7 files changed, 48 insertions(+), 20 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index ab1302a..7d859e4 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -82,7 +82,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) BUG_ON(clk_info->type != CGU_CLK_PLL); pll_info = &clk_info->pll; - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->pll_reg); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m += pll_info->m_offset; @@ -90,6 +90,9 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n += pll_info->n_offset; od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + ctl = readl(cgu->base + pll_info->bypass_reg); + bypass = !pll_info->no_bypass_bit && !!(ctl & BIT(pll_info->bypass_bit)); @@ -103,7 +106,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) BUG_ON(od == pll_info->od_max); od++; - return div_u64((u64)parent_rate * m, n * od); + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, + n * od); } static unsigned long @@ -136,7 +140,8 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, if (pod) *pod = od; - return div_u64((u64)parent_rate * m, n * od); + return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, + n * od); } static inline const struct ingenic_cgu_clk_info *to_clk_info( @@ -180,7 +185,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, clk_info->name, req_rate, rate); spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->pll_reg); ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); ctl |= (m - pll_info->m_offset) << pll_info->m_shift; @@ -191,7 +196,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->pll_reg); spin_unlock_irqrestore(&cgu->lock, flags); return 0; @@ -209,16 +214,21 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->bypass_reg); ctl &= ~BIT(pll_info->bypass_bit); + + writel(ctl, cgu->base + pll_info->bypass_reg); + + ctl = readl(cgu->base + pll_info->pll_reg); + ctl |= BIT(pll_info->enable_bit); - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->pll_reg); /* wait for the PLL to stabilise */ for (i = 0; i < timeout; i++) { - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->pll_reg); if (ctl & BIT(pll_info->stable_bit)) break; mdelay(1); @@ -242,11 +252,11 @@ static void ingenic_pll_disable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->pll_reg); ctl &= ~BIT(pll_info->enable_bit); - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->pll_reg); spin_unlock_irqrestore(&cgu->lock, flags); } @@ -258,7 +268,7 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; u32 ctl; - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->pll_reg); return !!(ctl & BIT(pll_info->enable_bit)); } diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 0dc8004..f7b6908 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -16,7 +16,9 @@ /** * struct ingenic_cgu_pll_info - information about a PLL - * @reg: the offset of the PLL's control register within the CGU + * @pll_reg: the offset of the PLL's control register within the CGU + * @bypass_reg: the offset of the bypass control register within the CGU + * @rate_multiplier: the multiplier needed by pll rate calculation * @m_shift: the number of bits to shift the multiplier value by (ie. the * index of the lowest bit of the multiplier value in the PLL's * control register) @@ -43,7 +45,9 @@ * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { - unsigned reg; + unsigned pll_reg; + unsigned bypass_reg; + unsigned rate_multiplier; const s8 *od_encoding; u8 m_shift, m_bits, m_offset; u8 n_shift, n_bits, n_offset; diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index a3b4635..0b05167 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -53,7 +53,9 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "pll", CGU_CLK_PLL, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .pll = { - .reg = CGU_REG_CPPCR, + .pll_reg = CGU_REG_CPPCR, + .bypass_reg = CGU_REG_CPPCR, + .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 4f0e92c..78f31df 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -68,7 +68,9 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "pll", CGU_CLK_PLL, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .pll = { - .reg = CGU_REG_CPPCR, + .pll_reg = CGU_REG_CPPCR, + .bypass_reg = CGU_REG_CPPCR, + .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 956dd65..32e476d 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -101,7 +101,9 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "pll0", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { - .reg = CGU_REG_CPPCR0, + .pll_reg = CGU_REG_CPPCR0, + .bypass_reg = CGU_REG_CPPCR0, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -123,7 +125,9 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "pll1", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { - .reg = CGU_REG_CPPCR1, + .pll_reg = CGU_REG_CPPCR1, + .bypass_reg = CGU_REG_CPPCR1, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index ea905ff..d07fff1 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -220,7 +220,9 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { /* PLLs */ #define DEF_PLL(name) { \ - .reg = CGU_REG_ ## name, \ + .pll_reg = CGU_REG_ ## name, \ + .bypass_reg = CGU_REG_ ## name, \ + .rate_multiplier = 1, \ .m_shift = 19, \ .m_bits = 13, \ .m_offset = 1, \ diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b22d87b..d6fe28f 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -57,7 +57,9 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { "apll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { - .reg = CGU_REG_APLL, + .pll_reg = CGU_REG_APLL, + .bypass_reg = CGU_REG_APLL, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -78,7 +80,9 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { "mpll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { - .reg = CGU_REG_MPLL, + .pll_reg = CGU_REG_MPLL, + .bypass_reg = CGU_REG_MPLL, + .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, From patchwork Fri Feb 14 17:27:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F629C3B1A1 for ; Fri, 14 Feb 2020 17:28:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E79D24650 for ; Fri, 14 Feb 2020 17:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391181AbgBNR2a (ORCPT ); Fri, 14 Feb 2020 12:28:30 -0500 Received: from out28-2.mail.aliyun.com ([115.124.28.2]:38684 "EHLO out28-2.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391169AbgBNR22 (ORCPT ); Fri, 14 Feb 2020 12:28:28 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.4007039|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.0399408-0.00629691-0.953762; DS=CONTINUE|ham_regular_dialog|0.00571966-0.000426352-0.993854; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16367; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Go9djQb_1581701284; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Go9djQb_1581701284) by smtp.aliyun-inc.com(10.147.41.231); Sat, 15 Feb 2020 01:28:19 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v5 3/6] dt-bindings: clock: Add X1830 bindings. Date: Sat, 15 Feb 2020 01:27:39 +0800 Message-Id: <1581701262-110556-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Rob Herring --- Notes: v1->v2: Change my Signed-off-by from "Zhou Yanjie " to "周琰杰 (Zhou Yanjie) " because the old mailbox is in an unstable state. v2->v3: Adjust order from [3/5] in v2 to [4/5] in v3. v3->v4: Adjust order from [4/5] in v3 to [3/4] in v4. v4->v5: Rebase on top of kernel 5.6-rc1. .../devicetree/bindings/clock/ingenic,cgu.txt | 1 + include/dt-bindings/clock/x1830-cgu.h | 47 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/x1830-cgu.h diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt index 75598e6..74bfc57 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -12,6 +12,7 @@ Required properties: * ingenic,jz4770-cgu * ingenic,jz4780-cgu * ingenic,x1000-cgu + * ingenic,x1830-cgu - reg : The address & length of the CGU registers. - clocks : List of phandle & clock specifiers for clocks external to the CGU. Two such external clocks should be specified - first the external crystal diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h new file mode 100644 index 00000000..ca5ccfe --- /dev/null +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_SCLKA 6 +#define X1830_CLK_CPUMUX 7 +#define X1830_CLK_CPU 8 +#define X1830_CLK_L2CACHE 9 +#define X1830_CLK_AHB0 10 +#define X1830_CLK_AHB2PMUX 11 +#define X1830_CLK_AHB2 12 +#define X1830_CLK_PCLK 13 +#define X1830_CLK_DDR 14 +#define X1830_CLK_MAC 15 +#define X1830_CLK_MSCMUX 16 +#define X1830_CLK_MSC0 17 +#define X1830_CLK_MSC1 18 +#define X1830_CLK_SSIPLL 19 +#define X1830_CLK_SSIPLL_DIV2 20 +#define X1830_CLK_SSIMUX 21 +#define X1830_CLK_SSI0 22 +#define X1830_CLK_SMB0 23 +#define X1830_CLK_SMB1 24 +#define X1830_CLK_SMB2 25 +#define X1830_CLK_UART0 26 +#define X1830_CLK_UART1 27 +#define X1830_CLK_SSI1 28 +#define X1830_CLK_SFC 29 +#define X1830_CLK_PDMA 30 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ From patchwork Fri Feb 14 17:27:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB316C3B1A1 for ; Fri, 14 Feb 2020 17:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B280124650 for ; Fri, 14 Feb 2020 17:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390988AbgBNR3E (ORCPT ); Fri, 14 Feb 2020 12:29:04 -0500 Received: from out28-3.mail.aliyun.com ([115.124.28.3]:54045 "EHLO out28-3.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404361AbgBNR3D (ORCPT ); Fri, 14 Feb 2020 12:29:03 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.28405|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.0386694-0.00507426-0.956256; DS=CONTINUE|ham_regular_dialog|0.0101767-0.000332658-0.989491; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03293; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Go9djQb_1581701284; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Go9djQb_1581701284) by smtp.aliyun-inc.com(10.147.41.231); Sat, 15 Feb 2020 01:28:21 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v5 5/6] dt-bindings: clock: Add and reorder ABI for X1000. Date: Sat, 15 Feb 2020 01:27:41 +0800 Message-Id: <1581701262-110556-7-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1581701262-110556-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SSI clock of X1000 not like JZ4770 and JZ4780, they are not directly derived from the output of SSIPLL, but from the clock obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2" is added for this purpose, it must between "X1000_CLK_SSIPLL" and "X1000_CLK_SSIMUX", otherwise an error will occurs when initializing the clock. These ABIs are only used for X1000, and I'm sure that no other devicetree out there is using these ABIs, so we should be able to reorder them. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. include/dt-bindings/clock/x1000-cgu.h | 58 ++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index bbaebaf..5d6eec5 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -12,33 +12,35 @@ #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_SCLKA 4 -#define X1000_CLK_CPUMUX 5 -#define X1000_CLK_CPU 6 -#define X1000_CLK_L2CACHE 7 -#define X1000_CLK_AHB0 8 -#define X1000_CLK_AHB2PMUX 9 -#define X1000_CLK_AHB2 10 -#define X1000_CLK_PCLK 11 -#define X1000_CLK_DDR 12 -#define X1000_CLK_MAC 13 -#define X1000_CLK_MSCMUX 14 -#define X1000_CLK_MSC0 15 -#define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_SCLKA 4 +#define X1000_CLK_CPUMUX 5 +#define X1000_CLK_CPU 6 +#define X1000_CLK_L2CACHE 7 +#define X1000_CLK_AHB0 8 +#define X1000_CLK_AHB2PMUX 9 +#define X1000_CLK_AHB2 10 +#define X1000_CLK_PCLK 11 +#define X1000_CLK_DDR 12 +#define X1000_CLK_MAC 13 +#define X1000_CLK_MSCMUX 14 +#define X1000_CLK_MSC0 15 +#define X1000_CLK_MSC1 16 +#define X1000_CLK_OTG 17 +#define X1000_CLK_SSIPLL 18 +#define X1000_CLK_SSIPLL_DIV2 19 +#define X1000_CLK_SSIMUX 20 +#define X1000_CLK_SFC 21 +#define X1000_CLK_I2C0 22 +#define X1000_CLK_I2C1 23 +#define X1000_CLK_I2C2 24 +#define X1000_CLK_UART0 25 +#define X1000_CLK_UART1 26 +#define X1000_CLK_UART2 27 +#define X1000_CLK_SSI 28 +#define X1000_CLK_PDMA 29 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */