From patchwork Fri Feb 28 04:36:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 204082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23DBBC3F2D0 for ; Fri, 28 Feb 2020 04:38:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F12572469D for ; Fri, 28 Feb 2020 04:38:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hgFIB8G5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730823AbgB1Eii (ORCPT ); Thu, 27 Feb 2020 23:38:38 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:34199 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730802AbgB1Eii (ORCPT ); Thu, 27 Feb 2020 23:38:38 -0500 Received: by mail-pf1-f193.google.com with SMTP id i6so1058970pfc.1; Thu, 27 Feb 2020 20:38:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QCI1h6XDepXvM9SY2yPFBOaTm7J4GLR1VLmmf1BO1BQ=; b=hgFIB8G5XahI8txUYsDG5MShh+0AatjMli8EcASbn9w8027Uc/WNZUIeppsDE5nxwu 8k1V9RFPmVegaSjuOx5NqPNXyhYFevqXge3mJywpLSUkweXuhEEPympdpxPUfv4+hb7M yVr3nweqvyatKHlLAGD5cGjE6180bkWLkRKuZ8d+BlAN7LXt6IsJ7ZOMRZy65LpEx7Ui S718KkrhH+sJwpIEeL74ndAs5kA5oN9ZUNx2dNeEdTEWXtc6ryrHznrwd0AtPIkTM4Sl YduGSO7MjAqAtPPPGBwrs4jG57l+x4oS+9uKRGtDuTu/gKF8UiMV8AVR31WyIdX3Axb3 SM8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QCI1h6XDepXvM9SY2yPFBOaTm7J4GLR1VLmmf1BO1BQ=; b=t6kDudtEznsH/lHYdAMKvyMVbufceRCvjSuUc30uZYiNotNyNS8TCOZJCDrFMMEsoQ y5UVIFZDgxY6nRgJhf1xSc4/SkgmBI9zBSfQuBcGDTPACdy0uqJz7Jt/cPkGgcTurabx XN9ILPJzAOUzF+2rpRdAhbL5XAMxzLzrFHtqXwD3qo/KjT77LMXKjLyeaoNks5gDFDgT 3+zawyxJNgHGUiG5CrimXglAFiMVaCenDf3YOmCoynWWHjJsLJ++ECZzPhDpESXG6Bdp dctgeTpBYRCX92OHu9lMWNKaBN74R1/d1XUXNNOX2nJ9JYpGjBMKcuB0IjCrk/mPGQMI mCbg== X-Gm-Message-State: APjAAAXm04d+VJL8D8HArsagtNs68N3OGHnmvzmUi1AUymljJLyrA4Yk mraEaxlYpqesh+M2C8CD4oY= X-Google-Smtp-Source: APXvYqyZ42VI70e6J50zsTaVBDtxBfufPRxVENg+DF+2e5lxd6dM8CgG2DAIqrDLFaRgxCHGRfp6tQ== X-Received: by 2002:a62:7681:: with SMTP id r123mr2516296pfc.169.1582864715674; Thu, 27 Feb 2020 20:38:35 -0800 (PST) Received: from localhost.localdomain ([240e:379:962:6595:7b84:9990:1a82:371c]) by smtp.gmail.com with ESMTPSA id 196sm9069047pfy.86.2020.02.27.20.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2020 20:38:35 -0800 (PST) From: Chuanhong Guo To: linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org Cc: Chuanhong Guo , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Matthias Brugger , Mark Brown , Tudor Ambarus , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/4] spi: make spi-max-frequency optional Date: Fri, 28 Feb 2020 12:36:33 +0800 Message-Id: <20200228043636.559915-2-gch981213@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200228043636.559915-1-gch981213@gmail.com> References: <20200228043636.559915-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We only need a spi-max-frequency when we specifically request a spi frequency lower than the max speed of spi host. This property is already documented as optional property and current host drivers are implemented to operate at highest speed possible when spi->max_speed_hz is 0. This patch makes spi-max-frequency an optional property so that we could just omit it to use max controller speed. Signed-off-by: Chuanhong Guo --- Change since v1: new commit drivers/spi/spi.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 38b4c78df506..c0c55dc79972 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1955,13 +1955,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, spi->mode |= SPI_CS_HIGH; /* Device speed */ - rc = of_property_read_u32(nc, "spi-max-frequency", &value); - if (rc) { - dev_err(&ctlr->dev, - "%pOF has no valid 'spi-max-frequency' property (%d)\n", nc, rc); - return rc; - } - spi->max_speed_hz = value; + if (!of_property_read_u32(nc, "spi-max-frequency", &value)) + spi->max_speed_hz = value; return 0; } From patchwork Fri Feb 28 04:36:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 204081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64D2AC3F2D1 for ; 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Thu, 27 Feb 2020 20:39:10 -0800 (PST) Received: from localhost.localdomain ([240e:379:962:6595:7b84:9990:1a82:371c]) by smtp.gmail.com with ESMTPSA id 196sm9069047pfy.86.2020.02.27.20.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2020 20:39:10 -0800 (PST) From: Chuanhong Guo To: linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org Cc: Chuanhong Guo , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Matthias Brugger , Mark Brown , Tudor Ambarus , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/4] dt-bindings: convert mtk-quadspi binding doc for spi-mtk-nor Date: Fri, 28 Feb 2020 12:36:35 +0800 Message-Id: <20200228043636.559915-4-gch981213@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200228043636.559915-1-gch981213@gmail.com> References: <20200228043636.559915-1-gch981213@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org spi-mtk-nor is a driver to replace mtk-quadspi and they have almost the same device-tree bindings. Reuse this binding documentation and convert it for new driver: 1. "Mediatek SoCs" -> "Mediatek ARM SoCs" because MTK MIPS SoCs use different controllers. 2. document "interrupts" as a required property because it's available on all SoCs with this controller and new driver takes advantages of it. It's implemented as optional only to maintain backward compatibility. 3. replace binding example with a mt7629 one because this is the only one I know the interrupt assignment. Signed-off-by: Chuanhong Guo --- Change since v1: none .../mtk-quadspi.txt => spi/spi-mtk-nor.txt} | 34 ++++++++----------- 1 file changed, 15 insertions(+), 19 deletions(-) rename Documentation/devicetree/bindings/{mtd/mtk-quadspi.txt => spi/spi-mtk-nor.txt} (62%) diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/spi/spi-mtk-nor.txt similarity index 62% rename from Documentation/devicetree/bindings/mtd/mtk-quadspi.txt rename to Documentation/devicetree/bindings/spi/spi-mtk-nor.txt index a12e3b5c495d..829da480b9a9 100644 --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-mtk-nor.txt @@ -1,4 +1,4 @@ -* Serial NOR flash controller for MediaTek SoCs +* SPI NOR flash controller for MediaTek ARM SoCs Required properties: - compatible: For mt8173, compatible should be "mediatek,mt8173-nor", @@ -13,6 +13,7 @@ Required properties: "mediatek,mt7629-nor", "mediatek,mt8173-nor" "mediatek,mt8173-nor" - reg: physical base address and length of the controller's register +- interrupts: Interrupt number used by the controller. - clocks: the phandle of the clocks needed by the nor controller - clock-names: the names of the clocks the clocks should be named "spi" and "sf". "spi" is used for spi bus, @@ -22,29 +23,24 @@ Required properties: - #address-cells: should be <1> - #size-cells: should be <0> -The SPI flash must be a child of the nor_flash node and must have a -compatible property. Also see jedec,spi-nor.txt. - -Required properties: -- compatible: May include a device-specific string consisting of the manufacturer - and name of the chip. Must also include "jedec,spi-nor" for any - SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). -- reg : Chip-Select number +There should be only one spi slave device following generic spi bindings. +It's not recommended to use this controller for devices other than SPI NOR +flash due to limited transfer capability of this controller. Example: +#include +#include +#include -nor_flash: spi@1100d000 { - compatible = "mediatek,mt8173-nor"; - reg = <0 0x1100d000 0 0xe0>; - clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; +spi_nor: spi@11014000 { + compatible = "mediatek,mt7629-nor", + "mediatek,mt8173-nor"; + reg = <0x11014000 0xe0>; + interrupts = ; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; clock-names = "spi", "sf"; #address-cells = <1>; #size-cells = <0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; };