From patchwork Fri Mar 6 21:09:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 203699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB1BC10DCE for ; Fri, 6 Mar 2020 21:10:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F226B20709 for ; Fri, 6 Mar 2020 21:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726314AbgCFVKN (ORCPT ); Fri, 6 Mar 2020 16:10:13 -0500 Received: from gloria.sntech.de ([185.11.138.130]:36136 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726300AbgCFVKN (ORCPT ); Fri, 6 Mar 2020 16:10:13 -0500 Received: from ip5f5a5d2f.dynamic.kabel-deutschland.de ([95.90.93.47] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1jAKES-0003F8-ML; Fri, 06 Mar 2020 22:10:08 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, mark.rutland@arm.com, christoph.muellner@theobroma-systems.com, robin.murphy@arm.com, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, kever.yang@rock-chips.com, Heiko Stuebner Subject: [PATCH 1/3] arm64: dts: rockchip: add core devicetree for rk3326 Date: Fri, 6 Mar 2020 22:09:20 +0100 Message-Id: <20200306210922.172346-1-heiko@sntech.de> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Heiko Stuebner The rk3326 is basically a px30 without the second display controller. So add a dtsi based on that, that just removes the affected nodes. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3326.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3326.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3326.dtsi b/arch/arm64/boot/dts/rockchip/rk3326.dtsi new file mode 100644 index 000000000000..2ba6da125137 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "px30.dtsi" + +&display_subsystem { + ports = <&vopb_out>; +}; + +/delete-node/ &dsi_in_vopl; +/delete-node/ &lvds_vopl_in; +/delete-node/ &vopl; +/delete-node/ &vopl_mmu; From patchwork Fri Mar 6 21:09:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 203698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A93D4C10F00 for ; Fri, 6 Mar 2020 21:10:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7514E2070E for ; Fri, 6 Mar 2020 21:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726178AbgCFVKP (ORCPT ); Fri, 6 Mar 2020 16:10:15 -0500 Received: from gloria.sntech.de ([185.11.138.130]:36128 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726185AbgCFVKO (ORCPT ); Fri, 6 Mar 2020 16:10:14 -0500 Received: from ip5f5a5d2f.dynamic.kabel-deutschland.de ([95.90.93.47] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1jAKET-0003F8-Cz; Fri, 06 Mar 2020 22:10:09 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, mark.rutland@arm.com, christoph.muellner@theobroma-systems.com, robin.murphy@arm.com, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, kever.yang@rock-chips.com, Heiko Stuebner Subject: [PATCH 3/3] arm64: dts: rockchip: add Odroid Advance Go Date: Fri, 6 Mar 2020 22:09:22 +0100 Message-Id: <20200306210922.172346-3-heiko@sntech.de> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200306210922.172346-1-heiko@sntech.de> References: <20200306210922.172346-1-heiko@sntech.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Heiko Stuebner The Odroid Advance Go is a handheld based on Rockchip's rk3326 soc with a DSI display and some handheld controls including an analog joystick connected to the saradc. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 544 ++++++++++++++++++ 2 files changed, 545 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index af1e1c3707d0..86c38467d487 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-copperhead-ltk101b4029w.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts new file mode 100644 index 000000000000..a16f4a0d1d4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -0,0 +1,544 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include +#include +#include "rk3326.dtsi" + +/ { + model = "ODROID-GO Advance"; + compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&btn_pins>; + + /* + * *** ODROIDGO2-Advance Switch layoout *** + * |------------------------------------------------| + * | sw15 sw16 | + * |------------------------------------------------| + * | sw1 |-------------------| sw8 | + * | sw3 sw4 | | sw7 sw5 | + * | sw2 | LCD Display | sw6 | + * | | | | + * | |-------------------| | + * | sw9 sw10 sw11 sw12 sw13 sw14 | + * |------------------------------------------------| + */ + + sw1 { + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + sw2 { + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + sw3 { + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + sw4 { + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + sw5 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + label = "BTN-A"; + linux,code = ; + }; + sw6 { + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + label = "BTN-B"; + linux,code = ; + }; + sw7 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + label = "BTN-Y"; + linux,code = ; + }; + sw8 { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + label = "BTN-X"; + linux,code = ; + }; + sw9 { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "F1"; + linux,code = ; + }; + sw10 { + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + label = "F2"; + linux,code = ; + }; + sw11 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + label = "F3"; + linux,code = ; + }; + sw12 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + label = "F4"; + linux,code = ; + }; + sw13 { + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; + label = "F5"; + linux,code = ; + }; + sw14 { + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; + label = "F6"; + linux,code = ; + }; + sw15 { + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT"; + linux,code = ; + }; + sw16 { + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT"; + linux,code = ; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "led_pins"; + pinctrl-0 = <&led_pins>; + + /* Blue LED : GPIO0_C1 */ + heartbeat { + label = "blue:heartbeat"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_bl>; + pwms = <&pwm1 0 25000 0>; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc_host { + compatible = "regulator-fixed"; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <&vccsys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, + <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>, + <17000000>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "elida,kd35t133"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_lcd>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "xin32k"; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; +}; + +/* EXT Header(P2) : 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +/* I2S 1 Channel Used */ +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + card-detect-delay = <800>; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "disabled"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dc_det: dc-det { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +};