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[209.132.180.67]) by mx.google.com with ESMTP id h69si5160309pge.830.2017.08.21.09.03.15; Mon, 21 Aug 2017 09:03:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ZFvXanSs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754447AbdHUQDL (ORCPT + 26 others); Mon, 21 Aug 2017 12:03:11 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:38198 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932142AbdHUQDI (ORCPT ); Mon, 21 Aug 2017 12:03:08 -0400 Received: by mail-wr0-f178.google.com with SMTP id p8so39037527wrf.5 for ; Mon, 21 Aug 2017 09:03:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u7hTrQdYqj7AkUYcAATDscw4tsL/7QGtInLnc70kmWY=; b=ZFvXanSsVd57klfvFQRXRGcH1h8uo7z0y0LaCfWtUJH+k4ep2GWEcDwyRQ3cilypY9 ysq0KvgNKP0P1G192sqNURK/naoJHM2DnbBaQsVhk/mIfvKA+DrO/rCS1nw6j9qAtRqC kpfaWs4fa/RqGplbLAapp7AZOREtOgpd6AM5dlSaWHoBxuhZ7KEW5kqEJ/xIgU34LpWI UfDWESmZphFHPdK4iU7RRv2i92Dyh8i5MHwtB6qu61tYxdOdLpcGRtqJUrEdSZq0N2AT Lyt1qvrMW+DvTPh2jbhIMnH3S21m6CBsOKESU/NZurd7tZmZCPJ/ACNbVgo+XmnZlLWP FsPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u7hTrQdYqj7AkUYcAATDscw4tsL/7QGtInLnc70kmWY=; b=umxcOLS0iqkcW6O1TW0N1jvZMc9TQrCqr3Z9AXD3XA0FWOAz8nB/vGmIBPAiy5cILg eIbNGFBE5A6IlXsxbaCnfq6wDxlmqns8XpMwofQL03XBbdCNEMIFhK3eHr/ujspIMhiI gvGChbdMDvhPJpOxVPPRvBiY+4NqQaS9X+KFPslUpS4INeErGc7wIa6BcL0iJnq28yRi WfCT/5RoS6MJA3WL5ahcndLcHJh2HTN+aVA6MkYxVSMY5CBaLzcmKJxS+YJgs/lntU6Y g4VwrxxdFFWtk2baRlyj5DwP9l6/RPu9kjIFvzTg+DDkhSH1M4SNF5bijAmVukfg7Avt orzQ== X-Gm-Message-State: AHYfb5iOkyktT0vkTkK31hy23c0gU3RRzp4SIi8xGedaxiafa+XSc2KR yP5M6WUIRKE6faj1 X-Received: by 10.223.171.209 with SMTP id s75mr2406646wrc.277.1503331387293; Mon, 21 Aug 2017 09:03:07 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:06 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/16] mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag Date: Mon, 21 Aug 2017 18:02:47 +0200 Message-Id: <20170821160301.21899-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 4217287923d4..d480a8052a06 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -389,7 +389,7 @@ static int meson_mmc_clk_init(struct meson_host *host) host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK); host->cfg_div.hw.init = &init; host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO; + CLK_DIVIDER_ROUND_CLOSEST; host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) From patchwork Mon Aug 21 16:02:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110587 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1494816qge; Mon, 21 Aug 2017 09:10:38 -0700 (PDT) X-Received: by 10.84.132.35 with SMTP id 32mr5111483ple.424.1503331838575; Mon, 21 Aug 2017 09:10:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331838; cv=none; d=google.com; s=arc-20160816; b=LlsfnYTW8NMnBnqK0LSz5jXWR6hJMN8Tyv1g2dpSD69CW5g/p/n/PR2w4+c3CO5QFw hZ54TAv7/onCuGBpMc4JVAD4ZbM5hgAbVlWJnAljtlSRrASWQeiLIDnfMmehwqr0rj25 b21A8VPAiiWXp91k8l5ZpOAxmaF1D/8YbkVMbvY+NqAGc5c3dW+ewf6g0Hfu0bac86v7 4jDO4ei8mdb1svSiELzEzF0dQBDoDnxrpng8wLCcMioTwmsVPqYxrSl/9sBHKNqNNmsl yNa9r77Jfi/LVFaX/GMegDgHimWYh9nOq9oHVkSoG+vABj+xg2gcv3KLYCcZGYYTBHCU uInA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=v2tkjLCmvtPUcXAXid7lD2gkivw1BrIsDeU4rrNjMuU=; b=ZMuCz6MqziR9hwwQ0BthPh0C9yGUQJZui1Sv0b2fWpsuprz0Ao0vF7qTKKkZBeQTsX 6GeJcT74bl3zINJPHJc0j5T4y+FxCuyeryIxhow9jb/5wQrUkfP8OuM7FAC6fLcFKaNu lA/gRn9Iw2/SrkpSseiTq3C1xrAeuVIqXuDCnQaRzf4VAC8vIAOu6+KEB6YxWtpHC+iY RuzsOJAolObE4bJKycesg4rE1JahA2Glj0cooxjSf1pOtWGbRoZojXUVjcUYWqPimpJa TSGAH0Ocqbc0fAatGDsMnC5mhuB9DErTW7UyFkCE05/tI85k3aeUohHdK29hyOG+eGMT 0gng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=pcoCdDys; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index d480a8052a06..8a74a048db88 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -45,9 +45,7 @@ #define CLK_DIV_MAX 63 #define CLK_SRC_MASK GENMASK(7, 6) #define CLK_SRC_XTAL 0 /* external crystal */ -#define CLK_SRC_XTAL_RATE 24000000 #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ -#define CLK_SRC_PLL_RATE 1000000000 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) @@ -57,7 +55,7 @@ #define CLK_PHASE_270 3 #define CLK_ALWAYS_ON BIT(24) -#define SD_EMMC_DElAY 0x4 +#define SD_EMMC_DELAY 0x4 #define SD_EMMC_ADJUST 0x8 #define SD_EMMC_CALOUT 0x10 #define SD_EMMC_START 0x40 From patchwork Mon Aug 21 16:02:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110571 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4245929obb; Mon, 21 Aug 2017 09:05:49 -0700 (PDT) X-Received: by 10.98.9.85 with SMTP id e82mr10643073pfd.257.1503331548984; Mon, 21 Aug 2017 09:05:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331548; cv=none; d=google.com; s=arc-20160816; b=EL0/hg3YFWzOaeZ+12SR01N6X7s/UmM3IatZ7xcUF/yTP3tWlm9su0NQv8hTRJztz5 jOBl+Aml86JsRsut5OMCgbIS3HpciIHErLINwMG2PItpatcLMwpZVxLbDDa/8ppR1sj6 iwc6uGUY688VKmE+37ouJE3C78MTPTr4t3XTlrKU8HWMGOO8NWC7h01V8D8Abve3BkIr vvIimPZNeCbfN7f8FutcjQWOGXhYVDqIVuqS8wKLryhcnqpXSDCymqFPvqsHqY8vP2Zz nAiESJ1nhjUQ8ePeISG4/L/iqX5x9QJhvAc8kLwxbCxPPdMaXNvTrPzl9svo8aEOetXH HxnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NQHDIP/kjjw/xPSDqnPE1P980K9m+9M7XcbxiKQH12U=; b=Hq6SSPocxZnfaQ0t0+ZGqFDDhAQLMgReoptLHVIMF2nwELd3wzPRvceeZKRFdzg27O ggpFMGjQVZXqtrcrKvjaUvm+dts22zYvU82Fe5FsNr3oiQE0kH7XD782RhhUFKEj4/2g ucrP9bRiDJili6Rjf58dvZEXAVdgNov/NKcO2sVekzqsRa/efhX2uKZku3G7HVqvUZUO WtQitOrPH1iDHBTTCIvoZrfUgToAMR/9ODgTOIgK3xVKJpsr0DoA1vvhB8zb6QaMHthy Z9zb7c346CwAOeXdSQrstc9xJwyOz5vqORFo7gKkgH4K33mazaKT8A09sH8zAr70Jv94 3b5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=gWqAYPf6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a28si1748018pgd.518.2017.08.21.09.05.48; Mon, 21 Aug 2017 09:05:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=gWqAYPf6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932224AbdHUQDQ (ORCPT + 26 others); Mon, 21 Aug 2017 12:03:16 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:36639 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754448AbdHUQDM (ORCPT ); Mon, 21 Aug 2017 12:03:12 -0400 Received: by mail-wr0-f171.google.com with SMTP id f8so66998598wrf.3 for ; Mon, 21 Aug 2017 09:03:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NQHDIP/kjjw/xPSDqnPE1P980K9m+9M7XcbxiKQH12U=; b=gWqAYPf6hfEZTt9CjgWaxtNgJ2hgeAO5xY+80BS/bZO43ibWzTnw2smm0emXMTDUps nEtFmnXEU+aKvNTh/2HgCF141VJaWa7V0xCxe4ch4liHTUHkWFY7TG1OsiTU1YBsBvBo aInRDL0R6wbk3WddoUIGnEeDbFjgIBSNG/Ic1HJHa0kgNmGDDvguXah5fqthsSFH+bcm 9fX/QFr1OTGx2yCxIEnPUzK4jk6+XwEGBzICITn8XLK/qPFgk3XvaT6P8zePQdVAcyfI +/3B7a4R80iVEh9mXWe4MDrOUi9wQqvtvPv7wQzRPQ7c9miJbJg79ZjLb+xATb3T65/A 3hBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NQHDIP/kjjw/xPSDqnPE1P980K9m+9M7XcbxiKQH12U=; b=Q8lJY2JM7Vr8Lkj4cJgYjaA4/uCuIWf/4yb13ihpktHXEsgIUl1OO/NSOwOtqeiA7t P8L0xkt6KsX68t+yqoi+ZIMrz8+hERNM3n/s6UuiDO6YTFJBVNvHcfv2LUQltMSDx0b5 P4WjclJlwb/7kUvva2JyVVYz7qVGB4FqaHZLGTXKEKXRDlGPagNIb4Lo3tqmyDsKPN/N /sFCEmavFkmzlab00AebsN4gxyaom4VyRlf9qVVPRw0laxoLAGVoYZ/Aem4DEd/5K8ID eCQ5USR3bz+scMU6aEY0vofTKn6ex4Y2NA4iBssszLqdwON+e6dvpWhrmHAH/45U8rUi UbyQ== X-Gm-Message-State: AHYfb5gwiYCeppmNrvPUcYriMAPU52oKydiXC03rhCUB8M+kwEAXcMiE rYbaBRxGyNAhzK3S X-Received: by 10.223.179.11 with SMTP id j11mr1039813wrd.235.1503331391056; Mon, 21 Aug 2017 09:03:11 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:10 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/16] mmc: meson-gx: cfg init overwrite values Date: Mon, 21 Aug 2017 18:02:50 +0200 Message-Id: <20170821160301.21899-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org cfg init function overwrite values set in the clk init function Remove the cfg pokes from the clk init. Actually, trying to use the CLK_AUTO, like initially tried in clk_init, would break the card initialization BEWARE not to poke the cfg register while the divider value in clk register is 0. It crashes the SoC. Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index a399fbd415f4..61668891b4fc 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -337,7 +337,7 @@ static int meson_mmc_clk_init(struct meson_host *host) int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; const char *clk_div_parents[1]; - u32 clk_reg, cfg; + u32 clk_reg; /* get the mux parents */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { @@ -403,12 +403,6 @@ static int meson_mmc_clk_init(struct meson_host *host) clk_reg &= ~CLK_ALWAYS_ON; writel(clk_reg, host->regs + SD_EMMC_CLOCK); - /* Ensure clock starts in "auto" mode, not "always on" */ - cfg = readl(host->regs + SD_EMMC_CFG); - cfg &= ~CFG_CLK_ALWAYS_ON; - cfg |= CFG_AUTO_CLK; - writel(cfg, host->regs + SD_EMMC_CFG); - ret = clk_prepare_enable(host->cfg_div_clk); if (ret) return ret; @@ -958,6 +952,9 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto err_core_clk; + /* set config to sane default */ + meson_mmc_cfg_init(host); + /* Stop execution */ writel(0, host->regs + SD_EMMC_START); @@ -966,9 +963,6 @@ static int meson_mmc_probe(struct platform_device *pdev) writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS); writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN); - /* set config to sane default */ - meson_mmc_cfg_init(host); - ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq, meson_mmc_irq_thread, IRQF_SHARED, NULL, host); From patchwork Mon Aug 21 16:02:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110585 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1493919qge; Mon, 21 Aug 2017 09:10:00 -0700 (PDT) X-Received: by 10.84.224.136 with SMTP id s8mr19394509plj.429.1503331800136; Mon, 21 Aug 2017 09:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331800; cv=none; d=google.com; s=arc-20160816; b=aYT2ze/OjyxKoQaiAMzKqTXa0Hv5Kg8oOqHebZtz9IC/tW4ARbvlfgFt+A24qsTtr0 9FrRq99XYe8NkjtZod3wpzeUugp8Tm0Zh9qFrHZ83lB1afgS/jEJx+0PkFmbenn2t2wQ GwPrY20dQmrNNhGHUAx3AbsJJOaEKhfX/CMfH7oNXcF85MehO0ezpzZkYLn1SYr4JtO9 hpwjGAbURTwM6FnpGDiqGeB3I96BH0gUXRzMKUdfCMUyb23hQvBJyQDPtho8y+QQC9EQ sj9bvGE1yRWt+FtkOGVQ52tLOcrFkXTD783157WT8m35w7v6EEhFfvbWBKAY0PXYi0cV aEiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rXd6q7OYpdZBu63ve9On+4T4IM8h14fRvuBmXWIXVUI=; b=dSfWIOMvB1XA9hQYblcq/7ZRyar2jv+AJPOCLYexjOmOCHIxc13uGLDnLj/HD1X09K rXTO0NzE3PdZERB65AyEwdNjYHa9JBoESW4fA0JEqpZocbtfxwXzN4SJHLy6Xxpogxiw DssgR9DRas5//nVIcpTaPZrNChBEhYFc5i34PiXSYsCRxWKTOfIoGknyAgUql6KHjNOu AXCUJi+I8xXsmzTNvcc42rIng9Kzpije/C/oPjjrz5/UNX2mwJY5fq5zx4tQY9YsNs0b NO73nkEPU3rE25rC5XxT6eSKzQsj2pDRjNdlMIJhrBj4liWU1jwDO7R0saH/yDOtdjlv IpuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=AFE7Nvx/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 62si7022226plf.66.2017.08.21.09.09.59; Mon, 21 Aug 2017 09:10:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=AFE7Nvx/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932169AbdHUQJz (ORCPT + 26 others); Mon, 21 Aug 2017 12:09:55 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:35703 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754452AbdHUQDN (ORCPT ); Mon, 21 Aug 2017 12:03:13 -0400 Received: by mail-wr0-f175.google.com with SMTP id k46so28389025wre.2 for ; Mon, 21 Aug 2017 09:03:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rXd6q7OYpdZBu63ve9On+4T4IM8h14fRvuBmXWIXVUI=; b=AFE7Nvx/7WiFpRD571CiqUnZsKCmYwBa84kVYnnozV9cuHhOi2K5dRGV3fN/2jbAG9 ZtIqTLgbGAKUNeExd4kPk4jScsFAjNht1LusfHEcmBkSt2o3zeFR9MwcZmyiXL4HBl0y unYecosYPYRFfhTn/2ZemSspaUfuFzjuGveus2xWFcJ4p+kvD1umexsbCWnmti81UGVh 1cjqK/XyPEVEsuuJgSu/0/Mq/YVEY588HZkTCWCUNlS8+dMnbKC9JLHNHTVxoW+aoOeS 7V1QDMEw5oPgpFWPEZFrcxnhX0U0P9NjvmiW9Z8vgPSy3LJq96HkBrhHW1WNl31bB3YE Tdzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rXd6q7OYpdZBu63ve9On+4T4IM8h14fRvuBmXWIXVUI=; b=ukFMVThpABzAtmC8S0QYDiDNX72gznrIwx5bQC6TrFpqq0zFuVXdH8+Jk9Ewnz6w1a H4njsBWmhk0Hbzub58B28f/wedy2vqTBQPTT1cRZpmWCfdteBkbiXWC9hRscY/oHMrYr XwG62LtmX25YcICHWfTl7aebAXM4TashmCyzKfBVj/qsTXSgmPc8Ohl5PESHKt93jw8h RVYX1i0Vv/gOgHDbXUF3Q73Hgl2baVsLsW2Eqr4GgZbbwtNdkAli7WvAYqcbdxXtUrMU pFllYYV4tcNnBjau1zrwGTbxyO2IKiLWYXOR4/GrVvjzpjyWhTC0RWjRhg++J5Mf7mzX lpfQ== X-Gm-Message-State: AHYfb5g35ngiZ07rkO0QZpG5oV6ygg/IURv9AlF4R8MF+bXMxz1iX1w2 KfECcNgBytsPMBOW X-Received: by 10.223.134.189 with SMTP id 58mr2660414wrx.157.1503331392222; Mon, 21 Aug 2017 09:03:12 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:11 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/16] mmc: meson-gx: rework set_ios function Date: Mon, 21 Aug 2017 18:02:51 +0200 Message-Id: <20170821160301.21899-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove conditional write of cfg register. Warn if set_clk fails for some reason. Consistently use host->dev instead of mixing with mmc_dev(mmc) Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 61668891b4fc..18fff28025d8 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -445,8 +445,8 @@ static void meson_mmc_set_tuning_params(struct mmc_host *mmc) static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); - u32 bus_width; - u32 val, orig; + u32 bus_width, val; + int err; /* * GPIO regulator, only controls switching between 1v8 and @@ -474,7 +474,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) int ret = regulator_enable(mmc->supply.vqmmc); if (ret < 0) - dev_err(mmc_dev(mmc), + dev_err(host->dev, "failed to enable vqmmc regulator\n"); else host->vqmmc_enabled = true; @@ -483,9 +483,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } - - meson_mmc_clk_set(host, ios->clock); - /* Bus width */ switch (ios->bus_width) { case MMC_BUS_WIDTH_1: @@ -504,8 +501,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } val = readl(host->regs + SD_EMMC_CFG); - orig = val; - val &= ~CFG_BUS_WIDTH_MASK; val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); @@ -519,11 +514,12 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (ios->timing == MMC_TIMING_MMC_HS400) val |= CFG_CHK_DS; - if (val != orig) { - writel(val, host->regs + SD_EMMC_CFG); - dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n", - __func__, orig, val); - } + err = meson_mmc_clk_set(host, ios->clock); + if (err) + dev_err(host->dev, "Failed to set clock: %d\n,", err); + + writel(val, host->regs + SD_EMMC_CFG); + dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); } static void meson_mmc_request_done(struct mmc_host *mmc, From patchwork Mon Aug 21 16:02:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110563 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4242396obb; Mon, 21 Aug 2017 09:03:20 -0700 (PDT) X-Received: by 10.84.128.195 with SMTP id a61mr19808436pla.222.1503331400642; Mon, 21 Aug 2017 09:03:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331400; cv=none; d=google.com; s=arc-20160816; b=ejMo0wOg/UzPSOsKtyHUmNp3hcI6UrTfji0WyyYAiEus2fQpCbvgiKEJqWp51B9y2L /BEUeMjE1r0Qz1Q90UzWn7bkvqDCwbt7WgAHyTdAtq4MEmEpNx5lD/Okiz1oTfn/TJR2 44CDZz1M/WeNT44yG65br4t4Z/afs2z1Pp3uI/f7W9gGpJPdSF/eXhj5mLpEx37rGG0Z IqDxQHwBWN3Ay3oVUFNWeox/6skeD3EKUCV7hTXz2XL8ExuXhDHf3KQytzYnzYRuBYYF i89AkPTKMcVlLC7kFTAGiqLFPn7wlELQYvZOqzGvTDy2OwAHrPDm1P1RfgktymGLGBpk S5Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=hr+C/T8uNZUC2Q3WmJzHqYHhdk4t7v/kNGCjMEB0QHI=; b=OoyQ8c9vPz39GlBD+Z/eSBek6IMPFC3ukRJJetriT8n7DldEaPPlwQ4gsC1ywJwr9B AQ40iunLKiFZGkFKUhhmQ40ygygpCMWj02o7Jhbm3T1OLfifqYaDygwF8BvVI3s5MxSC PpM+WUV/NfzO4DfXYDmaGxOqC3Ar17GF5ycyHeF4nQ4bVPqFiiYU/P+Ltl78cncOKIDB Xym86cpdjMDhSvRcZ3XidC/wdVRZ/1y5H3Jr0NMzY+Q7W32pAiPGo9lak46s2o7OJohj jEOQ4PdMMt5/AsvSv3KWNgltDZxY4UJXx/ceQA2ydvkXoI6gr7G7Oi734hvypBfr0dU6 QMDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=HmcpJvfZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Mon, 21 Aug 2017 09:03:13 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:12 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/16] mmc: meson-gx: rework clk_set function Date: Mon, 21 Aug 2017 18:02:52 +0200 Message-Id: <20170821160301.21899-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Clean-up clk_set function to prepare the next changes (DDR and clk-stop) Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 30 +++++++++--------------------- 1 file changed, 9 insertions(+), 21 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 18fff28025d8..8f9ba5190c18 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -139,7 +139,7 @@ struct meson_host { struct clk *core_clk; struct clk_mux mux; struct clk *mux_clk; - unsigned long current_clock; + unsigned long req_rate; struct clk_divider cfg_div; struct clk *cfg_div_clk; @@ -275,29 +275,18 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) int ret; u32 cfg; - if (clk_rate) { - if (WARN_ON(clk_rate > mmc->f_max)) - clk_rate = mmc->f_max; - else if (WARN_ON(clk_rate < mmc->f_min)) - clk_rate = mmc->f_min; - } - - if (clk_rate == host->current_clock) + /* Same request - bail-out */ + if (host->req_rate == clk_rate) return 0; /* stop clock */ cfg = readl(host->regs + SD_EMMC_CFG); - if (!(cfg & CFG_STOP_CLOCK)) { - cfg |= CFG_STOP_CLOCK; - writel(cfg, host->regs + SD_EMMC_CFG); - } - - dev_dbg(host->dev, "change clock rate %u -> %lu\n", - mmc->actual_clock, clk_rate); + cfg |= CFG_STOP_CLOCK; + writel(cfg, host->regs + SD_EMMC_CFG); + host->req_rate = 0; if (!clk_rate) { mmc->actual_clock = 0; - host->current_clock = 0; /* return with clock being stopped */ return 0; } @@ -309,13 +298,12 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) return ret; } + host->req_rate = clk_rate; mmc->actual_clock = clk_get_rate(host->cfg_div_clk); - host->current_clock = clk_rate; + dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); if (clk_rate != mmc->actual_clock) - dev_dbg(host->dev, - "divider requested rate %lu != actual rate %u\n", - clk_rate, mmc->actual_clock); + dev_dbg(host->dev, "requested rate was %lu\n", clk_rate); /* (re)start clock */ cfg = readl(host->regs + SD_EMMC_CFG); From patchwork Mon Aug 21 16:02:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110574 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4246999obb; Mon, 21 Aug 2017 09:06:31 -0700 (PDT) X-Received: by 10.99.126.91 with SMTP id o27mr16961955pgn.202.1503331591837; Mon, 21 Aug 2017 09:06:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331591; cv=none; d=google.com; s=arc-20160816; b=WgOATfQxVffW3rMCb+KJPOTxuYru6YODeIEXv7sHSwHL7kxCDtsCH/DNtJMOb+f6SL TZx9MevVhL/jXUXIDk3AjjIxSLM4cnNlTJ96VVaBZbLWh7DEnOlR5XSrSEqFZUsxqLJN wQz3Agf8fmJtC8j/XrsSm9vpBq1Nxn++ilqpotr/J/bJJOd9CucvOE90qM6lZJxtk4d5 iIxldJGMK37QPbzgx6Fy703NchDJKYMtuTRcWpmNQYHXJPbogPTHXmJoCcxdQroQkb+3 +F32bEFfL6Avysg75bXP83Vu/pni6iySV3hiEpRZIfSsgPyNq4IRi4c/aeVCRCu9G+pR KfGw== ARC-Message-Signature: i=1; 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Thanks to devm, carrying the clock structure around after init is not necessary. Rework the function to remove these from the controller host data. Finally, set initial mmc clock rate before enabling it, simplifying the exit condition. Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 107 +++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 55 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8f9ba5190c18..2f45daa5d510 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -42,10 +42,7 @@ #define SD_EMMC_CLOCK 0x0 #define CLK_DIV_MASK GENMASK(5, 0) -#define CLK_DIV_MAX 63 #define CLK_SRC_MASK GENMASK(7, 6) -#define CLK_SRC_XTAL 0 /* external crystal */ -#define CLK_SRC_PLL 1 /* FCLK_DIV2 */ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) @@ -137,13 +134,9 @@ struct meson_host { spinlock_t lock; void __iomem *regs; struct clk *core_clk; - struct clk_mux mux; - struct clk *mux_clk; + struct clk *mmc_clk; unsigned long req_rate; - struct clk_divider cfg_div; - struct clk *cfg_div_clk; - unsigned int bounce_buf_size; void *bounce_buf; dma_addr_t bounce_dma_addr; @@ -291,7 +284,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) return 0; } - ret = clk_set_rate(host->cfg_div_clk, clk_rate); + ret = clk_set_rate(host->mmc_clk, clk_rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", clk_rate, ret); @@ -299,7 +292,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) } host->req_rate = clk_rate; - mmc->actual_clock = clk_get_rate(host->cfg_div_clk); + mmc->actual_clock = clk_get_rate(host->mmc_clk); dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); if (clk_rate != mmc->actual_clock) @@ -321,10 +314,13 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) static int meson_mmc_clk_init(struct meson_host *host) { struct clk_init_data init; + struct clk_mux *mux; + struct clk_divider *div; + struct clk *clk; char clk_name[32]; int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; - const char *clk_div_parents[1]; + const char *clk_parent[1]; u32 clk_reg; /* get the mux parents */ @@ -343,66 +339,67 @@ static int meson_mmc_clk_init(struct meson_host *host) mux_parent_names[i] = __clk_get_name(clk); } + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = 0; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); + clk_reg |= CLK_DIV_MASK; + clk_reg |= CLK_ALWAYS_ON; + writel(clk_reg, host->regs + SD_EMMC_CLOCK); + /* create the mux */ + mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); init.name = clk_name; init.ops = &clk_mux_ops; init.flags = 0; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS; - host->mux.reg = host->regs + SD_EMMC_CLOCK; - host->mux.shift = __bf_shf(CLK_SRC_MASK); - host->mux.mask = CLK_SRC_MASK >> host->mux.shift; - host->mux.flags = 0; - host->mux.table = NULL; - host->mux.hw.init = &init; - host->mux_clk = devm_clk_register(host->dev, &host->mux.hw); - if (WARN_ON(IS_ERR(host->mux_clk))) - return PTR_ERR(host->mux_clk); + mux->reg = host->regs + SD_EMMC_CLOCK; + mux->shift = __bf_shf(CLK_SRC_MASK); + mux->mask = CLK_SRC_MASK >> mux->shift; + mux->hw.init = &init; + + clk = devm_clk_register(host->dev, &mux->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); /* create the divider */ + div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); init.name = clk_name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; - clk_div_parents[0] = __clk_get_name(host->mux_clk); - init.parent_names = clk_div_parents; - init.num_parents = ARRAY_SIZE(clk_div_parents); + clk_parent[0] = __clk_get_name(clk); + init.parent_names = clk_parent; + init.num_parents = 1; - host->cfg_div.reg = host->regs + SD_EMMC_CLOCK; - host->cfg_div.shift = __bf_shf(CLK_DIV_MASK); - host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK); - host->cfg_div.hw.init = &init; - host->cfg_div.flags = CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ROUND_CLOSEST; + div->reg = host->regs + SD_EMMC_CLOCK; + div->shift = __bf_shf(CLK_DIV_MASK); + div->width = __builtin_popcountl(CLK_DIV_MASK); + div->hw.init = &init; + div->flags = (CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ROUND_CLOSEST); - host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) - return PTR_ERR(host->cfg_div_clk); + host->mmc_clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) + return PTR_ERR(host->mmc_clk); /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); - clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); - clk_reg &= ~CLK_ALWAYS_ON; - writel(clk_reg, host->regs + SD_EMMC_CLOCK); - - ret = clk_prepare_enable(host->cfg_div_clk); + host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); + ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) return ret; - /* Get the nearest minimum clock to 400KHz */ - host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000); - - ret = meson_mmc_clk_set(host, host->mmc->f_min); - if (ret) - clk_disable_unprepare(host->cfg_div_clk); - - return ret; + return clk_prepare_enable(host->mmc_clk); } static void meson_mmc_set_tuning_params(struct mmc_host *mmc) @@ -951,7 +948,7 @@ static int meson_mmc_probe(struct platform_device *pdev) meson_mmc_irq_thread, IRQF_SHARED, NULL, host); if (ret) - goto err_div_clk; + goto err_init_clk; mmc->caps |= MMC_CAP_CMD23; mmc->max_blk_count = CMD_CFG_LENGTH_MASK; @@ -967,7 +964,7 @@ static int meson_mmc_probe(struct platform_device *pdev) if (host->bounce_buf == NULL) { dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); ret = -ENOMEM; - goto err_div_clk; + goto err_init_clk; } host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, @@ -986,8 +983,8 @@ static int meson_mmc_probe(struct platform_device *pdev) err_bounce_buf: dma_free_coherent(host->dev, host->bounce_buf_size, host->bounce_buf, host->bounce_dma_addr); -err_div_clk: - clk_disable_unprepare(host->cfg_div_clk); +err_init_clk: + clk_disable_unprepare(host->mmc_clk); err_core_clk: clk_disable_unprepare(host->core_clk); free_host: @@ -1009,7 +1006,7 @@ static int meson_mmc_remove(struct platform_device *pdev) dma_free_coherent(host->dev, host->bounce_buf_size, host->bounce_buf, host->bounce_dma_addr); - clk_disable_unprepare(host->cfg_div_clk); + clk_disable_unprepare(host->mmc_clk); clk_disable_unprepare(host->core_clk); mmc_free_host(host->mmc); From patchwork Mon Aug 21 16:02:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110572 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4245982obb; 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Mon, 21 Aug 2017 09:03:15 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:14 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/16] mmc: meson-gx: fix dual data rate mode frequencies Date: Mon, 21 Aug 2017 18:02:54 +0200 Message-Id: <20170821160301.21899-10-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 2f45daa5d510..0d3416dae8cf 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -262,14 +262,29 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, mmc_get_dma_dir(data)); } -static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) +static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) +{ + if (ios->timing == MMC_TIMING_MMC_DDR52 || + ios->timing == MMC_TIMING_UHS_DDR50 || + ios->timing == MMC_TIMING_MMC_HS400) + return true; + + return false; +} + +static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) { struct mmc_host *mmc = host->mmc; + unsigned long rate = ios->clock; int ret; u32 cfg; + /* DDR modes require higher module clock */ + if (meson_mmc_timing_is_ddr(ios)) + rate <<= 1; + /* Same request - bail-out */ - if (host->req_rate == clk_rate) + if (host->req_rate == rate) return 0; /* stop clock */ @@ -278,25 +293,29 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) writel(cfg, host->regs + SD_EMMC_CFG); host->req_rate = 0; - if (!clk_rate) { + if (!rate) { mmc->actual_clock = 0; /* return with clock being stopped */ return 0; } - ret = clk_set_rate(host->mmc_clk, clk_rate); + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", - clk_rate, ret); + rate, ret); return ret; } - host->req_rate = clk_rate; + host->req_rate = rate; mmc->actual_clock = clk_get_rate(host->mmc_clk); + /* We should report the real output frequency of the controller */ + if (meson_mmc_timing_is_ddr(ios)) + mmc->actual_clock >>= 1; + dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); - if (clk_rate != mmc->actual_clock) - dev_dbg(host->dev, "requested rate was %lu\n", clk_rate); + if (ios->clock != mmc->actual_clock) + dev_dbg(host->dev, "requested rate was %u\n", ios->clock); /* (re)start clock */ cfg = readl(host->regs + SD_EMMC_CFG); @@ -490,16 +509,14 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); val &= ~CFG_DDR; - if (ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_DDR52 || - ios->timing == MMC_TIMING_MMC_HS400) + if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; val &= ~CFG_CHK_DS; if (ios->timing == MMC_TIMING_MMC_HS400) val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios->clock); + err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); From patchwork Mon Aug 21 16:02:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110568 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4244160obb; Mon, 21 Aug 2017 09:04:35 -0700 (PDT) X-Received: by 10.84.193.101 with SMTP id e92mr19594961pld.209.1503331475820; Mon, 21 Aug 2017 09:04:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331475; cv=none; d=google.com; s=arc-20160816; b=oe8ad65RMM5fOtnCzDskN/WdXziF1QCVXCz8I3NtZZ5gMx8Xq0T835TyZw0wZKY/az UYduDUvmTZLSD8q/CrX4shMBs4HkF+Xn/5Ixd6upr92QW2CTQX27SEXkPeOJVTO3FSxF tGmn0FSFBvyYvnjs5er+kelUI6ID9TMISN+g1buK0UXI5tpI5S+Xo2jY/f455+FTYgdw OTogYhrtLtONA79aM/vUB4cDLa0tp/6zXVKwuK1p/sL/WBU0CzSpuiTsP/tazfKm2jDl xkR2UFXaWeMIy2xlqP8amTZoEo28LNBKgsLxJFsZBzEtGiS/XTrg1EjuXW3XLZZ0KSh0 eJlA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id g5si8269652plj.654.2017.08.21.09.04.35; Mon, 21 Aug 2017 09:04:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=QU8YraVZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754542AbdHUQED (ORCPT + 26 others); Mon, 21 Aug 2017 12:04:03 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:32819 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754338AbdHUQDV (ORCPT ); Mon, 21 Aug 2017 12:03:21 -0400 Received: by mail-wr0-f169.google.com with SMTP id 30so30555765wrk.0 for ; Mon, 21 Aug 2017 09:03:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+UIJ4D0C6pJg406mf/36VP+y4bPZApTRahj1mpgvJJc=; b=QU8YraVZI7gz3n/xaNFuz8rf2h1d93RVk/jh+3rZ8x2lPeVdowXVKUfyONDr4Q1hxx J4okpjxtuyAa3AyIT9pt8cogFUPY4rxIdNn084xQQouekDJtNrL843Jqh8mUKiUDFsSl 0bqiN0/xUdZZGF4y7AyBopndvH3CI/0gWTxSBnCo4hlaHqvtKdTGqIN6Yn/a6aTsVXD5 mRIv6d8lfQjgxgjtfYWiIZe4Ihkm8JkKSwtBjO9MmvRUN3dOde0vyfku6bzIsI9nD8/9 yrrXyD1NfWY7msRsIGz1MgT9JDbR1FNKfGkA+guPCjAt4Dnve+UfoCCuAsPsXgqq3iVx 2Jaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+UIJ4D0C6pJg406mf/36VP+y4bPZApTRahj1mpgvJJc=; b=WdrzbHHpIuNHnmWVrtZl1ZnEfunDQbTrBriliss5JVTmGczxQlIFJGLxqzMT0lI02j Hjc809EvRa6XCYtuibibKOPAlvo1eTwOV6IZzGqmf5bzcRoxbCyx1CsTO7wRSR7XqJmr 6JQaEsKCZWwKDXiac3HWV78+XEfUw8rnAftQLWLgjYDI3vib0WKwwaU/nlPZgREfSu13 gkgys/Fxk1YbmWRy5QwrjrPts7C6mlINDQ9jCqEfZ6mcYwgnRjI7w+NDcST+4z8s3JHl hTGqdVVG/Xa/8qrHhouPXi8HcxgfL79rzFZNN4+29/O1rQJ/W97V326oIuLX88//L6Rb rclQ== X-Gm-Message-State: AHYfb5gKkEVmTflrxgKYQal8Du0jqYvTSeSprJh+dN56gtTc+C9F8lQz 2hUi+FUyvdW8t5CK X-Received: by 10.28.32.15 with SMTP id g15mr6145345wmg.115.1503331399440; Mon, 21 Aug 2017 09:03:19 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:18 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 13/16] mmc: meson-gx: use CCF to handle the clock phases Date: Mon, 21 Aug 2017 18:02:58 +0200 Message-Id: <20170821160301.21899-14-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Several phases can be controlled on the meson-gx controller, the core, tx and rx clock phase. The tx and rx uses delays to allow for a more fine grained setting of the phase. To properly compute the phase using delays, accessing the clock rate is necessary. Instead of ad-hoc functions, use the common clock framework to set the clock phases (and access the clock rate while doing it). Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 217 ++++++++++++++++++++++++++++++++-------- 1 file changed, 176 insertions(+), 41 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 441ebf2b0146..df1ac96bd0db 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -46,10 +46,9 @@ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) -#define CLK_PHASE_0 0 -#define CLK_PHASE_90 1 -#define CLK_PHASE_180 2 -#define CLK_PHASE_270 3 +#define CLK_TX_DELAY_MASK GENMASK(19, 16) +#define CLK_RX_DELAY_MASK GENMASK(23, 20) +#define CLK_DELAY_STEP_PS 200 #define CLK_ALWAYS_ON BIT(24) #define SD_EMMC_DELAY 0x4 @@ -121,9 +120,9 @@ #define MUX_CLK_NUM_PARENTS 2 struct meson_tuning_params { - u8 core_phase; - u8 tx_phase; - u8 rx_phase; + unsigned int core_phase; + unsigned int tx_phase; + unsigned int rx_phase; }; struct sd_emmc_desc { @@ -142,6 +141,8 @@ struct meson_host { void __iomem *regs; struct clk *core_clk; struct clk *mmc_clk; + struct clk *rx_clk; + struct clk *tx_clk; unsigned long req_rate; struct pinctrl *pinctrl; @@ -181,6 +182,90 @@ struct meson_host { #define CMD_RESP_MASK GENMASK(31, 1) #define CMD_RESP_SRAM BIT(0) +struct meson_mmc_phase { + struct clk_hw hw; + void __iomem *reg; + unsigned long phase_mask; + unsigned long delay_mask; + unsigned int delay_step_ps; +}; + +#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) + +static int meson_mmc_clk_get_phase(struct clk_hw *hw) +{ + struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); + unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); + unsigned long period_ps, p, d; + int degrees; + u32 val; + + val = readl(mmc->reg); + p = (val & mmc->phase_mask) >> __bf_shf(mmc->phase_mask); + degrees = p * 360 / phase_num; + + if (mmc->delay_mask) { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + d = (val & mmc->delay_mask) >> __bf_shf(mmc->delay_mask); + degrees += d * mmc->delay_step_ps * 360 / period_ps; + degrees %= 360; + } + + return degrees; +} + +static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, + unsigned int phase, + unsigned int delay) +{ + u32 val; + + val = readl(mmc->reg); + val &= ~mmc->phase_mask; + val |= phase << __bf_shf(mmc->phase_mask); + + if (mmc->delay_mask) { + val &= ~mmc->delay_mask; + val |= delay << __bf_shf(mmc->delay_mask); + } + + writel(val, mmc->reg); +} + +static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) +{ + struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); + unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); + unsigned long period_ps, d = 0, r; + uint64_t p; + + p = degrees % 360; + + if (!mmc->delay_mask) { + p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); + } else { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + + /* First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(p, 360 / phase_num); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * mmc->delay_step_ps); + d = min(d, mmc->delay_mask >> __bf_shf(mmc->delay_mask)); + } + + meson_mmc_apply_phase_delay(mmc, p, d); + return 0; +} + +static const struct clk_ops meson_mmc_clk_phase_ops = { + .get_phase = meson_mmc_clk_get_phase, + .set_phase = meson_mmc_clk_set_phase, +}; + static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) { unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; @@ -373,6 +458,13 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } +static void meson_mmc_set_phase_params(struct meson_host *host) +{ + clk_set_phase(host->mmc_clk, host->tp.core_phase); + clk_set_phase(host->tx_clk, host->tp.tx_phase); + clk_set_phase(host->rx_clk, host->tp.rx_phase); +} + /* * The SD/eMMC IP block has an internal mux and divider used for * generating the MMC clock. Use the clock framework to create and @@ -383,6 +475,7 @@ static int meson_mmc_clk_init(struct meson_host *host) struct clk_init_data init; struct clk_mux *mux; struct clk_divider *div; + struct meson_mmc_phase *core, *tx, *rx; struct clk *clk; char clk_name[32]; int i, ret = 0; @@ -408,9 +501,6 @@ static int meson_mmc_clk_init(struct meson_host *host) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); clk_reg |= CLK_DIV_MASK; clk_reg |= CLK_ALWAYS_ON; writel(clk_reg, host->regs + SD_EMMC_CLOCK); @@ -456,10 +546,80 @@ static int meson_mmc_clk_init(struct meson_host *host) div->flags = (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST); - host->mmc_clk = devm_clk_register(host->dev, &div->hw); + clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + /* create the mmc core clock */ + core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); + if (!core) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = CLK_SET_RATE_PARENT; + clk_parent[0] = __clk_get_name(clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + core->reg = host->regs + SD_EMMC_CLOCK; + core->phase_mask = CLK_CORE_PHASE_MASK; + core->hw.init = &init; + + host->mmc_clk = devm_clk_register(host->dev, &core->hw); if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) return PTR_ERR(host->mmc_clk); + /* create the mmc tx clock */ + tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); + if (!tx) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = 0; + clk_parent[0] = __clk_get_name(host->mmc_clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + tx->reg = host->regs + SD_EMMC_CLOCK; + tx->phase_mask = CLK_TX_PHASE_MASK; + tx->delay_mask = CLK_TX_DELAY_MASK; + tx->delay_step_ps = CLK_DELAY_STEP_PS; + tx->hw.init = &init; + + host->tx_clk = devm_clk_register(host->dev, &tx->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) + return PTR_ERR(host->tx_clk); + + /* create the mmc rx clock */ + rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); + if (!rx) + return -ENOMEM; + + snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); + init.name = clk_name; + init.ops = &meson_mmc_clk_phase_ops; + init.flags = 0; + clk_parent[0] = __clk_get_name(host->mmc_clk); + init.parent_names = clk_parent; + init.num_parents = 1; + + rx->reg = host->regs + SD_EMMC_CLOCK; + rx->phase_mask = CLK_RX_PHASE_MASK; + rx->delay_mask = CLK_RX_DELAY_MASK; + rx->delay_step_ps = CLK_DELAY_STEP_PS; + rx->hw.init = &init; + + host->rx_clk = devm_clk_register(host->dev, &rx->hw); + if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) + return PTR_ERR(host->rx_clk); + + /* Set the initial phase parameters */ + meson_mmc_set_phase_params(host); + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); @@ -469,31 +629,6 @@ static int meson_mmc_clk_init(struct meson_host *host) return clk_prepare_enable(host->mmc_clk); } -static void meson_mmc_set_tuning_params(struct mmc_host *mmc) -{ - struct meson_host *host = mmc_priv(mmc); - u32 regval; - - /* stop clock */ - regval = readl(host->regs + SD_EMMC_CFG); - regval |= CFG_STOP_CLOCK; - writel(regval, host->regs + SD_EMMC_CFG); - - regval = readl(host->regs + SD_EMMC_CLOCK); - regval &= ~CLK_CORE_PHASE_MASK; - regval |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - regval &= ~CLK_TX_PHASE_MASK; - regval |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - regval &= ~CLK_RX_PHASE_MASK; - regval |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - writel(regval, host->regs + SD_EMMC_CLOCK); - - /* start clock */ - regval = readl(host->regs + SD_EMMC_CFG); - regval &= ~CFG_STOP_CLOCK; - writel(regval, host->regs + SD_EMMC_CFG); -} - static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -863,13 +998,13 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) dev_info(mmc_dev(mmc), "(re)tuning...\n"); - for (i = CLK_PHASE_0; i <= CLK_PHASE_270; i++) { + for (i = 0; i < 360; i += 90) { host->tp.rx_phase = i; /* exclude the active parameter set if retuning */ if (!memcmp(&tp_old, &host->tp, sizeof(tp_old)) && mmc->doing_retune) continue; - meson_mmc_set_tuning_params(mmc); + meson_mmc_set_phase_params(host); ret = mmc_send_tuning(mmc, opcode, &cmd_error); if (!ret) break; @@ -1000,9 +1135,9 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; - host->tp.core_phase = CLK_PHASE_180; - host->tp.tx_phase = CLK_PHASE_0; - host->tp.rx_phase = CLK_PHASE_0; + host->tp.core_phase = 180; + host->tp.tx_phase = 0; + host->tp.rx_phase = 0; ret = meson_mmc_clk_init(host); if (ret) From patchwork Mon Aug 21 16:02:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110569 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4244833obb; Mon, 21 Aug 2017 09:05:02 -0700 (PDT) X-Received: by 10.98.202.69 with SMTP id n66mr2506428pfg.197.1503331502736; Mon, 21 Aug 2017 09:05:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331502; cv=none; d=google.com; s=arc-20160816; b=rrTNrnQjnMcn/1hglyu52kLS126l0pu29y8aIAqgkRqChtbIonzXmB5q2Ameo6F6Bw ZZb2jS7BLgDzwKvRQMXQ6rLD0f2FElE6xdrVZOKnzSrI6Yc3+aZ+HG50kU6/DUFmB8hf 9cgoBtRqQeTYlP6QVNZutvjZEXNW9gHht2HsTeC3f8k9C73HapMpXgY10Uy5EcAbqoeY qutiT8VnyRPNsoLsxPeDoKTvBZlsPIdw662sr5imyILbqVg3AvaQ+tN52dlUgDH7iC92 panvMIwm0OZ2R2QITsBj2OBzgc3Fag0mP09ygBFNI1yFO2cr5vbLKzE/Mb7NcrGmXcah DURQ== ARC-Message-Signature: i=1; a=rsa-sha256; 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[209.132.180.67]) by mx.google.com with ESMTP id g5si8269652plj.654.2017.08.21.09.05.02; Mon, 21 Aug 2017 09:05:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ZjlwlA5E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932231AbdHUQEA (ORCPT + 26 others); Mon, 21 Aug 2017 12:04:00 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:36737 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754476AbdHUQDV (ORCPT ); Mon, 21 Aug 2017 12:03:21 -0400 Received: by mail-wr0-f178.google.com with SMTP id f8so67002563wrf.3 for ; Mon, 21 Aug 2017 09:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GuyOubelvJA7rWpAisvKFUWKQSlHIpAuJJBzrfBNATs=; b=ZjlwlA5EtHtHCKHeNPKT9LcwsAPRXHXS1fSAALWzfAtFBXIpchLsvc4lD+P+HLly1m DA/93lfsPPhsgV/pUMp52mxEBZTMotG1T40drv5x8o+jbcKUsTQPH/xxO0jPaky92Aeh scnZLQn0ftO5YMp3ad7JYrJazhnfRRgakcb5xnhJ5I6L+WmR+tS/04+iMi8G9NbyYzwR qCcpzmY7yGiOa0QlOHkN71dtTClxaXxnvLCKnDP5NhY9U2fYpZ1ohVxI+Ds1qE9A/1eb bafOoBBwxRytUwWdQFIfZa97GKLVlzeLmIu99oHQVA/QUQZUQ9J9Y7wrJVncApAFCbw+ uPwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GuyOubelvJA7rWpAisvKFUWKQSlHIpAuJJBzrfBNATs=; b=hn8mqTbIb5ttrSw2N0EuMXFgH3NLCe9x4jJ9EoJ/pD0sbSLk6Jf4Ex/GjrRqHhmUZS OWUxxLwZZeRtHyNTyiliMWp6V2B/mVsT4HlPdK8lFxExsa0nCeF+L0XJcn2GLxoyqWHI 4g3SL8lrvvfpNcCkbznN2+ZIrJ4Kd/fh5uMIQJSh7v/wnYZNHxM8SQ+jSkDMbnIQwGmv sJnbzHEvvDnxickO38HNhcTy3Uz0OZhtZ41w+0iJRQ5QKy0efLVM8B2nXyUJTS52bSdi QrNZ0PnW3F9+zwJyYoHqERfbMgAmIqF26IgkGR2XjBPw2vZs+x14BwUe/3W1COoe+PsD eDxA== X-Gm-Message-State: AHYfb5jP/zr5JxbGkYw2loDg+mVsL0UZwM02YwgN9Bug0YuHyXyj/w7/ w8hAal6IAmrGKHOy X-Received: by 10.28.195.87 with SMTP id t84mr1866595wmf.99.1503331400541; Mon, 21 Aug 2017 09:03:20 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:19 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 14/16] mmc: meson-gx: implement voltage switch callback Date: Mon, 21 Aug 2017 18:02:59 +0200 Message-Id: <20170821160301.21899-15-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement voltage switch callback (shamelessly copied from sunxi mmc driver). This allow, with the appropriate tuning function, to use SD ultra high speed modes. Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index df1ac96bd0db..3167f561e1a6 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1050,6 +1050,28 @@ static int meson_mmc_card_busy(struct mmc_host *mmc) return !(FIELD_GET(STATUS_DATI, regval) & 0xf); } +static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) +{ + /* vqmmc regulator is available */ + if (!IS_ERR(mmc->supply.vqmmc)) { + /* + * The usual amlogic setup uses a GPIO to switch from one + * regulator to the other. While the voltage ramp up is + * pretty fast, care must be taken when switching from 3.3v + * to 1.8v. Please make sure the regulator framework is aware + * of your own regulator constraints + */ + return mmc_regulator_set_vqmmc(mmc, ios); + + } + + /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) + return 0; + + return -EINVAL; +} + static const struct mmc_host_ops meson_mmc_ops = { .request = meson_mmc_request, .set_ios = meson_mmc_set_ios, @@ -1058,6 +1080,7 @@ static const struct mmc_host_ops meson_mmc_ops = { .post_req = meson_mmc_post_req, .execute_tuning = meson_mmc_execute_tuning, .card_busy = meson_mmc_card_busy, + .start_signal_voltage_switch = meson_mmc_voltage_switch, }; static int meson_mmc_probe(struct platform_device *pdev) From patchwork Mon Aug 21 16:03:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110570 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4245194obb; Mon, 21 Aug 2017 09:05:18 -0700 (PDT) X-Received: by 10.99.65.65 with SMTP id o62mr16953840pga.7.1503331518666; Mon, 21 Aug 2017 09:05:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331518; cv=none; d=google.com; s=arc-20160816; b=UD3soGaKi4ZmEpuiYCZiF4vlq8iMgCBUuIzBmhe/1SQA+f0GDFQMD8J3DEsOm+INS9 Hg0XZyS8Gj0EYGdmHpdA6oORBTi6Hpvw31XbGuHQF+CrttowNrGMP996FU/iQ3GHivVK R+TbzI/J9qw0Cwt9TPGVg3hKpKag/9WzzrQxNG9WqSF5GlSp9CfuQ4g15WnpODcw3hlr 6gS5QV0Cc+NAu3DgvO7IJp2kXtCwSuIRMCkBvCQAP+Be9elouR/nrn6yvL8Eixn2JlU5 X611YVDURfsALk8zUMpG9qJXcJd4AFXZeizb7pxU3v96+cuBm5Mua+kEYFFL3PqIb47C 6i5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pwhGKSiatDZIKAM4wyfDOdqR/aXoik20ct+gofTiRgA=; b=MesaNHtkyGa04XbB9xNibSmiaAtK9OIGpynarm81NpwJvnrXBFvWBSqYhguywOfDW7 uaAvusH9wlobQYlgxYhGjsGkMfQAlPT+ZqroAJvk4hLGapc4PvEZUSc7jySPrtubkaPA mP8IjIh9V02RzhWJmXtQmYOQ9/UW0087bVcUPstEjU+E9cHF48SLtHYNSBlxv3nwrXbE pi+AL79ieW5KeEpmaFH4TA7g1A9hn1kcE5m1lxzsr/159W/1Y56syt0zdZB4q3Vupd2y Gq4Lv+Bdy1vtgEmm3V/RFJ5yhwYrSmzEL2zMFyxlfGwPxzHlvAztgj1Pr6U3Ss6Vyjx0 66Lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=EsWmTVyu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Some cards fails to initialize with this setting and eMMC mode DDR52 does not work. Changing this setting to 270 fixes these issues, without any regression so far Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.9.5 Reviewed-by: Kevin Hilman diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3167f561e1a6..290631d46a4b 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1158,8 +1158,14 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; + /* + * Set phases : These values are mostly the datasheet recommended ones + * except for the Tx phase. Datasheet recommends 180 but some cards + * fail at initialisation with it. 270 works just fine, it fixes these + * initialisation issues and enable eMMC DDR52 mode. + */ host->tp.core_phase = 180; - host->tp.tx_phase = 0; + host->tp.tx_phase = 270; host->tp.rx_phase = 0; ret = meson_mmc_clk_init(host); From patchwork Mon Aug 21 16:03:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 110565 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4242884obb; Mon, 21 Aug 2017 09:03:40 -0700 (PDT) X-Received: by 10.99.126.80 with SMTP id o16mr7134227pgn.378.1503331420841; Mon, 21 Aug 2017 09:03:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503331420; cv=none; d=google.com; s=arc-20160816; b=Eji3Ee6czSBcmnh6zEvcGirQgGmINu54/YZ/rShLwAthntZmbky5899Y/QelMJsZY/ NhkXgbxQou1xidXHS2cZDFe8gcabJZe6aEIQrdgT5ptxdt30Iq69lFJYhtqe1UWH/v6g EWvvd12jHgNXZ+GG/CoGq4N94HSf3e4EDX/fWTT6d8NAuucM4t/WLY8oLyznm8cSv2HO NsPVW+AhZ3uNuXerRS9P7pee/7OazARgzvTsXGPn5PILKDT6iXL8uIKd0UR/sST5XJSd 3OpDrnLXv35tsG3E2AopXYX9rZ0iQiPMtFJaKss4iekr5+ylRuCslHEHVcQQ8stJAmNh 6LKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=FWSza7nhxFmVrAqzMRATkKe+54E1gYR3WI8OGLT7VxQ=; b=IRQzw6iLaaU2TxrGaASnx0UWwB156Uhw4mkVkjB8rrda6oCRdUQ33lu+Sxe1GOT4uT v/NdS5uuvORbtQ2FVNt+nml4SGfr5461f2QGNJxwfNt1Kp0abicIIUx9IHW/yv+BC3VD iu2k5e1g8JMp0PtCYcKg/hogg3xD0RvvIxh29qPwCe0XJG5FoG2HhAOpYK3VP/G+Wi9s TtGM2SXAPEvaH+SM/C1F1JeQ/KtcAqC4nlXBmL/rIm21xRvtCZDpy7Ud+7vPpKWDxZlm 0tKg27oUbRrKPVCKBp+74+EyBlb33sOanxcJ1Hkd7K9BdGhLiYCcqibfh2/77hZ9vcZx p+DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=PMnzi2Mq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q67si7423553pgq.557.2017.08.21.09.03.40; Mon, 21 Aug 2017 09:03:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=PMnzi2Mq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754507AbdHUQDi (ORCPT + 26 others); Mon, 21 Aug 2017 12:03:38 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:36760 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754483AbdHUQDY (ORCPT ); Mon, 21 Aug 2017 12:03:24 -0400 Received: by mail-wr0-f170.google.com with SMTP id f8so67003508wrf.3 for ; Mon, 21 Aug 2017 09:03:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FWSza7nhxFmVrAqzMRATkKe+54E1gYR3WI8OGLT7VxQ=; b=PMnzi2MqCiK+E8STsUOZeHRCziCVyZHgSCbVEiAVpeYGTo/c+F+kZkx6JJTtrCHtQt FaQoHLX28wL6/wQ+hXss7Izk98UUFIGFc0dC1rDd0K5L7BAw2VEFWctp/N0d/x164BrO +ZBYMTiJRxlgBDtAY7aSrRgCYL/fhypOzsVcjyPhML52W2WJZcLX3af3TlapmKM+2GEk laFZDH1jgC1/PwuBGsh0/eL8fk6TLzrVTQXqdKYWQFqiH+qFh9cJBGdD63CNwka/X75E hcftaRPYB44Ir8GdTbEBM4g2S2bRHS0ZrZqecICW1gBAI7C73MtiY9l7fifKAKO6rV7V dblg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FWSza7nhxFmVrAqzMRATkKe+54E1gYR3WI8OGLT7VxQ=; b=DOnM4LRn98GaPBe5Cv3Z7zd38XntsZDf4tA3q9VTHZl8P6PbaEzWaE4ouGMVPlcJct C2b3e4/ExW3G4Pc6nGRWVNVpa/dIDqQuDIMSTKKCUd3nvL5G34gk2iwR1uEgzQNKxcu0 1/IE/xx6FT0U2FmW7yH/EAD0SV+Q70iUYWIQ0ZfBIRK7P0wJK2O5r3LMHGxHdt0n8uSq dtSC1xm227l/d6qnHmu9mLxPN3rB4WEITWx+MpifGnMeebmZ2w4xQBkYL66io+iVB8xD 8YPOWEEzveXdIWDIOh4yWjPIYEHBgAeNbdk8pcJ2q/0DhQ1ys2hdJdgrSVzKb6f20uxt tOtA== X-Gm-Message-State: AHYfb5jmHMGjRbxn+BpzroscXnr6mDcXd8eIF9B88WnTceESy1OyF+SM iqi3Ikyu5ee6aVrX X-Received: by 10.28.193.203 with SMTP id r194mr6401039wmf.85.1503331402733; Mon, 21 Aug 2017 09:03:22 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id 63sm8120063wra.30.2017.08.21.09.03.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Aug 2017 09:03:22 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 16/16] mmc: meson-gx: rework tuning function Date: Mon, 21 Aug 2017 18:03:01 +0200 Message-Id: <20170821160301.21899-17-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170821160301.21899-1-jbrunet@baylibre.com> References: <20170821160301.21899-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework tuning function of the rx phase. Now that the phase can be more precisely set using CCF, test more phase setting and find the largest working window. Then the tuning selected is the one at the center of the window. This rework allows to use new modes, such as UHS SDR50 Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 161 +++++++++++++++++++++++++++------------- 1 file changed, 111 insertions(+), 50 deletions(-) -- 2.9.5 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 290631d46a4b..137b93227629 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_TX_DELAY_MASK GENMASK(19, 16) #define CLK_RX_DELAY_MASK GENMASK(23, 20) #define CLK_DELAY_STEP_PS 200 +#define CLK_PHASE_STEP 30 +#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) #define CLK_ALWAYS_ON BIT(24) #define SD_EMMC_DELAY 0x4 @@ -119,12 +121,6 @@ #define MUX_CLK_NUM_PARENTS 2 -struct meson_tuning_params { - unsigned int core_phase; - unsigned int tx_phase; - unsigned int rx_phase; -}; - struct sd_emmc_desc { u32 cmd_cfg; u32 cmd_arg; @@ -155,7 +151,6 @@ struct meson_host { struct sd_emmc_desc *descs; dma_addr_t descs_dma_addr; - struct meson_tuning_params tp; bool vqmmc_enabled; }; @@ -458,13 +453,6 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) return 0; } -static void meson_mmc_set_phase_params(struct meson_host *host) -{ - clk_set_phase(host->mmc_clk, host->tp.core_phase); - clk_set_phase(host->tx_clk, host->tp.tx_phase); - clk_set_phase(host->rx_clk, host->tp.rx_phase); -} - /* * The SD/eMMC IP block has an internal mux and divider used for * generating the MMC clock. Use the clock framework to create and @@ -617,18 +605,122 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) return PTR_ERR(host->rx_clk); - /* Set the initial phase parameters */ - meson_mmc_set_phase_params(host); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) return ret; + /* + * Set phases : These values are mostly the datasheet recommended ones + * except for the Tx phase. Datasheet recommends 180 but some cards + * fail at initialisation with it. 270 works just fine, it fixes these + * initialisation issues and enable eMMC DDR52 mode. + */ + clk_set_phase(host->mmc_clk, 180); + clk_set_phase(host->tx_clk, 270); + clk_set_phase(host->rx_clk, 0); + return clk_prepare_enable(host->mmc_clk); } +static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) +{ + DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); + DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); + + /* + * shift the bitmap right and reintroduce the dropped bits on the left + * of the bitmap + */ + bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); + bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, + CLK_PHASE_POINT_NUM); + bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); +} + +static void meson_mmc_find_next_region(unsigned long *map, + unsigned long *start, + unsigned long *stop) +{ + *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); + *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); +} + +static int meson_mmc_find_tuning_point(unsigned long *test) +{ + unsigned long shift, stop, offset = 0, start = 0, size = 0; + + /* Get the all good/all bad situation out the way */ + if (bitmap_full(test, CLK_PHASE_POINT_NUM)) + return 0; /* All points are good so point 0 will do */ + else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) + return -EIO; /* No successful tuning point */ + + /* + * Now we know there is a least one region find. Make sure it does + * not wrap by the shifting the bitmap if necessary + */ + shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); + if (shift != 0) + meson_mmc_shift_map(test, shift); + + while (start < CLK_PHASE_POINT_NUM) { + meson_mmc_find_next_region(test, &start, &stop); + + if ((stop - start) > size) { + offset = start; + size = stop - start; + } + + start = stop; + } + + /* Get the center point of the region */ + offset += (size / 2); + + /* Shift the result back */ + offset = (offset + shift) % CLK_PHASE_POINT_NUM; + + return offset; +} + +static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, + struct clk *clk) +{ + int point, ret; + DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); + + dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", + __clk_get_name(clk)); + bitmap_zero(test, CLK_PHASE_POINT_NUM); + + /* Explore tuning points */ + for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { + clk_set_phase(clk, point * CLK_PHASE_STEP); + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) + set_bit(point, test); + } + + /* Find the optimal tuning point and apply it */ + point = meson_mmc_find_tuning_point(test); + if (point < 0) + return point; /* tuning failed */ + + clk_set_phase(clk, point * CLK_PHASE_STEP); + dev_dbg(mmc_dev(mmc), "success with phase: %d\n", + clk_get_phase(clk)); + return 0; +} + +static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct meson_host *host = mmc_priv(mmc); + + return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -667,6 +759,8 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) host->vqmmc_enabled = true; } + /* Reset rx phase */ + clk_set_phase(host->rx_clk, 0); break; } @@ -990,29 +1084,6 @@ static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) return IRQ_HANDLED; } -static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) -{ - struct meson_host *host = mmc_priv(mmc); - struct meson_tuning_params tp_old = host->tp; - int ret = -EINVAL, i, cmd_error; - - dev_info(mmc_dev(mmc), "(re)tuning...\n"); - - for (i = 0; i < 360; i += 90) { - host->tp.rx_phase = i; - /* exclude the active parameter set if retuning */ - if (!memcmp(&tp_old, &host->tp, sizeof(tp_old)) && - mmc->doing_retune) - continue; - meson_mmc_set_phase_params(host); - ret = mmc_send_tuning(mmc, opcode, &cmd_error); - if (!ret) - break; - } - - return ret; -} - /* * NOTE: we only need this until the GPIO/pinctrl driver can handle * interrupts. For now, the MMC core will use this for polling. @@ -1158,16 +1229,6 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; - /* - * Set phases : These values are mostly the datasheet recommended ones - * except for the Tx phase. Datasheet recommends 180 but some cards - * fail at initialisation with it. 270 works just fine, it fixes these - * initialisation issues and enable eMMC DDR52 mode. - */ - host->tp.core_phase = 180; - host->tp.tx_phase = 270; - host->tp.rx_phase = 0; - ret = meson_mmc_clk_init(host); if (ret) goto err_core_clk;