From patchwork Mon Mar 9 21:07:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C15AC10F25 for ; Mon, 9 Mar 2020 21:08:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DFBC024655 for ; Mon, 9 Mar 2020 21:08:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XEjDDu7c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726932AbgCIVIt (ORCPT ); Mon, 9 Mar 2020 17:08:49 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:40842 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726118AbgCIVIs (ORCPT ); Mon, 9 Mar 2020 17:08:48 -0400 Received: by mail-wr1-f65.google.com with SMTP id p2so12242660wrw.7; Mon, 09 Mar 2020 14:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GzyAiqo4rFDPCZ0tgI6VRMILwWz+jZH78kexviER6Rk=; b=XEjDDu7cGa+PfMYkKG7e3ZzBQx83G9i/1pY8jzvtASfMqVQHe8L/iQM+9lkxSGbCuG C6FMqn+c6zOIOPWEduxT6u3b4780kfZBkxBG8VrbrpIbiDJgUVqMTqx1gl6YK1dIspOH BAxjJCmRx0uav71mBPwEO3iYK5ezP7EsQg+DHLDqTHz8pYYSwUQbSiJxLrTXaMec3N0Z frrBqcxs+xoaY2mVXdYctkPg0iUpjdYjOUe7vdgOh/RYS/lSh4Yw23TzknOgFYfsOPN9 8J3URcvX2ktGTMrqK0tRbeVrEuN1sz8GHkKrQ1pQ4PqD0yrWu5RBMunc/gjjh+yjI9Nv IR/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GzyAiqo4rFDPCZ0tgI6VRMILwWz+jZH78kexviER6Rk=; b=A/FGAo2kX8fC8J/WNnH2f0eKeArRkdEA5spS9GBYxqMJ1m80KoRUkpJTu5Rlsymoge bAJC6E9f1LfSG0svNZSCe9poyRbhhzt1Ga4Qnew1pcWHesmT/xQAJ7NtkOv4/oiySRNI MrNQR8DwrQP7oAYbLFYpKjQj+2xd77OI4cVD40cm+pwkVbypriocSLqLJJjmF9oPPYRP 5BkDzIccTWeZInc1vfizgKDFqCriXgPlS01KndZRbcTZqGTiZhpui9d8tZZe/KHYAW3N OhSc12ftNOV/NA7J4mAP5LsBi6q92jQuGuu59wFGrk3TGFGFts0YQqrVcZUAC65c4tNa tvcA== X-Gm-Message-State: ANhLgQ1C4XnX92VpBEXFALd9EUi5EyWVaXxMmr9aF8HrMywFieK8ISDL xBGljA+FK9pCukeGMkCSvDg= X-Google-Smtp-Source: ADFU+vuM3Rjr1Ncf4MMecDXYLwy+kESuLdkVVfVLus90/bUuAkgv1pfn1b+W8RekoJuB1121gqdk5A== X-Received: by 2002:a5d:4902:: with SMTP id x2mr24327896wrq.301.1583788126003; Mon, 09 Mar 2020 14:08:46 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id j205sm1016275wma.42.2020.03.09.14.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2020 14:08:45 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v2 2/6] spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA Date: Mon, 9 Mar 2020 23:07:51 +0200 Message-Id: <20200309210755.6759-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309210755.6759-1-olteanv@gmail.com> References: <20200309210755.6759-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean In XSPI mode, the 32-bit PUSHR register can be written to separately: the higher 16 bits are for commands and the lower 16 bits are for data. This has nicely been hacked around, by defining a second regmap with a width of 16 bits, and effectively splitting a 32-bit register into 2 16-bit ones, from the perspective of this regmap_pushr. The problem is the assumption about the controller's endianness. If the controller is little endian (such as anything post-LS1046A), then the first 2 bytes, in the order imposed by memory layout, will actually hold the TXDATA, and the last 2 bytes will hold the CMD. So take the controller's endianness into account when performing split writes to PUSHR. The obvious and simple solution would have been to call regmap_get_val_endian(), but that is an internal regmap function and we don't want to change regmap just for this. Therefore, we just re-read the "big-endian" device tree property. Fixes: 58ba07ec79e6 ("spi: spi-fsl-dspi: Add support for XSPI mode registers") Signed-off-by: Vladimir Oltean --- Changes in v2: Parse "big-endian" device tree bindings instead of taking the decision based on compatible SoC. drivers/spi/spi-fsl-dspi.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 0ce26c1cbf62..0483abd403a4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -103,10 +103,6 @@ #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) -/* Register offsets for regmap_pushr */ -#define PUSHR_CMD 0x0 -#define PUSHR_TX 0x2 - #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) struct chip_data { @@ -240,6 +236,13 @@ struct fsl_dspi { int words_in_flight; + /* + * Offsets for CMD and TXDATA within SPI_PUSHR when accessed + * individually (in XSPI mode) + */ + int pushr_cmd; + int pushr_tx; + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; @@ -670,12 +673,12 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) */ if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; - regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); + regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); } static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { - regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); + regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); } static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) @@ -1256,6 +1259,7 @@ static int dspi_probe(struct platform_device *pdev) struct fsl_dspi *dspi; struct resource *res; void __iomem *base; + bool big_endian; ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); if (!ctlr) @@ -1281,6 +1285,7 @@ static int dspi_probe(struct platform_device *pdev) /* Only Coldfire uses platform data */ dspi->devtype_data = &devtype_data[MCF5441X]; + big_endian = true; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); @@ -1302,6 +1307,15 @@ static int dspi_probe(struct platform_device *pdev) ret = -EFAULT; goto out_ctlr_put; } + + big_endian = of_device_is_big_endian(np); + } + if (big_endian) { + dspi->pushr_cmd = 0; + dspi->pushr_tx = 2; + } else { + dspi->pushr_cmd = 2; + dspi->pushr_tx = 0; } if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) From patchwork Mon Mar 9 21:07:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1395EC10F25 for ; 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Mon, 09 Mar 2020 14:08:48 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v2 4/6] spi: spi-fsl-dspi: Add support for LS1028A Date: Mon, 9 Mar 2020 23:07:53 +0200 Message-Id: <20200309210755.6759-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200309210755.6759-1-olteanv@gmail.com> References: <20200309210755.6759-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean This is similar to the DSPI instantiation on LS1028A, except that: - The A-011218 erratum has been fixed, so DMA works - The endianness is different, which has implications on XSPI mode Some benchmarking with the following command: spidev_test --device /dev/spidev2.0 --bpw 8 --size 256 --cpha --iter 10000000 --speed 20000000 shows that in DMA mode, it can achieve around 2400 kbps, and in XSPI mode, the same command goes up to 4700 kbps. This is somewhat to be expected, since the DMA buffer size is extremely small at 8 bytes, the winner becomes whomever can prepare the buffers for transmission quicker, and DMA mode has higher overhead there. So XSPI FIFO mode has been chosen as the operating mode for this chip. Signed-off-by: Vladimir Oltean --- Changes in v2: Switch to DSPI_XSPI_MODE. drivers/spi/spi-fsl-dspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 43d2d9fc8b92..cf8a141bbaf2 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -125,6 +125,7 @@ struct fsl_dspi_devtype_data { enum { LS1021A, LS1012A, + LS1028A, LS1043A, LS1046A, LS2080A, @@ -153,6 +154,12 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .max_clock_factor = 8, .fifo_size = 16, }, + [LS1028A] = { + .trans_mode = DSPI_XSPI_MODE, + .dma_bufsize = 8, + .max_clock_factor = 8, + .fifo_size = 4, + }, [LS1043A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, @@ -1100,6 +1107,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }, { .compatible = "fsl,ls1012a-dspi", .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1028a-dspi", + .data = &devtype_data[LS1028A], }, { .compatible = "fsl,ls1043a-dspi", .data = &devtype_data[LS1043A], From patchwork Mon Mar 9 21:07:55 2020 Content-Type: text/plain; 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Mon, 9 Mar 2020 17:08:54 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46611 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727030AbgCIVIx (ORCPT ); Mon, 9 Mar 2020 17:08:53 -0400 Received: by mail-wr1-f66.google.com with SMTP id n15so13014312wrw.13; Mon, 09 Mar 2020 14:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kAEXGIBTihs2aEXLy+/u0H3T9UnyJrJyBGNNvIDBqSQ=; b=TWCaCqSPmiFJmxJN3aCnLwv2ssaFFm8FOa/wqZJCht7oJDCzhqWxWQvZMp+qr/Rait dNI9vOe3IBXvfj9BbQnNrXiFwacEQB6Jr94SD7J8TABorbw9SlGzwCm/u2qEm7PCn+SV hBfbwPfyNKANya8pIjT4oHQwV6zLNgRAcYdEOXxhqHsYoCVrtqDA7OvN4vgVyiFgj11o nmDgdETMu6lU0pPbWSjP2XsXZhLR4bWHm+HTfEK7pg5yobgJ60pxu6BmfqiNB48T7/HU WxJ8Fh3+szMQwrChXAfUwnH+XVZ0rglHvMIlgypPpn6KgqEuAnKCLedhqpntKQliZB6t l3CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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On the reference design board, these are exported to either the mikroBUS1 or mikroBUS2 connector (according to the CPLD register BRDCFG3[SPI3]). Signed-off-by: Vladimir Oltean --- Changes in v2: Change compatible string for spidev node. arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index bb7ba3bcbe56..13555ed52b89 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -83,6 +83,20 @@ }; }; +&dspi2 { + bus-num = <2>; + status = "okay"; + + /* mikroBUS1 */ + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <20000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; + reg = <0>; + }; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50;