From patchwork Wed Mar 18 10:31:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 203139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD770C10DCE for ; Wed, 18 Mar 2020 10:31:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 815DD2076C for ; Wed, 18 Mar 2020 10:31:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="j7De3Ill" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727594AbgCRKbn (ORCPT ); Wed, 18 Mar 2020 06:31:43 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:7443 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727324AbgCRKbm (ORCPT ); Wed, 18 Mar 2020 06:31:42 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 18 Mar 2020 03:30:52 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 18 Mar 2020 03:31:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 18 Mar 2020 03:31:41 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Mar 2020 10:31:41 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Mar 2020 10:31:41 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 18 Mar 2020 03:31:40 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , , , Nagarjuna Kristam Subject: [PATCH V1 1/8] dt-bindings: phy: tegra-xusb: Add charger-detect property Date: Wed, 18 Mar 2020 16:01:00 +0530 Message-ID: <1584527467-8058-2-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> References: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584527452; bh=Ur7COE1LR32rGOz+P92MOunBwsp5tY0yJq0Yuagh3FA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=j7De3Ill6zgqK3UmI3iIErLBoTjeUXQkQaGVIH17WXclxVYWZPm/If8jFhd9URArX lyLmZ8eg98VGuTzZlfsqDs2t1S6AsxS8LoemFS7MCPf3mMQPRTX/4eoast6zd+xspc sfr5rxgP9XVpDzkeQ1HCpuQQwVnRM2G/7EkREikTRIGaTpOiWg5FwYj0rn+i1FS5hJ lppSCHaZzPYcySJjCJA6d62AO4fym5oOvhwcqNj/KaaOhxeoI36dx1YoswyS94bF3s gg0XKEe3SlnJtxEZ2TFPoePWeukrsVYLyfKc65WFbfrpUJ7QG3cLP0hFZFPS7GVCXv vWJc2nZiRRoOg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add nvidia,charger-detect boolean property for Tegra210 and Tegra186 platforms. This property is used to inform driver to perform charger detection on corresponding USB 2 port. Signed-off-by: Nagarjuna Kristam --- Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 38c5fa2..9b2d2dd 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -190,6 +190,10 @@ Required properties for OTG/Peripheral capable USB2 ports: and peripheral roles. Connector should be added as subnode. See usb/usb-conn-gpio.txt. +Optional properties for OTG/Peripheral capable USB2 ports: +- nvidia,charger-detect: A boolean property whose presence inform driver to + perform charger-detect activity. + Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be From patchwork Wed Mar 18 10:31:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 203136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23DA7C5ACD8 for ; Wed, 18 Mar 2020 10:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E696520770 for ; Wed, 18 Mar 2020 10:32:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="A9PR2Pje" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727815AbgCRKbz (ORCPT ); Wed, 18 Mar 2020 06:31:55 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:7086 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727800AbgCRKby (ORCPT ); Wed, 18 Mar 2020 06:31:54 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 18 Mar 2020 03:31:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 18 Mar 2020 03:31:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 18 Mar 2020 03:31:53 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Mar 2020 10:31:53 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Mar 2020 10:31:53 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 18 Mar 2020 03:31:52 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , , , Nagarjuna Kristam Subject: [PATCH V1 4/8] phy: tegra: xusb: Add USB2 pad power control support for Tegra210 Date: Wed, 18 Mar 2020 16:01:03 +0530 Message-ID: <1584527467-8058-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> References: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584527500; bh=tEoOEHoqSMKBOPIlCwlXMu5sLKIef0sdU0dEXS+YRvg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=A9PR2Pjeeyv/r9rWLuSqTaDvorDmCFD2jUFnDPbUSnWFd+UsoZT2Xn/TOJny7iMkz wRR0o8RO+VKKWMcNyPu5imyXKs6JS48BI6YggMwhpIn4DlTZ1CAZu+uKO279Vx61SV cCGKWUWAHUsGLg+tHuWmgmG5h3D+YxpOV6OLfR/nVOt9Pe3RJpQeA+AmelWhvxc1D0 e1zS92w0DqaDh2PG5NjdY2ZN4YPDO61VCltCjQrPzjb4JyfTlL1EDwqpr9Gt1B6Lvl B5qyBJQKkpI0rBP1xU5aIwqjkvKR/GedRgDwsfeI+hYMeR5+6QvGcJ/cHOr3LAf9bA xjE7NiJ2AMoKA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add USB2 pad power on and off API's for TEgra210 and provide its control via soc ops. It can be used by operations like charger detect to power on and off USB2 pad if needed. Signed-off-by: Nagarjuna Kristam --- drivers/phy/tegra/xusb-tegra210.c | 190 ++++++++++++++++++++++++++------------ 1 file changed, 133 insertions(+), 57 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index 54d6826..0841564 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -994,6 +994,128 @@ static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, return 0; } +static void tegra210_usb2_bias_pad_power_on(struct tegra_xusb_usb2_pad *pad) +{ + struct tegra_xusb_padctl *padctl = pad->base.padctl; + u32 value; + + if (pad->enable++ > 0) + return; + + dev_dbg(padctl->dev, "power on BIAS PAD & USB2 tracking\n"); + + if (clk_prepare_enable(pad->clk)) + dev_warn(padctl->dev, "failed to enable BIAS PAD & USB2 tracking\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << + XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | + (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK << + XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT)); + value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << + XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | + (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL << + XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT); + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + + udelay(1); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + + udelay(50); +} + +static void tegra210_usb2_bias_pad_power_off(struct tegra_xusb_usb2_pad *pad) +{ + struct tegra_xusb_padctl *padctl = pad->base.padctl; + u32 value; + + if (WARN_ON(pad->enable == 0)) + return; + + if (--pad->enable > 0) + return; + + dev_dbg(padctl->dev, "power off USB2 tracking\n"); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + + clk_disable_unprepare(pad->clk); +} + +/* must be called under padctl->lock */ +void tegra210_usb2_pad_power_on(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); + struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + unsigned int index = lane->index; + u32 value; + + if (!phy) + return; + + if (usb2->powered_on) + return; + + dev_info(padctl->dev, "power on UTMI pads %d\n", index); + + tegra210_usb2_bias_pad_power_on(pad); + + udelay(2); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + value &= ~XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + value &= ~XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + + usb2->powered_on = true; +} + +/* must be called under padctl->lock */ +void tegra210_usb2_pad_power_down(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); + struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + unsigned int index = lane->index; + u32 value; + + if (!phy) + return; + + if (!usb2->powered_on) + return; + + dev_info(padctl->dev, "power down UTMI pad %d\n", index); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + value |= XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + value |= XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + + udelay(2); + + tegra210_usb2_bias_pad_power_off(pad); + usb2->powered_on = false; +} + static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { @@ -1037,7 +1159,6 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) { struct tegra_xusb_lane *lane = phy_get_drvdata(phy); struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); - struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); struct tegra_xusb_padctl *padctl = lane->pad->padctl; struct tegra210_xusb_padctl *priv; struct tegra_xusb_usb2_port *port; @@ -1053,6 +1174,8 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) priv = to_tegra210_xusb_padctl(padctl); + mutex_lock(&padctl->lock); + if (port->usb3_port_fake != -1) { value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK( @@ -1148,62 +1271,21 @@ static int tegra210_usb2_phy_power_on(struct phy *phy) if (port->supply && port->mode == USB_DR_MODE_HOST) { err = regulator_enable(port->supply); - if (err) + if (err) { + mutex_unlock(&padctl->lock); return err; + } } - mutex_lock(&padctl->lock); - - if (pad->enable > 0) { - pad->enable++; - mutex_unlock(&padctl->lock); - return 0; - } - - err = clk_prepare_enable(pad->clk); - if (err) - goto disable_regulator; + tegra210_usb2_pad_power_on(phy); - value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << - XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | - (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK << - XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT)); - value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << - XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | - (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL << - XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT); - padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - - value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); - value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; - padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); - - udelay(1); - - value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; - padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - - udelay(50); - - clk_disable_unprepare(pad->clk); - - pad->enable++; mutex_unlock(&padctl->lock); - return 0; - -disable_regulator: - regulator_disable(port->supply); - mutex_unlock(&padctl->lock); - return err; } static int tegra210_usb2_phy_power_off(struct phy *phy) { struct tegra_xusb_lane *lane = phy_get_drvdata(phy); - struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); struct tegra_xusb_padctl *padctl = lane->pad->padctl; struct tegra_xusb_usb2_port *port; u32 value; @@ -1217,6 +1299,8 @@ static int tegra210_usb2_phy_power_off(struct phy *phy) mutex_lock(&padctl->lock); + tegra210_usb2_pad_power_down(phy); + if (port->usb3_port_fake != -1) { value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY( @@ -1243,18 +1327,8 @@ static int tegra210_usb2_phy_power_off(struct phy *phy) padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); } - if (WARN_ON(pad->enable == 0)) - goto out; - - if (--pad->enable > 0) - goto out; - - value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); - value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; - padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); - -out: regulator_disable(port->supply); + mutex_unlock(&padctl->lock); return 0; } @@ -2210,6 +2284,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = { .hsic_set_idle = tegra210_hsic_set_idle, .vbus_override = tegra210_xusb_padctl_vbus_override, .utmi_port_reset = tegra210_utmi_port_reset, + .utmi_pad_power_on = tegra210_usb2_pad_power_on, + .utmi_pad_power_down = tegra210_usb2_pad_power_down, }; static const char * const tegra210_xusb_padctl_supply_names[] = { From patchwork Wed Mar 18 10:31:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 203138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50312C5ACD8 for ; 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by hqpgpgate101.nvidia.com on Wed, 18 Mar 2020 03:31:58 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Mar 2020 10:31:58 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Mar 2020 10:31:58 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 18 Mar 2020 03:31:57 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , , , Nagarjuna Kristam Subject: [PATCH V1 5/8] phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection Date: Wed, 18 Mar 2020 16:01:04 +0530 Message-ID: <1584527467-8058-6-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> References: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584527505; bh=pY6qvJepwpU2bb/SniBNpFYzDjpr4moHCnxDbEyBKfk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=m6AYWv4vVTKPhDh1xjxqPjnGfjXaJC7VELyEa0GptwvzyfqDkKb0PYNM83K12994L wE+FCnQ0NXVlALk8U6q24fClox6hyfyAVsgMvz4J0y1pdq/q54s0oGk0g1vRXkiGpS TzxrZPh3KNxAw8exppAGJ8AAVs7oxWS1euPz1j60pGp0FE/InIEZX6X6ty4mz16Eas 9Em0szhIk5fXiTdiyTrVFRpjEEe2Ff9DTKg3XD8BeNJrLEw1q9+VGW5EH6ueMC99Xy 5OCrQtQxrWET4lXZPZDu9BQemosnHvuEcFyItg669/hBz43VOR5QIqPbkUo50mkPKE mvTFR6K/fLzOw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org AWhen USB charger is enabled, UTMI PAD needs to be protected according to the direction and current level. Add support for the same on Tegra210 and Tegra186. Signed-off-by: Nagarjuna Kristam --- drivers/phy/tegra/xusb-tegra186.c | 40 +++++++++++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb-tegra210.c | 31 ++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.h | 13 +++++++++++++ 3 files changed, 84 insertions(+) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 18ed3d6..5d8f3229 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -68,6 +68,13 @@ #define PORTX_SPEED_SUPPORT_MASK (0x3) #define PORT_SPEED_SUPPORT_GEN1 (0x0) +#define USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x84 + (x) * 0x40) +#define PD_VREG (1 << 6) +#define VREG_LEV(x) (((x) & 0x3) << 7) +#define VREG_DIR(x) (((x) & 0x3) << 11) +#define VREG_DIR_IN VREG_DIR(1) +#define VREG_DIR_OUT VREG_DIR(2) + #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) #define HS_CURR_LEVEL(x) ((x) & 0x3f) #define TERM_SEL BIT(25) @@ -289,6 +296,37 @@ static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy) usb2->powered_on = false; } +static void tegra186_xusb_padctl_utmi_pad_set_protection_level( + struct tegra_xusb_port *port, int level, + enum tegra_vbus_dir dir) +{ + u32 value; + struct tegra_xusb_padctl *padctl = port->padctl; + unsigned int index = port->index; + + value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); + + if (level < 0) { + /* disable pad protection */ + value |= PD_VREG; + value &= ~VREG_LEV(~0); + value &= ~VREG_DIR(~0); + } else { + if (dir == TEGRA_VBUS_SOURCE) + value |= VREG_DIR_OUT; + else if (dir == TEGRA_VBUS_SINK) + value |= VREG_DIR_IN; + + value &= ~PD_VREG; + value &= ~VREG_DIR(~0); + value &= ~VREG_LEV(~0); + value |= VREG_LEV(level); + } + + padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); +} + + static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, bool status) { @@ -931,6 +969,8 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .vbus_override = tegra186_xusb_padctl_vbus_override, .utmi_pad_power_on = tegra_phy_xusb_utmi_pad_power_on, .utmi_pad_power_down = tegra_phy_xusb_utmi_pad_power_down, + .utmi_pad_set_protection_level = + tegra186_xusb_padctl_utmi_pad_set_protection_level, }; #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index 0841564..93517b1 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -74,6 +74,8 @@ #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) +#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x) (((x) & 0x3) << 7) +#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(x) (((x) & 0x3) << 11) #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29) @@ -1116,6 +1118,33 @@ void tegra210_usb2_pad_power_down(struct phy *phy) usb2->powered_on = false; } +static void tegra210_xusb_padctl_utmi_pad_set_protection_level( + struct tegra_xusb_port *port, int level, + enum tegra_vbus_dir dir) +{ + u32 value; + struct tegra_xusb_padctl *padctl = port->padctl; + unsigned int index = port->index; + + value = padctl_readl(padctl, + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); + + if (level < 0) { + /* disable pad protection */ + value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; + value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); + value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0); + } else { + value &= ~XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; + value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0); + value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); + value |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(level); + } + + padctl_writel(padctl, value, + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); +} + static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { @@ -2286,6 +2315,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = { .utmi_port_reset = tegra210_utmi_port_reset, .utmi_pad_power_on = tegra210_usb2_pad_power_on, .utmi_pad_power_down = tegra210_usb2_pad_power_down, + .utmi_pad_set_protection_level = + tegra210_xusb_padctl_utmi_pad_set_protection_level, }; static const char * const tegra210_xusb_padctl_supply_names[] = { diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index ba5ee88..81dd01b 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -259,6 +259,17 @@ to_sata_pad(struct tegra_xusb_pad *pad) */ struct tegra_xusb_port_ops; +/* + * Tegra OTG port VBUS direction: + * default (based on port capability) or + * as source or sink + */ +enum tegra_vbus_dir { + TEGRA_VBUS_DEFAULT, + TEGRA_VBUS_SOURCE, + TEGRA_VBUS_SINK +}; + struct tegra_xusb_port { struct tegra_xusb_padctl *padctl; struct tegra_xusb_lane *lane; @@ -383,6 +394,8 @@ struct tegra_xusb_padctl_ops { int (*utmi_port_reset)(struct phy *phy); void (*utmi_pad_power_on)(struct phy *phy); void (*utmi_pad_power_down)(struct phy *phy); + void (*utmi_pad_set_protection_level)(struct tegra_xusb_port *port, + int max_ua, enum tegra_vbus_dir dir); }; struct tegra_xusb_padctl_soc { From patchwork Wed Mar 18 10:31:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 203137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE788C5ACD7 for ; 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by hqpgpgate101.nvidia.com on Wed, 18 Mar 2020 03:32:10 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Mar 2020 10:32:10 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Mar 2020 10:32:10 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 18 Mar 2020 03:32:09 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , , , Nagarjuna Kristam Subject: [PATCH V1 8/8] phy: tegra: xusb: Enable charger detect for Tegra210 Date: Wed, 18 Mar 2020 16:01:07 +0530 Message-ID: <1584527467-8058-9-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> References: <1584527467-8058-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584527517; bh=uv1fkuSad4kBCRwzQTXQF9RBAm7wcOWJwqJqYeh9Dgk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nlt9uEKHAIpz95lJP5LapcrgBgt5MBTTN31/B/CCweamN7BYeJg/1YQjP7JCYAh5Y 2debWzIoQcLnjabTZ2I6ojb/mckNczHj0CevzfXvM3qP6P9C8oZrZ80JdIjiYCBTcC lehWiEekdhTX0y5KOV4IjSCm/QSTZ4ZXDNT5z6+ulN9+V995YBDfLSWpoGLkYFi2hx IhiQJj+Y4fK858j0g0bJ74UYf7FEMBuT0OYefiO46tKfmnVIyt8tyfhRJrOHWrM/zO 7UIu0yDPg7sgSu6kYUi9y8PVkhhVGYRWAX7jzVM3ZypC+dExD1eCby9lV4B6DC8YOT qUr3iAfDx9Dww== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 SoC supports charger detect, set corresponding soc flag. Signed-off-by: Nagarjuna Kristam --- drivers/phy/tegra/xusb-tegra210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index 93517b1..4c8cb0a 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -2347,6 +2347,7 @@ const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = { .supply_names = tegra210_xusb_padctl_supply_names, .num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names), .need_fake_usb3_port = true, + .charger_detect = true, }; EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);