From patchwork Thu Mar 26 06:48:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 202788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69C5FC2D0E7 for ; Thu, 26 Mar 2020 06:49:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2BEEA2078E for ; Thu, 26 Mar 2020 06:49:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="NXMrBUAF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727775AbgCZGt3 (ORCPT ); Thu, 26 Mar 2020 02:49:29 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:36475 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbgCZGt2 (ORCPT ); Thu, 26 Mar 2020 02:49:28 -0400 Received: by mail-wr1-f68.google.com with SMTP id 31so6358711wrs.3 for ; Wed, 25 Mar 2020 23:49:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fh/TLNefQmL1SjuEsz52lTohOhcfunUSRzYwviSzm/Y=; b=NXMrBUAF2/syHgv1mCPuwpGVTtKZMJfoDeayagoJ4OiDq+ycNTphmqXDZNryHWDKzL MiKDQYxc23B3Ivzm7qW990+m8vIMAkRa+8KPtlqQyAyj8Jkw4gsuzNytrgohAxFJf7KN 4smiFzsPh1N+otMLKkRsPXpH7fV3LkHw5Vi1U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fh/TLNefQmL1SjuEsz52lTohOhcfunUSRzYwviSzm/Y=; b=DMLaN8Jt4tR7hlQfRYm87t4go7wM+WbXdVLD5JdIhUNZt1q2mAj35vCK4lPWHO+Rpq wWMsO+3Wtd3uOwANl6ohulCaQZ5KTvqxy6a9JwY0cYEJLMS8vLRYqXQ7P6T1JN5y6Ic1 aljQCiHwm9vhXjdMA5idniuGEujq27zXG0PxdPgUDEnyJ5Wcr09pAaR4DYzBOmsgjVKE r8vxEZmTgyryHzB7xc0ZU9MvEhnLvzkPD091mdpWmxwnVXirp4ZtMfXmQQrE4XjdNPkB 2/FyKoGG5o6welCjn6Cpqevze2rf1DNBJHz3X08YkZ/jhz20cTXTuI2Lml2JOkrUBsmi lgkw== X-Gm-Message-State: ANhLgQ0kJYYvFB12ByiFz6F/F9bHxGQwnV/yLOfv+L82tIrEoZ3aqdi9 Anf/wjcdUctzDwfqHHjvOHtoNA== X-Google-Smtp-Source: ADFU+vvQ3rK47wJ0+nIAYV8ZUHsndQ8ahJHsCpAmdfrH86NngQd44OZSVGpJqx7/ULYofCL2OrXueg== X-Received: by 2002:adf:e611:: with SMTP id p17mr7444925wrm.212.1585205365864; Wed, 25 Mar 2020 23:49:25 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:25 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 2/6] PCI: iproc: Add INTx support with better modeling Date: Thu, 26 Mar 2020 12:18:42 +0530 Message-Id: <1585205326-25326-3-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ray Jui Add PCIe legacy interrupt INTx support to the iProc PCIe driver by modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, INTD share the same interrupt line connected to the GIC in the system, while the status of each INTx can be obtained through the INTX CSR register. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam Reviewed-by: Andrew Murray --- drivers/pci/controller/pcie-iproc.c | 147 +++++++++++++++++++++++++++++++++++- drivers/pci/controller/pcie-iproc.h | 8 ++ 2 files changed, 153 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 0a468c7..62d8f43 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -270,6 +271,7 @@ enum iproc_pcie_reg { /* enable INTx */ IPROC_PCIE_INTX_EN, + IPROC_PCIE_INTX_CSR, /* outbound address mapping */ IPROC_PCIE_OARR0, @@ -314,6 +316,7 @@ static const u16 iproc_pcie_reg_paxb_bcma[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_LINK_STATUS] = 0xf0c, }; @@ -325,6 +328,7 @@ static const u16 iproc_pcie_reg_paxb[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -341,6 +345,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -846,9 +851,142 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) return link_is_active ? 0 : -ENODEV; } -static void iproc_pcie_enable(struct iproc_pcie *pcie) +static void iproc_pcie_mask_irq(struct irq_data *d) { + struct iproc_pcie *pcie = irq_data_get_irq_chip_data(d); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_EN); + val &= ~(BIT(irqd_to_hwirq(d))); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, val); + spin_unlock_irqrestore(&pcie->intx_lock, flags); +} + +static void iproc_pcie_unmask_irq(struct irq_data *d) +{ + struct iproc_pcie *pcie = irq_data_get_irq_chip_data(d); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_EN); + val |= (BIT(irqd_to_hwirq(d))); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, val); + spin_unlock_irqrestore(&pcie->intx_lock, flags); +} + +static struct irq_chip iproc_pcie_irq_chip = { + .name = "pcie-iproc-intc", + .irq_enable = iproc_pcie_unmask_irq, + .irq_disable = iproc_pcie_mask_irq, + .irq_mask = iproc_pcie_mask_irq, + .irq_unmask = iproc_pcie_unmask_irq, +}; + +static int iproc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &iproc_pcie_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = iproc_pcie_intx_map, +}; + +static void iproc_pcie_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct iproc_pcie *pcie; + struct device *dev; + unsigned long status; + u32 bit, virq; + + chained_irq_enter(chip, desc); + pcie = irq_desc_get_handler_data(desc); + dev = pcie->dev; + + /* go through INTx A, B, C, D until all interrupts are handled */ + do { + status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR); + for_each_set_bit(bit, &status, PCI_NUM_INTX) { + virq = irq_find_mapping(pcie->irq_domain, bit); + if (virq) + generic_handle_irq(virq); + else + dev_err(dev, "unexpected INTx%u\n", bit); + } + } while ((status & SYS_RC_INTX_MASK) != 0); + + chained_irq_exit(chip, desc); +} + +static int iproc_pcie_intx_enable(struct iproc_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node; + int ret; + + /* + * BCMA devices do not map INTx the same way as platform devices. All + * BCMA needs below line to enable INTx + */ iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); + + node = of_get_compatible_child(dev->of_node, "brcm,iproc-intc"); + if (node) + pcie->irq = of_irq_get(node, 0); + + if (!node || pcie->irq <= 0) + return 0; + + spin_lock_init(&pcie->intx_lock); + + /* set IRQ handler */ + irq_set_chained_handler_and_data(pcie->irq, iproc_pcie_isr, pcie); + + /* add IRQ domain for INTx */ + pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, + &intx_domain_ops, pcie); + if (!pcie->irq_domain) { + dev_err(dev, "failed to add INTx IRQ domain\n"); + ret = -ENOMEM; + goto err_rm_handler_data; + } + + return 0; + +err_rm_handler_data: + of_node_put(node); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + + return ret; +} + +static void iproc_pcie_intx_disable(struct iproc_pcie *pcie) +{ + uint32_t offset, virq; + unsigned long flags; + + spin_lock_irqsave(&pcie->intx_lock, flags); + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, 0x0); + spin_unlock_irqrestore(&pcie->intx_lock, flags); + + if (pcie->irq <= 0) + return; + + for (offset = 0; offset < PCI_NUM_INTX; offset++) { + virq = irq_find_mapping(pcie->irq_domain, offset); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(pcie->irq_domain); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); } static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, @@ -1518,7 +1656,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_power_off_phy; } - iproc_pcie_enable(pcie); + ret = iproc_pcie_intx_enable(pcie); + if (ret) { + dev_err(dev, "failed to enable INTx\n"); + goto err_power_off_phy; + } if (IS_ENABLED(CONFIG_PCI_MSI)) if (iproc_pcie_msi_enable(pcie)) @@ -1562,6 +1704,7 @@ int iproc_pcie_remove(struct iproc_pcie *pcie) pci_remove_root_bus(pcie->root_bus); iproc_pcie_msi_disable(pcie); + iproc_pcie_intx_disable(pcie); phy_power_off(pcie->phy); phy_exit(pcie->phy); diff --git a/drivers/pci/controller/pcie-iproc.h b/drivers/pci/controller/pcie-iproc.h index 4f03ea5..787bfba 100644 --- a/drivers/pci/controller/pcie-iproc.h +++ b/drivers/pci/controller/pcie-iproc.h @@ -74,9 +74,13 @@ struct iproc_msi; * @ib: inbound mapping related parameters * @ib_map: outbound mapping region related parameters * + * @irq: interrupt line wired to the generic GIC for INTx + * @irq_domain: IRQ domain for INTx + * * @need_msi_steer: indicates additional configuration of the iProc PCIe * controller is required to steer MSI writes to external interrupt controller * @msi: MSI data + * @intx_lock: spinlock to protect access to INTx related registers */ struct iproc_pcie { struct device *dev; @@ -102,8 +106,12 @@ struct iproc_pcie { struct iproc_pcie_ib ib; const struct iproc_pcie_ib_map *ib_map; + int irq; + struct irq_domain *irq_domain; + bool need_msi_steer; struct iproc_msi *msi; + spinlock_t intx_lock; }; int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); From patchwork Thu Mar 26 06:48:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 202787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0F49C2D0ED for ; Thu, 26 Mar 2020 06:49:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B88E72078E for ; Thu, 26 Mar 2020 06:49:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="NTCciXFr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727851AbgCZGtm (ORCPT ); Thu, 26 Mar 2020 02:49:42 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:51279 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727829AbgCZGtj (ORCPT ); Thu, 26 Mar 2020 02:49:39 -0400 Received: by mail-wm1-f68.google.com with SMTP id c187so5289559wme.1 for ; Wed, 25 Mar 2020 23:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OVO9bKocQbOQc1/49KmYXs6ZePtPJP+gvN7tmpCfXfU=; b=NTCciXFrFmPV8p/p7Se0wRVKia7DN88jm5uIeaKNbyAlic+RsUF+B7vKYzASobnevi jjh8FsbzDj+k+HLucITbhLuKXFdhd8C42j/wwzeBhZpArOU9pu9KKR+Z8TCMjERkhgRO Sc868Vb47o/i+zLzdfPZYJlnzEff1j5Yq1hdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OVO9bKocQbOQc1/49KmYXs6ZePtPJP+gvN7tmpCfXfU=; b=UGi4A603sxR1ENdouZKe0m4mXoZUzIkbCOwG7t8VWxncodtyMfpb8QDSIxH8vMrEIq F9R6uLg2vruxaWGbj/g9Jrj0np4Roo90THkZ568Pl5s9t9aX/XQRWz9J35FSqxuDTRNa XOw8HE1xPrxBTWtPr+aw4vWWMRX3CU5Lx6bGjeWx9KagPunKwVsKQnucxnEH1ec9AGYw YNJTn1VRvUdOrB+Z/gP7sSzr9NVqcXcgFUe/BYqavYJh1jkFr6mv/fbTxQ5I0Opj/jEF cFnxLVUxtTSv6oqHBm0u9zs+oE39tt5vfl0yeHGFRSNBkaeB/4pTvDH/T+1mvnzhhvKp XZtQ== X-Gm-Message-State: ANhLgQ2ILOzVFypw4HXzlZqS7hp6sfb6/1MIzXC8Mb/+kTycMK9lODBf 4GkhM/9AOqofXh0BelcSMu5ItQ== X-Google-Smtp-Source: ADFU+vtPQW2fLjN0Jb2qkD9Ufe80DstHs3fBKYta9Yd//1Td0RCacNfRNc3cx/4XWzWkCZufQuUagQ== X-Received: by 2002:a1c:408b:: with SMTP id n133mr1410962wma.182.1585205376914; Wed, 25 Mar 2020 23:49:36 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:36 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 4/6] arm: dts: Change PCIe INTx mapping for NSP Date: Thu, 26 Mar 2020 12:18:44 +0530 Message-Id: <1585205326-25326-5-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-nsp.dtsi | 45 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index da6d70f..6d73221 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -529,8 +529,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -559,6 +562,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -566,8 +577,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -596,6 +610,14 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie2: pcie@18014000 { @@ -603,8 +625,11 @@ reg = <0x18014000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; linux,pci-domain = <2>; @@ -633,6 +658,14 @@ ; brcm,pcie-msi-inten; }; + + pcie2_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; thermal-zones { From patchwork Thu Mar 26 06:48:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 202786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A325C43331 for ; Thu, 26 Mar 2020 06:49:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 478D820936 for ; Thu, 26 Mar 2020 06:49:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="eOzaFwpa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727830AbgCZGtt (ORCPT ); Thu, 26 Mar 2020 02:49:49 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44572 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727873AbgCZGtt (ORCPT ); Thu, 26 Mar 2020 02:49:49 -0400 Received: by mail-wr1-f68.google.com with SMTP id m17so6302575wrw.11 for ; Wed, 25 Mar 2020 23:49:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0idw5B6PcVqWUxIoMkNt7TgZxctDSgOOI59ozY4oTHM=; b=eOzaFwpapO566KIN7o8CtBngABKyDb0NQEUbuybM+vBuUJ6pSDk6ZXtpd0TBG5lVde ptxih3E2lZ1YpIPRurd1aXbCr2bn4XHT3tOHFPBrImMzJVGQbsVkQvVLIW7OHtnTo8fe OvcoHrjVDGAENbGCR2UwXUevVKaeUk//26t/g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0idw5B6PcVqWUxIoMkNt7TgZxctDSgOOI59ozY4oTHM=; b=QocyNWR0hpXNx3g5luVmJZhPRacBZkNv4uX5vclftBqkHhlroRBpNqajraOF2gkpWD sahVBcD30X5BIWttrPiNksa1eOL7sq4ICTDqTUczmirdMzegZUSVY4D+fIkHb8cNExC2 mrzXcgKcuKmIj8yeCphX70QltmHAEEhgV1woUmtiWdJsg+OXphSr1WUpauBWLievFDAe 1pR5jVXDVO7n5p33zaQPhsO8vWkytF+TXP3kg5M8lbjEy0uRLJhUVVYCuer56psDmman BWOFmBPIjhapjTtKU/Vj7oof90Xt0JgA0jHEQzLd+vAqnXlCSafleUmnx838HQwVaL0n bWrQ== X-Gm-Message-State: ANhLgQ2LXOnYiHy6I+V6BnWSsUo8yfQjkqnIg2jeobmU2/MMwjORch5x sI6E/BnvdAegpaQ+EehQ6/POtA== X-Google-Smtp-Source: ADFU+vsQTR/kVV+uSwHzxwJhKiVFKKuIbCfDf2JW2zqZaGt6ru+SMQ31s/bTu6v99Ao07jypy+Wdrw== X-Received: by 2002:adf:efc9:: with SMTP id i9mr7182823wrp.23.1585205387945; Wed, 25 Mar 2020 23:49:47 -0700 (PDT) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id v21sm2069137wmj.8.2020.03.25.23.49.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Mar 2020 23:49:47 -0700 (PDT) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Andrew Murray , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v5 6/6] arm64: dts: Change PCIe INTx mapping for NS2 Date: Thu, 26 Mar 2020 12:18:46 +0530 Message-Id: <1585205326-25326-7-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> References: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 28 ++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 15f7b0e..489bfd5 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -117,8 +117,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -140,6 +143,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie4: pcie@50020000 { @@ -148,8 +158,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; linux,pci-domain = <4>; @@ -171,6 +184,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie4_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie8: pcie@60c00000 {