From patchwork Mon Mar 30 01:08:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC7F0C2D0ED for ; Mon, 30 Mar 2020 01:11:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1D38206F6 for ; Mon, 30 Mar 2020 01:11:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KP9TxrfH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbgC3BJi (ORCPT ); Sun, 29 Mar 2020 21:09:38 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:44882 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbgC3BJi (ORCPT ); Sun, 29 Mar 2020 21:09:38 -0400 Received: by mail-lj1-f196.google.com with SMTP id p14so16282742lji.11; Sun, 29 Mar 2020 18:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SyPm2KUzhH4yj1dDse11pz3n8NBqlBEAYiobqyRVKu0=; b=KP9TxrfH1Yf2u0M+Qtac+pS0JF1w7wo582/b4iHBGbtBNizsLtp/XIKOhtjx1hlfvL R6t/LkbP+19Yq1EXACCNsU+pkMNzVT4AiHeHn/0lr4pEKcJuPzvoFZ/wxAPjKYR757Ho a5PvbKFSiO3kOk24Yvx2hSWeACsEowJuj/Ub6d7ov70sS9Xbv9XPLdDICyRYEbiAUBj6 S4NuHgx2bM/09Q8WZ8qLgPNP0j9TzqOJajKK7y0Gm0gcGh4ZHlNMhv7R4N872aiyRql6 k5NMBWn9V+dwJ5HXs/lF6jcJ7NZaXjejWFecR//GK+8G8bhe2w94UnhZdEuzhkiLYSCx P4LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SyPm2KUzhH4yj1dDse11pz3n8NBqlBEAYiobqyRVKu0=; b=DXGYEOOeLGdyw2vJ43owk79mJ5pwzlsfJhHie/45RCYRNYNG0Snuvuu/fpAWTqyItu 6Z3EL6uTkpfrM+cGYZCGvb5vgRBgaPEo/sMd8p+qNZvDBQny88mWmdhu9FUc4I+BKWlo q5pj7jHpY6Njmst++PnEBtieqSz6ljYrKGUQMlT9BiecA+zKs9k2Ig7dRWKD0mpbvARz /T3meIDsipDfC4qQnEzPxw4/MFbfx/pM2UZFzqS6G4qu0Ls25YfD6x+wpLdOgkjziLke cHN2w+e4F+NIegqx1gkZcRMigiq9UBKw+JaANVNyk8Zo3CicNsyuKYvo5UiAzz8V7ngp NpVQ== X-Gm-Message-State: AGi0Pub6TotPWsZaT+CN+Ran+pGkO6s1JFM9WMhAnPXyXXDOR7quyot/ cJjT23/eNPxgQGejn7z/Dew= X-Google-Smtp-Source: APiQypLbylsFxaY2bHTyqNbB0g8en9J+rivsuZCDeT0HmvlMHYmh+tF0t5nYIOiPUvnJQ/+pK6AF9A== X-Received: by 2002:a05:651c:310:: with SMTP id a16mr5341055ljp.275.1585530575210; Sun, 29 Mar 2020 18:09:35 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:34 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 01/22] dt-bindings: memory: tegra20: mc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:43 +0300 Message-Id: <20200330010904.27643-2-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Memory controller is interconnected with memory clients and with the external memory controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file . Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 { From patchwork Mon Mar 30 01:08:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFE51C2D0EE for ; Mon, 30 Mar 2020 01:11:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B7B7220786 for ; Mon, 30 Mar 2020 01:11:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pg3NEZBI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728182AbgC3BJm (ORCPT ); Sun, 29 Mar 2020 21:09:42 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:44882 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727941AbgC3BJj (ORCPT ); Sun, 29 Mar 2020 21:09:39 -0400 Received: by mail-lj1-f193.google.com with SMTP id p14so16282792lji.11; Sun, 29 Mar 2020 18:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=THnwhwTdTmg4c86hFlh2qknbtHQvbfTX5IFqa2InF7g=; b=Pg3NEZBItMfCSgDZPKnxTIcXNI+xr/d79Of+mkt+dYMW5wLwo4Ok4roS8EnABFr8to xwy1Sr5/1/6SLKsSJM0j0LjHENfTxhyPHZyEORqb2qJlsTpnub+E1FEtrgj1IRH81M6t dNlP8O6iO/HB5amOL4OsRy3/ZOzQ7DIz7nIygl7Mi5CFGOFhObTMot7NqF94YE0HnILN 6u3UmhkiAOd9W++3BaZ6hFxXzZtoKFDtBLhW0Iw1k/suQz/MPpg7FJucm/Sl5yiKtdWS soby3PljbjCvP0aiph0jIIhGe13/Y2UxSrt1aRvhemGgtUV3to0eaAg5RFUHE6fBl9A2 i9Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=THnwhwTdTmg4c86hFlh2qknbtHQvbfTX5IFqa2InF7g=; b=n1UPFzo9HMSHUCyNNzRMPTy6KtT1oGYci9+6UlgdEdtp5UonSbawd5/ZiedeT5ejdB mMcRR2UGJljjKDWXwLcqQrolkI0IN+ZsqTJIyce7DPOUVHUQ4fPs8zyu3W1o3uJwPaSK UULNabYHpp/+yI0t0qbotZHVH8wvs07a6aDw8dZpvNlPUggDZdkl1dqNcXUTznoxoA8V adiXPq268yjlnUOGJgTb3sUxEQbl+CreR1OfjIy1bJC4juFsp8iOFAxTK9yq7NyiUNHN Zca+OqH0L4Ea8gL5o+ArKlMp6of9uNi3r/aTG9pSUT068nASkUs3r+vq/McxXkXrzhQv Cigw== X-Gm-Message-State: AGi0PuZYdGWHIYNkX1BXGktdANjjHUzATtfx6pSSQEYWMbN+DDJsfSpc MulMBvonJNWdQlvgd3CGOnE= X-Google-Smtp-Source: APiQypKDy2Ro7EQKBqSUe7PyjSLNAnaV0wdFF27xRufe2z5meT1FtGCGpLLX8lEkaMU6PMzGngPfnA== X-Received: by 2002:a05:651c:552:: with SMTP id q18mr5910854ljp.1.1585530576340; Sun, 29 Mar 2020 18:09:36 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:35 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 02/22] dt-bindings: memory: tegra20: emc: Document new interconnect property Date: Mon, 30 Mar 2020 04:08:44 +0300 Message-Id: <20200330010904.27643-3-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns external memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..f51da7662de4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. +- #interconnect-cells : Should be 0. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; + #interconnect-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; From patchwork Mon Mar 30 01:08:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B99C2D0ED for ; Mon, 30 Mar 2020 01:11:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C7C8208FE for ; Mon, 30 Mar 2020 01:11:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O6r9IkP9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728314AbgC3BKy (ORCPT ); Sun, 29 Mar 2020 21:10:54 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:46474 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728162AbgC3BJm (ORCPT ); Sun, 29 Mar 2020 21:09:42 -0400 Received: by mail-lj1-f194.google.com with SMTP id r7so8639692ljg.13; Sun, 29 Mar 2020 18:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M8DwevTofPw/pIdfp/6Cb1DGwp3gDQ5YLGJ2daY85MQ=; b=O6r9IkP9gT5mV1V+BtMChNkuEDA23g0XoMFPgKrfLC+yuksJd+kdDolL2UC22dmopL 8dRNBCHi6LH8QW6N5NcbEtW4SDXNG/MExceo4TisUduBw64+BAVDGYmAAQdz3Be0LHCX mjfTEe6cl0PW4dxXnpcjbBZCxPoJKShkYTanh08JV583adSP2d0dDdfpep8wEeORsAM8 3t2+4S53B48ZvhAP+LympPmE4r/XEcCcZWovbKkeLJ1edLnk05mFThwKS/geusT9gLtm joORZjx+6oCNPKX8VF+NcQNPo3CHNAbP4CcaX37k6Ib9ig2gzPMOUEQK+hmSWJfNDYnu A6Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M8DwevTofPw/pIdfp/6Cb1DGwp3gDQ5YLGJ2daY85MQ=; b=S8STf9i2RCuBseMepJdXP924tTBRYhgd7XXWFXofdOMVO29opKJlMfPVGRjgWTvmf3 v4uKF8y7TVUEiBHAfgVx+mQ1TsnXHGmHmVEy1+kwnSTSKqrJklSuhZ9c7xUVeTM2JeIo QoJ5ivWe44GxIXyo6DZjcznwA2M+UTbjbPJtFuGwK2GjV4ZyzmkhJzBFJNzfXNe1m53e NGrgDWvA05E9g2n9yVSIvg3UoWf0R/2DZQ5/DWR5DcbuFn5GxY6CeO60MLRl7MZ3Bssz 7aSqi+n80wWeOXYS7zh/JEYB++1CgiS/Ew2hqB2m0q1PSMNj3M/Kz2PU5F2CvdnIj3MO Wh5A== X-Gm-Message-State: AGi0PuYgYsOAoshpAArNGCAkQY/iTqPT4Gfif1mtnt+1D6CuyEPK17rc bOXDQdyw8MA+2HqTQOEvsaI= X-Google-Smtp-Source: APiQypLK4tHPYMPuq2cSaOwrtI4imEKVje/al1R0EOqTdKMfdRe0Dz8UxEc++EAv1R+FeNNvPSHdAg== X-Received: by 2002:a2e:7401:: with SMTP id p1mr5574125ljc.279.1585530580279; Sun, 29 Mar 2020 18:09:40 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:39 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 06/22] dt-bindings: memory: tegra20: Add memory client IDs Date: Mon, 30 Mar 2020 04:08:48 +0300 Message-Id: <20200330010904.27643-7-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif From patchwork Mon Mar 30 01:08:49 2020 Content-Type: text/plain; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 07/22] dt-bindings: memory: tegra30: Add memory client IDs Date: Mon, 30 Mar 2020 04:08:49 +0300 Message-Id: <20200330010904.27643-8-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif From patchwork Mon Mar 30 01:08:50 2020 Content-Type: text/plain; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 08/22] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Mon, 30 Mar 2020 04:08:50 +0300 Message-Id: <20200330010904.27643-9-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..974048e83541 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -109,6 +109,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -126,6 +135,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -626,15 +644,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Mon Mar 30 01:08:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 787A2C2D0ED for ; Mon, 30 Mar 2020 01:10:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4DFAD2137B for ; Mon, 30 Mar 2020 01:10:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b5rOMWO+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728365AbgC3BJt (ORCPT ); Sun, 29 Mar 2020 21:09:49 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43322 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728309AbgC3BJs (ORCPT ); Sun, 29 Mar 2020 21:09:48 -0400 Received: by mail-lj1-f195.google.com with SMTP id g27so16239083ljn.10; Sun, 29 Mar 2020 18:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X5VcCh6eWMr9J37Xsf4tsyddBbuWfmiDNSVOMhCKemo=; b=b5rOMWO+3GLaJSJN3NaO51/e76l80sUm8FMWOvxcEKGmHEDls6ROUnIqCrEKrzlJcO N3PpRx/tVJZfG5xi/5b5ATmYpg57lHcfXtTWLU2pgwb5yXTMjOkrvCZ9Nl1gS1mFKzX3 kD9TdbPWtKhhH2vQhwAzD+EOvJTYYqf0u/Bk2V0Ic6UCo//nNh3ZvUwh9HoHo5t4Ercp NLfExVyx2nUkXADa1KDkSPQ90e+ZHK9nfVDyUUwJP+WDwkhDTS7Dk12fFIxsk3f4Y4SU /YvXCgp/d5fV2d45rT0Al30tw44Y5tfC+m34Yhtp7+JIUB6Rz11CxmIDyZpPI1mRJ4NC 0iag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X5VcCh6eWMr9J37Xsf4tsyddBbuWfmiDNSVOMhCKemo=; b=t33klstrevJ5eyGOT9LBoUSKml9Ep8El51yk5moXrcwZP+0mhYXzpuCSltf/crxVLK VrtjnYVsmP2IBfieVuIL8BOiNdhzRQOG6Kyw4wi7RX4Nt84cKJshkvwDCY98CBHFySPq SZq8xze/FNbuFyEcppnuSLQbfYmJ+QzmpOIla6B6fuyOb6fBwpn4ujpZ/oY6afGfLqpN OjcaDVLXlRRd8ZlXWXr4/vh2e1CRXi8fUTr908hd+kBMeADEX88OBTqOT837oYFgqOI0 YAGO0pe6gGv0BWYrKp5g/2qy3gmRyOy0iKOwdfSzXJ2X3C1p451j76MLhZX3B3XJ9M3u agsQ== X-Gm-Message-State: AGi0PubkCScq3nk/kc9XBFIGQ0SDoshl1EYtTlH7UKLzZJODuWW3rFiK +V+7oGosU2iedvEJxMFZrSU= X-Google-Smtp-Source: APiQypKhd7xEcrpcg3+qT1NGCf3mvbNjU1UXyNo0WHIQkeyyHkHVYwc+qMtCRcL9+xBspJXRW6opGQ== X-Received: by 2002:a2e:b4f1:: with SMTP id s17mr3231463ljm.283.1585530585762; Sun, 29 Mar 2020 18:09:45 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 11/22] memory: tegra: Register as interconnect provider Date: Mon, 30 Mar 2020 04:08:53 +0300 Message-Id: <20200330010904.27643-12-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now memory controller is a memory interconnection provider. This allows us to use interconnect API in order to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 118 ++++++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 8 +++ include/soc/tegra/mc.h | 3 + 3 files changed, 129 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..bcf0478c5f5a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -591,6 +591,117 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +static int tegra_mc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_onecell_data *data; + struct icc_node *node; + unsigned int num_nodes; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(mc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + num_nodes = mc->soc->num_clients; + + data = devm_kzalloc(mc->dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + mc->provider.dev = mc->dev; + mc->provider.set = tegra_mc_icc_set; + mc->provider.data = data; + mc->provider.xlate = of_icc_xlate_onecell; + mc->provider.aggregate = tegra_mc_icc_aggregate; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < num_nodes; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); + +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -699,6 +810,13 @@ static int tegra_mc_probe(struct platform_device *pdev) } } + if (IS_ENABLED(CONFIG_INTERCONNECT)) { + err = tegra_mc_interconnect_setup(mc); + if (err) + dev_err(&pdev->dev, "failed to initialize ICC: %d\n", + err); + } + return 0; } diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 957c6eb74ff9..bb13747cd96c 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -114,4 +114,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra's ICC, the values are chosen + * such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_EMC 1000 +#define TEGRA_ICC_EMEM 2000 +#define TEGRA_ICC_MC 3000 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..71de023f9f47 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -7,6 +7,7 @@ #define __SOC_TEGRA_MC_H__ #include +#include #include #include @@ -178,6 +179,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; From patchwork Mon Mar 30 01:08:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DFCCC2D0F1 for ; Mon, 30 Mar 2020 01:10:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1DB7D206F6 for ; Mon, 30 Mar 2020 01:10:40 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:47 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 13/22] memory: tegra20-emc: Continue probing if timings are missing in device-tree Date: Mon, 30 Mar 2020 04:08:55 +0300 Message-Id: <20200330010904.27643-14-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 37 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index ef3abc18a3f4..3a6eb5cc5c29 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -383,6 +383,11 @@ tegra_emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) return of_node_get(dev->of_node); @@ -451,6 +456,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -656,13 +664,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int irq, err; - /* driver has nothing to do in a case of memory timing absence */ - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "EMC device tree node doesn't have memory timings\n"); - return 0; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "interrupt not specified\n"); @@ -670,23 +671,20 @@ static int tegra_emc_probe(struct platform_device *pdev) return irq; } - np = tegra_emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; - err = tegra_emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = tegra_emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) @@ -699,7 +697,8 @@ static int tegra_emc_probe(struct platform_device *pdev) err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, dev_name(&pdev->dev), emc); if (err) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", + irq, err); return err; } From patchwork Mon Mar 30 01:08:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 005FAC2D0E7 for ; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 15/22] memory: tegra20-emc: Create tegra20-devfreq device Date: Mon, 30 Mar 2020 04:08:57 +0300 Message-Id: <20200330010904.27643-16-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The tegra20-devfreq driver provides memory frequency scaling functionality and it uses EMC clock for the scaling. Since tegra20-devfreq is a software driver, the device for the driver needs to be created manually. Let's do it from EMC driver since it provides the clk rate-change functionality. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index a2fcff221659..867cd518b32e 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -838,6 +838,9 @@ static int tegra_emc_probe(struct platform_device *pdev) err); } + if (IS_ENABLED(CONFIG_ARM_TEGRA20_DEVFREQ)) + platform_device_register_simple("tegra20-devfreq", -1, NULL, 0); + return 0; unset_cb: From patchwork Mon Mar 30 01:08:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AC69C43331 for ; Mon, 30 Mar 2020 01:09:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6EA7D20748 for ; Mon, 30 Mar 2020 01:09:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="F7nQYiIa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728494AbgC3BJ4 (ORCPT ); Sun, 29 Mar 2020 21:09:56 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:45491 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728414AbgC3BJy (ORCPT ); Sun, 29 Mar 2020 21:09:54 -0400 Received: by mail-lj1-f195.google.com with SMTP id t17so16314658ljc.12; Sun, 29 Mar 2020 18:09:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UVJ9yyE9K29bjnDrPjNdExCXsCR6dQskyYaw3z4hZMU=; b=F7nQYiIaHaST/H7lR7YpTTa4yZjR1j5Co4uSUtl0sgMnIvNo+M+8NFbhKOUavfmm/K L8+5mcmop875YhcV806hvT5NeLKYsURWzYro4YNtmtxxThG3DBQSRBJ//NBhVa/Okk96 blIweno/JmI2vIHcs2M+M4ocr7ITywTV95X+8QFqxcqUksEe66nTgUuojF5u3kqHxspg 1NjfQIp6xQcVYJng1r5m8wGrvQ5T6aaEVHyUeWn/zN01OXK9w0VoPkj6PF9Aa6GCc3Ip jy5pmksmf3z4WB4zU7CpLFG/vX4jxXtz8+Luys44rcz0vmCYu5W2IWhL6O6ANdqxBHPh KN4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UVJ9yyE9K29bjnDrPjNdExCXsCR6dQskyYaw3z4hZMU=; b=jh8QoreotbNhDq380wY0xiDEH3/1qJ5o5q+mo85zlYEOl47QUe6CfzcaIuB49YntDW v7vuczRCikjU4imnlCAErGdc4RuqNYUQElc8YYueUkUUv+FlFmKrXQYQJeTrZkIYoJS+ R5Z1gJZB1ddPNu28bzFfIU+woGTpix130LG/sZFU31Sh2fY8yzrLBJscw01hLlG0HUTY e9w0lUvVU1j4AfzJoAZuQ4VnjO4Bx1351pw7k+Od+vXbMv/Ibwka3+1xJbJYYdEc0UfZ J14rnEVNHVjgROrFQTs2aCvuWVL+qSkxl9RrVwoVYuS20IL8/UF5Mx4p+n/yustbV99P 3Taw== X-Gm-Message-State: AGi0PuYCLpk6i7m8pSxy64fx2q7n3Z8yA9ogINfeniyY2cgkNB50H0i1 XZnWFMLTLPK8jYdz00TISL8= X-Google-Smtp-Source: APiQypIW79Ltthny3GKQ7ecV2+YYx75UJ9/u2MNZafMabV+CzVs4wTMFMrkD4t5ow3wMmWRR3u68tQ== X-Received: by 2002:a2e:88cb:: with SMTP id a11mr5830944ljk.245.1585530592036; Sun, 29 Mar 2020 18:09:52 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 17/22] memory: tegra30-emc: Register as interconnect provider Date: Mon, 30 Mar 2020 04:08:59 +0300 Message-Id: <20200330010904.27643-18-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now external memory controller is a memory interconnection provider. This allows us to use interconnect API to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30-emc.c | 115 +++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 69698665d431..5a4106173a75 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -327,6 +328,7 @@ struct tegra_emc { struct device *dev; struct tegra_mc *mc; struct notifier_block clk_nb; + struct icc_provider provider; struct clk *clk; void __iomem *regs; unsigned int irq; @@ -1264,6 +1266,112 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node * +emc_of_icc_xlate_onecell(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id == TEGRA_ICC_EMEM) + return node; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long rate = icc_units_to_bps(dst->avg_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + int err; + + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = clk_set_min_rate(emc->clk, rate); + if (err) + return err; + + err = clk_set_rate(emc->clk, rate); + if (err) + return err; + + return 0; +} + +static int emc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + struct icc_node *node; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.xlate = emc_of_icc_xlate_onecell; + emc->provider.aggregate = emc_icc_aggregate; + + err = icc_provider_add(&emc->provider); + if (err) + return err; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); + +del_provider: + icc_provider_del(&emc->provider); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct platform_device *mc; @@ -1344,6 +1452,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + if (IS_ENABLED(CONFIG_INTERCONNECT)) { + err = tegra_emc_interconnect_init(emc); + if (err) + dev_err(&pdev->dev, "failed to initialize ICC: %d\n", + err); + } + return 0; unset_cb: From patchwork Mon Mar 30 01:09:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52775C2D0EE for ; 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[91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 19/22] drm/tegra: dc: Tune up high priority request controls for Tegra20 Date: Mon, 30 Mar 2020 04:09:01 +0300 Message-Id: <20200330010904.27643-20-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra20 has a high-priority-request control that allows to configure when display's memory client should perform read requests with a higher priority (Tegra30+ uses other means like Latency Allowance). This patch changes the controls configuration in order to get a more aggressive memory prefetching, which allows to reliably avoid FIFO underflow when running on a lower memory frequency. This allow us safely drop the memory bandwidth requirement by about two times in a most popular use-cases (only one display active, video overlay inactive, no scaling is done). Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b540ac6ffdc4..564af302a965 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1980,12 +1980,12 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); /* initialize timer */ - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x70) | + WINDOW_B_THRESHOLD(0x30) | WINDOW_C_THRESHOLD(0x70); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0) | + WINDOW_B_THRESHOLD(0) | WINDOW_C_THRESHOLD(0); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | From patchwork Mon Mar 30 01:09:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 202669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9045C2D0E7 for ; Mon, 30 Mar 2020 01:10:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB0E8206F6 for ; Mon, 30 Mar 2020 01:10:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b2Wk9D3n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728567AbgC3BKA (ORCPT ); Sun, 29 Mar 2020 21:10:00 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35046 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728496AbgC3BJ6 (ORCPT ); Sun, 29 Mar 2020 21:09:58 -0400 Received: by mail-lj1-f193.google.com with SMTP id k21so16333361ljh.2; Sun, 29 Mar 2020 18:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vPqDxoQDIqKqbTClKBTFY/GuSR/u7mIa4tRLiNa4khw=; b=b2Wk9D3nd02S1yBEw9VfNDHynpLIG1M19fnbYk4/jKvJE6gnNPd6fx/N9rmAc3h1WJ 0W4cIvLJs4zAoKqlmKnVdTm/7JOiI2jcLsTRUwkogWpygEHuBr7tnXXjJKfMFhu8jCzi YNL7hvXCo/KE3R0Er5Z7L0GQKBMAtnPchxE9PvlT2PvaEMODvg/pRIs15ZIS8BfaXRGD 7qCFNCiqYt3gQNpoHKhM8w1hg292Gntwo2n6q4Cw4K3lczlaaHnH9gTmwB2oxgsIKVAj voa3vghwgz+YfoFB1PGPeHCDGheL2yfhAk0ebY3wbFhZODm3AdVX9swEnK1snhMnnzA5 G39A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vPqDxoQDIqKqbTClKBTFY/GuSR/u7mIa4tRLiNa4khw=; b=U+MSYHN1RurowozjbCw9o9b2SBdqN0fn65m5n44spwJt52qpDkZAnbnV/MAt34AStS c8uKasm4KnwU/CMyg9NrbgmDd0LUCEYC4RS388lCdSG1Stjri4xoF2fDtWxegnxc+fvM w4X0JUShJFzn1PoferHvg47NV3epqQTtA2rFcMIok+Aw5JxoMVA9B2dsrtfbtRwNiNWg Cvi0E6munGHW1GR7E+Yt/QMjNtQTu+NSYYw1WJf3rfnvpkoSYPcbEVDCwTjTXOvDa1jU 7nHi/fsB+nzVhtZdicR8RjSFT4yp282Cijxw5ER/CdV80EaMoLRnWx8yEI4CZ3WhL2nY MGWg== X-Gm-Message-State: AGi0PuZtC5s+NAzpJLlsccWBMM/sWQChDQhHErk7al2HW45cI/3OwOjF bBUwGk0K0u99ayTxT1ccHkQ= X-Google-Smtp-Source: APiQypJKpYIkMoYh3zusIktDsInbffTBT2Ewun8AAXofUfmOfattVIpgibKPpUp/ustF4Zz22EcaHQ== X-Received: by 2002:a2e:740e:: with SMTP id p14mr5716504ljc.290.1585530595270; Sun, 29 Mar 2020 18:09:55 -0700 (PDT) Received: from localhost.localdomain (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.gmail.com with ESMTPSA id f23sm2449005lja.60.2020.03.29.18.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 18:09:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , Georgi Djakov , Rob Herring Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v2 20/22] drm/tegra: dc: Extend debug stats with total number of events Date: Mon, 30 Mar 2020 04:09:02 +0300 Message-Id: <20200330010904.27643-21-digetx@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200330010904.27643-1-digetx@gmail.com> References: <20200330010904.27643-1-digetx@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get reset. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 10 ++++++++++ drivers/gpu/drm/tegra/dc.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 564af302a965..7112f80ff9e8 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1616,6 +1616,11 @@ static int tegra_dc_show_stats(struct seq_file *s, void *data) seq_printf(s, "underflow: %lu\n", dc->stats.underflow); seq_printf(s, "overflow: %lu\n", dc->stats.overflow); + seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); + seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); + seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); + seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); + return 0; } @@ -2187,6 +2192,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): frame end\n", __func__); */ + dc->stats.frames_total++; dc->stats.frames++; } @@ -2195,6 +2201,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); */ drm_crtc_handle_vblank(&dc->base); + dc->stats.vblank_total++; dc->stats.vblank++; } @@ -2202,6 +2209,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): underflow\n", __func__); */ + dc->stats.underflow_total++; dc->stats.underflow++; } @@ -2209,11 +2217,13 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) /* dev_dbg(dc->dev, "%s(): overflow\n", __func__); */ + dc->stats.overflow_total++; dc->stats.overflow++; } if (status & HEAD_UF_INT) { dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); + dc->stats.underflow_total++; dc->stats.underflow++; } diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 3a0ff57c5169..3eb4eddc2288 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -41,6 +41,11 @@ struct tegra_dc_stats { unsigned long vblank; unsigned long underflow; unsigned long overflow; + + unsigned long frames_total; + unsigned long vblank_total; + unsigned long underflow_total; + unsigned long overflow_total; }; struct tegra_windowgroup_soc {