From patchwork Sat Apr 4 01:25:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 202424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B58CEC2BA1E for ; Sat, 4 Apr 2020 01:25:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 854B820737 for ; Sat, 4 Apr 2020 01:25:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ARlB71dG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726426AbgDDBZO (ORCPT ); Fri, 3 Apr 2020 21:25:14 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8288 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbgDDBZO (ORCPT ); Fri, 3 Apr 2020 21:25:14 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Apr 2020 18:24:23 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Apr 2020 18:25:13 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Apr 2020 18:25:13 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 4 Apr 2020 01:25:13 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 4 Apr 2020 01:25:13 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.193]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Apr 2020 18:25:12 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v6 2/9] arm64: tegra: Add reset-cells to mc Date: Fri, 3 Apr 2020 18:25:00 -0700 Message-ID: <1585963507-12610-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585963463; bh=fypsljnYXUQBk09pkBuzFp0S2nxT0B9eauugx/SlCBI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ARlB71dGov+V9JUbaD/x3Jo5bVpb6yNX+zLTzQ4U4Yv3qwmraXukvJu6Ls/Cmb7H/ n0zievMV9fppxmYIfoZhhaUbefzc8MnUCAv7sNG2GjPetFv4TNtZ93GuxbfnZrBG+P Cbieeyx/FmTxWk8tJas77tSORjmCt8XFt6CfPpBUEweTlFcvos8Q5uY74iKQIoadZ6 mlTUsfaexeAndmACh7+6N3Ar0qhUTw6mv6pxft1kgDsm7++ckYNTItjEHhvxeQzVeW GLhsmK4LyPjEEvyl0dFE/frjp3bQg4kCn2urO2Mi4ob04woKWU6s0wNa6+UMPiHAhv mBbFHl9S6KPDA== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 device tree is missing reset-cells property for mc node. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d0eff92..5b1dfd8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -894,6 +894,7 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; sata@70020000 { From patchwork Sat Apr 4 01:25:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 202425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ADCCC2BA1B for ; Sat, 4 Apr 2020 01:25:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5194F2087E for ; Sat, 4 Apr 2020 01:25:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Sv3e/CA4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726186AbgDDBZP (ORCPT ); Fri, 3 Apr 2020 21:25:15 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8295 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726481AbgDDBZP (ORCPT ); Fri, 3 Apr 2020 21:25:15 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Apr 2020 18:24:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 03 Apr 2020 18:25:14 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 03 Apr 2020 18:25:14 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 4 Apr 2020 01:25:14 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 4 Apr 2020 01:25:14 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.193]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Apr 2020 18:25:13 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v6 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Date: Fri, 3 Apr 2020 18:25:01 -0700 Message-ID: <1585963507-12610-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585963464; bh=FfGJH9b8JGj6Sguul3LNMexpCVjUbOXcObIX96zc9Fo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Sv3e/CA4jCeJq0ggWwSHMwhhjHI8Wwa/4tPLVRK4J/zJW+HuyKazF7oVXfeOz+aSM YALWBXNhkgJdA4jScM1Z/m4fAritfCnQHD9QGFFb5IB3i3C7iKN6D93WYSmqE6Hi3y 5wtqxyV472fdmmaPDR2KGL6ELBzuiH/zBG+PPdoIw7uUTw6yP0ibul6iMewrGzInai xs8e+XamPS3cftmEqSfNJBtMrUTqxfFqHrreLl7HIo78dYBj/X8Fm3z+DTosXwtGoP c82oI38EpEZn0Scm25zX0w5NkWqx+eJafk4Fc8EtykowkPdWzNhot4APQuRuJSYU8w ZhAB3ru7FbdWg== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 uses PLLD out internally for CSI TPG. This patch adds clk id for this CSI TPG clock from PLLD. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b..d8909e0 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,7 +351,7 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ +#define TEGRA210_CLK_CSI_TPG 320 /* 321 */ #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 From patchwork Sat Apr 4 01:25:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 202426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C37FC2BA1A for ; Sat, 4 Apr 2020 01:25:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5392D2087E for ; Sat, 4 Apr 2020 01:25:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="nynG8ud/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727121AbgDDBZS (ORCPT ); Fri, 3 Apr 2020 21:25:18 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9125 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726620AbgDDBZQ (ORCPT ); Fri, 3 Apr 2020 21:25:16 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Apr 2020 18:23:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Apr 2020 18:25:15 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Apr 2020 18:25:15 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 4 Apr 2020 01:25:15 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 4 Apr 2020 01:25:15 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.193]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Apr 2020 18:25:14 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v6 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Fri, 3 Apr 2020 18:25:02 -0700 Message-ID: <1585963507-12610-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585963416; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=nynG8ud/22Fkty41DAxBdfnGLZBOJybm/lSHq+7gvgpWlKqOTpKU5N4ktEhDNrNER /5bPXKBFYIt0dQ/+fuTuJ9MpfIEsroGeLvOnje1YF0DPLNe0a4NOEWDPhuXqjjBh/K GTrcYDTtMnPeMg+OJK9FaCmgEUU62h+VNyQ5qOJCVrAoWQZxIVSV9+i4roxMKpN2hy Y3TXu/R++le3VUSLdANXfz8CrjSu6iZ8yetgV3f92X2jOD8+Wp1wbGRafg0IEIlZl3 u4x3vBDzMYGY0TcDT9U3MZwJYCQLCyTrIGc/v7gTF7DUNXHB3KkOokirdC1Qhz57T/ 017hplxreqNtQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, From patchwork Sat Apr 4 01:25:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 202427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4A97C2BA1A for ; Sat, 4 Apr 2020 01:25:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4DD920737 for ; Sat, 4 Apr 2020 01:25:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="bzmcSmNV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726659AbgDDBZh (ORCPT ); Fri, 3 Apr 2020 21:25:37 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:8305 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726403AbgDDBZV (ORCPT ); Fri, 3 Apr 2020 21:25:21 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Apr 2020 18:24:30 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Apr 2020 18:25:20 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Apr 2020 18:25:20 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 4 Apr 2020 01:25:20 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 4 Apr 2020 01:25:19 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.193]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Apr 2020 18:25:19 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v6 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Date: Fri, 3 Apr 2020 18:25:06 -0700 Message-ID: <1585963507-12610-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585963470; bh=L8ndW8+Uxj7JNOHxtp4ihFZmkMPUeCnBtUyBLpK+IFo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=bzmcSmNVAroSrnmECtU5PBrQ2Eh/fvjnZW4I7aH7hOlnKB/iTdeSDAjm7wE9No/gq en/JScX0+Ew1uDRLUb429P8yxFh7F0VRCtOCb7+npCTF/B/ZTTBW41nUSwsCfVkxXu y8sfrdVcb9ART2NXmkDODVVIVAtuT1F5vVRRwowBgucMm8rNfQdEFvCU6EzTj4ZhJP ZOaUGVnNs5Z4tsu4y0fj6h4q0sCpoB1Ggk4k5Jm242O+CejGEJyCjaOuVnfFp7fut2 fZERG4hxdALX/MyNHWGnR18PmTm9O/beExheOhRfpGcrlCoNUJcdqo0UEZsk1HXZBv hLACOS5eTiMPw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds ID for Tegra210 VI controller reset to use with device tree. Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/reset/tegra210-car.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h index 9dc84ec..8755946 100644 --- a/include/dt-bindings/reset/tegra210-car.h +++ b/include/dt-bindings/reset/tegra210-car.h @@ -10,5 +10,6 @@ #define TEGRA210_RESET(x) (7 * 32 + (x)) #define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) #define TEGRA210_RST_ADSP TEGRA210_RESET(1) +#define TEGRA210_RST_VI 20 #endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ From patchwork Sat Apr 4 01:25:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 202428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B20EC43331 for ; Sat, 4 Apr 2020 01:25:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 61FEB214D8 for ; Sat, 4 Apr 2020 01:25:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="DrG94gA2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726380AbgDDBZX (ORCPT ); Fri, 3 Apr 2020 21:25:23 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18810 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727254AbgDDBZW (ORCPT ); Fri, 3 Apr 2020 21:25:22 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Apr 2020 18:25:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 03 Apr 2020 18:25:21 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 03 Apr 2020 18:25:21 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 4 Apr 2020 01:25:21 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 4 Apr 2020 01:25:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.164.193]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Apr 2020 18:25:20 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v6 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Fri, 3 Apr 2020 18:25:07 -0700 Message-ID: <1585963507-12610-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> References: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585963508; bh=yB3b29VbNFtTvMcPZCMVxLppaVECoZp9WEY70dWiuUY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DrG94gA21AI8HLj25IoD73oQAFXxnrKG3J01umfSi+5L3OB/WmOuIKTGc4Ju2otz2 4+y9MRHp8I/U0QjlubB88nz3sl8Poe6gkpnr9M2AOUIqFier0bjUjThMx+iCmZaYmA vuupZmcfV+6gdxVeDG6PzGPFC68EyhDL+qIEdZKJQgIgZUaRQl5cqP9T3Bw9mkOBIj 2fsKMoekOBrI7D7cBaUhGYBoTREtGQeQH+zU2vW5aYTOG23AXBE0Mwi9QUW5/IQ5/F 9spn/WOcrVgx7UFjUmsdL+Fqujq2uOnjDU0I2+arQ9gPHuOorRtf516BUj0Ne5BS/q 7YjcIQy4b9cFQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..cad42a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -839,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {