From patchwork Thu Aug 17 10:11:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 110310 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1982738qge; Thu, 17 Aug 2017 03:14:04 -0700 (PDT) X-Received: by 10.98.150.138 with SMTP id s10mr4694163pfk.80.1502964844348; Thu, 17 Aug 2017 03:14:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502964844; cv=none; d=google.com; s=arc-20160816; b=RUVL2NBk8Q5FEuVRck82AX+4kf7WI8bY6Xp+wamVQfqoh0ish0th9nE1KlCNptPhNY u1Hwj13cDlbaBBeerLxlrLoefARfW7Beodl9VHckewS7muwFxr+dW4BYgb+qw1ORAoRf /fWjTtIL91Lg1K0ZbntVYqC5oXcy8ngGClhfbHV8gavQjkEE2E/iKQMap6YMj3mbisIi qR6GmYiTxF9KE1w0jmaaODgMwylageY4cjHD4xQpOL//lDyM1vfoLT3vibL7RXSUpRR4 Jw+5vcX8ehrn9mHmft6zs5ooMmRpSmw35xd3rbRnc/1iBMt//jpZ+JTDcz8rYs7myxm8 St7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=00qdBoikjgo55bTM7Vt/weViT5linwNM92EZItq34RI=; b=rMjSpwrUWHJd2bX0pPqj+VpgixvCFntx8jV6txQM+hkkIPr50hUUuOOPuJ9YcYMsks ODCS73fC/bhI8EjSt/BpGJhXFeY0KXXHyedu3rN1obvLpxhcsUgwRprLsIlDleC0KFSU f32BerwiBJpG+erreIA9rORjIQoERlTLcIMtfoRM2MjMA3C5L7Ul7+KhXJ/muIV/D8ch XiJHMCONhdpcnqzHPZ/Idj3lzVuHiTIoo6Kuxt28nyr3DCB2Jsf8EtoK8UzGwppDHf3L 6UgLBGM+U4i6k987jPpEh5epAkgRdrZS7Wade30SwA4WHsffEI6NTNsYakihP5erk7vk 9GAQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6si1922246pff.340.2017.08.17.03.14.03; Thu, 17 Aug 2017 03:14:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752274AbdHQKN3 (ORCPT + 26 others); Thu, 17 Aug 2017 06:13:29 -0400 Received: from mx2.suse.de ([195.135.220.15]:42658 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752322AbdHQKLt (ORCPT ); Thu, 17 Aug 2017 06:11:49 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 3C9BEAF7D; Thu, 17 Aug 2017 10:11:48 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org Subject: [RFC 2/3] arm64: dts: realtek: Add irq mux to RTD1295 Date: Thu, 17 Aug 2017 12:11:39 +0200 Message-Id: <20170817101140.32000-3-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170817101140.32000-1-afaerber@suse.de> References: <20170817101140.32000-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update UART nodes with interrupts. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.12.3 diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 2d2d84b573e3..77063e984db9 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -112,6 +112,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@98007000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x98007000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@98007088 { compatible = "realtek,rtd1295-reset"; reg = <0x98007088 0x4>; @@ -124,16 +132,28 @@ reg-shift = <2>; reg-io-width = <4>; clock-frequency = <27000000>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; status = "disabled"; }; + irq_mux: interrupt-controller@9801b000 { + compatible = "realtek,rtd1295-irq-mux"; + reg = <0x9801b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@9801b200 { compatible = "snps,dw-apb-uart"; reg = <0x9801b200 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <432000000>; + interrupt-parent = <&irq_mux>; + interrupts = <3>, <5>; resets = <&reset2 RTD1295_RSTN_UR1>; status = "disabled"; }; @@ -144,6 +164,8 @@ reg-shift = <2>; reg-io-width = <4>; clock-frequency = <432000000>; + interrupt-parent = <&irq_mux>; + interrupts = <8>, <13>; resets = <&reset2 RTD1295_RSTN_UR2>; status = "disabled"; }; From patchwork Thu Aug 17 10:11:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 110311 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1982956qge; Thu, 17 Aug 2017 03:14:17 -0700 (PDT) X-Received: by 10.98.33.84 with SMTP id h81mr4724949pfh.302.1502964857528; Thu, 17 Aug 2017 03:14:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502964857; cv=none; d=google.com; s=arc-20160816; b=hEtsUGFWUtQk/FtnN8/T6Ba4NjdFOfoXPJtvJh/yIksqIdyuN0KqtrJBcXjNz0Sil7 klP9YrCNbb5nUocnLA4DKRYXEczJ1ZzLkEk49pWgGwgSSyxnNNLbfmTHO6Vce6j6UVnT OlG7FVQqaftFJ7x0qCYdoyt5LbzhEJP84ZqzYN5a7grKx4uR9oss0AKJm3SdI+fnZ3fG RKL7MUjEE4Mq4kDoeuJEAZDYgsAtw/fnmE+7yCLiN2cHrCwgB0GO2yjy00MK5fTc4um0 glmJZ+XkafFx3lxggH8lQCQjYJk+aVih0IAJMfr8UapcWX6G47iO8wnFa93AFgfY/byW TsPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=KMSnnXzVP1VNpghJnFtGmqi7u/3sVJ3Mol2CfGSla5w=; b=OsNPOU94uiamgifsOBqCh/zJi/dAD4Mq7RzaTu/Ve1iWD6XA+FDa0drDtuxTict+9+ 4dHKEOBc4ZgA7FQE2Z7pV5kkoJtZOVi30DdnG0xIO8MOOQjpthIVFqvU9RlpjDslDnYg 43pq+8R39cIyK0rrxedGlpS3lEHE6ekTHvm7Cn/15SApJ+3KrwLH+oKUK3ihX1WJjaP9 orWt/so7arVD5FxnF4j6PyEsDU05zb40MtcDMGDt3bg40qSiNgdHv2ox1fK8pkBwKA1W Pg4aQU4Or/WAit6EWmHEYhyp0O85asoUO+kEw9B01M4t1UKNbOxtmuvFJEsBH78jY4q5 1nog== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i8si2045353plk.794.2017.08.17.03.14.17; Thu, 17 Aug 2017 03:14:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752165AbdHQKN1 (ORCPT + 26 others); Thu, 17 Aug 2017 06:13:27 -0400 Received: from mx2.suse.de ([195.135.220.15]:42674 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752376AbdHQKLu (ORCPT ); Thu, 17 Aug 2017 06:11:50 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5CD03AF81; Thu, 17 Aug 2017 10:11:49 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [RFC 3/3] irqchip: Add Realtek RTD1295 mux driver Date: Thu, 17 Aug 2017 12:11:40 +0200 Message-Id: <20170817101140.32000-4-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170817101140.32000-1-afaerber@suse.de> References: <20170817101140.32000-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This irq mux driver is derived from the RTD1295 vendor DT and assumes a linear mapping between intr_en and intr_status registers. Code for RTD119x indicates this may not always be the case (i2c_3). The register initialization was copied from QNAP's mach-rtk119x/rtk_irq_mux.c as a boot fix, without full insights into what exactly this is changing (TODO). Signed-off-by: Andreas Färber --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rtd119x-mux.c | 201 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 drivers/irqchip/irq-rtd119x-mux.c -- 2.12.3 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e88d856cc09c..46202a0b7d96 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd119x-mux.o diff --git a/drivers/irqchip/irq-rtd119x-mux.c b/drivers/irqchip/irq-rtd119x-mux.c new file mode 100644 index 000000000000..c6c1ba126bf3 --- /dev/null +++ b/drivers/irqchip/irq-rtd119x-mux.c @@ -0,0 +1,201 @@ +/* + * Realtek RTD129x IRQ mux + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct rtd119x_irq_mux_info { + unsigned intr_status; + unsigned intr_en; +}; + +struct rtd119x_irq_mux_data { + void __iomem *intr_status; + void __iomem *intr_en; + int irq; + struct irq_domain *domain; + spinlock_t lock; +}; + +static void rtd119x_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd119x_irq_mux_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 intr_en, intr_status, status; + int ret; + + chained_irq_enter(chip, desc); + + spin_lock(&data->lock); + intr_en = readl(data->intr_en); + intr_status = readl(data->intr_status); + spin_unlock(&data->lock); + + status = intr_status & intr_en; + if (status != 0) { + unsigned irq = __ffs(status); + ret = generic_handle_irq(irq_find_mapping(data->domain, irq)); + if (ret == 0) { + spin_lock(&data->lock); + intr_status = readl(data->intr_status); + intr_status |= BIT(irq - 1); + writel(intr_status, data->intr_status); + spin_unlock(&data->lock); + } + } + + chained_irq_exit(chip, desc); +} + +static void rtd119x_mux_mask_irq(struct irq_data *data) +{ + struct rtd119x_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + u32 intr_status; + + intr_status = readl(mux_data->intr_status); + intr_status |= BIT(data->hwirq); + writel(intr_status, mux_data->intr_status); +} + +static void rtd119x_mux_unmask_irq(struct irq_data *data) +{ + struct rtd119x_irq_mux_data *mux_data = irq_data_get_irq_chip_data(data); + u32 intr_en; + + intr_en = readl(mux_data->intr_en); + intr_en |= BIT(data->hwirq); + writel(intr_en, mux_data->intr_en); +} + +static int rtd119x_mux_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct rtd119x_irq_mux_data *mux_data = irq_data_get_irq_chip_data(d); + struct irq_chip *chip = irq_get_chip(mux_data->irq); + struct irq_data *data = irq_get_irq_data(mux_data->irq); + + if (chip && chip->irq_set_affinity) + return chip->irq_set_affinity(data, mask_val, force); + + return -EINVAL; +} + +static struct irq_chip rtd119x_mux_irq_chip = { + .name = "rtd119x-mux", + .irq_mask = rtd119x_mux_mask_irq, + .irq_unmask = rtd119x_mux_unmask_irq, + .irq_set_affinity = rtd119x_mux_set_affinity, +}; + +static int rtd119x_mux_irq_domain_xlate(struct irq_domain *d, + struct device_node *controller, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (irq_domain_get_of_node(d) != controller) + return -EINVAL; + + if (intsize < 1) + return -EINVAL; + + *out_hwirq = intspec[0]; + *out_type = 0; + + return 0; +} + +static int rtd119x_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd119x_irq_mux_data *data = d->host_data; + + irq_set_chip_and_handler(irq, &rtd119x_mux_irq_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_probe(irq); + + return 0; +} + +static struct irq_domain_ops rtd119x_mux_irq_domain_ops = { + .xlate = rtd119x_mux_irq_domain_xlate, + .map = rtd119x_mux_irq_domain_map, +}; + +static int __init rtd119x_irq_mux_init(struct device_node *node, + struct device_node *parent, + const struct rtd119x_irq_mux_info *info) +{ + struct rtd119x_irq_mux_data *data; + void __iomem *base; + u32 val; + + base = of_iomap(node, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->intr_status = base + info->intr_status; + data->intr_en = base + info->intr_en; + + data->irq = irq_of_parse_and_map(node, 0); + if (data->irq <= 0) { + kfree(data); + return -EINVAL; + } + + data->domain = irq_domain_add_linear(node, 32, + &rtd119x_mux_irq_domain_ops, data); + if (!data->domain) { + kfree(data); + return -ENOMEM; + } + + /* TODO Investigate why these are necessary (from downstream rtk119x rtk_irq_mux.c) */ + val = readl(data->intr_en); + val &= ~BIT(2); + writel(val, data->intr_en); + + writel(BIT(2), data->intr_status); + + irq_set_chained_handler_and_data(data->irq, rtd119x_mux_irq_handle, data); + + return 0; +} + +static const struct rtd119x_irq_mux_info rtd1295_iso_irq_mux_info = { + .intr_status = 0x0, + .intr_en = 0x40, +}; + +static int __init rtd1295_iso_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + return rtd119x_irq_mux_init(node, parent, &rtd1295_iso_irq_mux_info); +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1295_iso_irq_mux_init); + +static const struct rtd119x_irq_mux_info rtd1295_irq_mux_info = { + .intr_status = 0xc, + .intr_en = 0x80, +}; + +static int __init rtd1295_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + return rtd119x_irq_mux_init(node, parent, &rtd1295_irq_mux_info); +} +IRQCHIP_DECLARE(rtd1295_mux, "realtek,rtd1295-irq-mux", rtd1295_irq_mux_init);